19703d9d7SCatalin Marinas /* 29703d9d7SCatalin Marinas * Based on arch/arm/kernel/setup.c 39703d9d7SCatalin Marinas * 49703d9d7SCatalin Marinas * Copyright (C) 1995-2001 Russell King 59703d9d7SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 69703d9d7SCatalin Marinas * 79703d9d7SCatalin Marinas * This program is free software; you can redistribute it and/or modify 89703d9d7SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 99703d9d7SCatalin Marinas * published by the Free Software Foundation. 109703d9d7SCatalin Marinas * 119703d9d7SCatalin Marinas * This program is distributed in the hope that it will be useful, 129703d9d7SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 139703d9d7SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 149703d9d7SCatalin Marinas * GNU General Public License for more details. 159703d9d7SCatalin Marinas * 169703d9d7SCatalin Marinas * You should have received a copy of the GNU General Public License 179703d9d7SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 189703d9d7SCatalin Marinas */ 199703d9d7SCatalin Marinas 209703d9d7SCatalin Marinas #include <linux/export.h> 219703d9d7SCatalin Marinas #include <linux/kernel.h> 229703d9d7SCatalin Marinas #include <linux/stddef.h> 239703d9d7SCatalin Marinas #include <linux/ioport.h> 249703d9d7SCatalin Marinas #include <linux/delay.h> 259703d9d7SCatalin Marinas #include <linux/utsname.h> 269703d9d7SCatalin Marinas #include <linux/initrd.h> 279703d9d7SCatalin Marinas #include <linux/console.h> 289703d9d7SCatalin Marinas #include <linux/bootmem.h> 299703d9d7SCatalin Marinas #include <linux/seq_file.h> 309703d9d7SCatalin Marinas #include <linux/screen_info.h> 319703d9d7SCatalin Marinas #include <linux/init.h> 329703d9d7SCatalin Marinas #include <linux/kexec.h> 339703d9d7SCatalin Marinas #include <linux/crash_dump.h> 349703d9d7SCatalin Marinas #include <linux/root_dev.h> 35de79a64dSCatalin Marinas #include <linux/clk-provider.h> 369703d9d7SCatalin Marinas #include <linux/cpu.h> 379703d9d7SCatalin Marinas #include <linux/interrupt.h> 389703d9d7SCatalin Marinas #include <linux/smp.h> 399703d9d7SCatalin Marinas #include <linux/fs.h> 409703d9d7SCatalin Marinas #include <linux/proc_fs.h> 419703d9d7SCatalin Marinas #include <linux/memblock.h> 429703d9d7SCatalin Marinas #include <linux/of_fdt.h> 43d6bafb9bSCatalin Marinas #include <linux/of_platform.h> 449703d9d7SCatalin Marinas 459703d9d7SCatalin Marinas #include <asm/cputype.h> 469703d9d7SCatalin Marinas #include <asm/elf.h> 479703d9d7SCatalin Marinas #include <asm/cputable.h> 489703d9d7SCatalin Marinas #include <asm/sections.h> 499703d9d7SCatalin Marinas #include <asm/setup.h> 504c7aa002SJavi Merino #include <asm/smp_plat.h> 519703d9d7SCatalin Marinas #include <asm/cacheflush.h> 529703d9d7SCatalin Marinas #include <asm/tlbflush.h> 539703d9d7SCatalin Marinas #include <asm/traps.h> 549703d9d7SCatalin Marinas #include <asm/memblock.h> 55e790f1deSWill Deacon #include <asm/psci.h> 569703d9d7SCatalin Marinas 579703d9d7SCatalin Marinas unsigned int processor_id; 589703d9d7SCatalin Marinas EXPORT_SYMBOL(processor_id); 599703d9d7SCatalin Marinas 6025804e6aSSteve Capper unsigned long elf_hwcap __read_mostly; 619703d9d7SCatalin Marinas EXPORT_SYMBOL_GPL(elf_hwcap); 629703d9d7SCatalin Marinas 639703d9d7SCatalin Marinas static const char *cpu_name; 649703d9d7SCatalin Marinas static const char *machine_name; 659703d9d7SCatalin Marinas phys_addr_t __fdt_pointer __initdata; 669703d9d7SCatalin Marinas 679703d9d7SCatalin Marinas /* 689703d9d7SCatalin Marinas * Standard memory resources 699703d9d7SCatalin Marinas */ 709703d9d7SCatalin Marinas static struct resource mem_res[] = { 719703d9d7SCatalin Marinas { 729703d9d7SCatalin Marinas .name = "Kernel code", 739703d9d7SCatalin Marinas .start = 0, 749703d9d7SCatalin Marinas .end = 0, 759703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 769703d9d7SCatalin Marinas }, 779703d9d7SCatalin Marinas { 789703d9d7SCatalin Marinas .name = "Kernel data", 799703d9d7SCatalin Marinas .start = 0, 809703d9d7SCatalin Marinas .end = 0, 819703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 829703d9d7SCatalin Marinas } 839703d9d7SCatalin Marinas }; 849703d9d7SCatalin Marinas 859703d9d7SCatalin Marinas #define kernel_code mem_res[0] 869703d9d7SCatalin Marinas #define kernel_data mem_res[1] 879703d9d7SCatalin Marinas 889703d9d7SCatalin Marinas void __init early_print(const char *str, ...) 899703d9d7SCatalin Marinas { 909703d9d7SCatalin Marinas char buf[256]; 919703d9d7SCatalin Marinas va_list ap; 929703d9d7SCatalin Marinas 939703d9d7SCatalin Marinas va_start(ap, str); 949703d9d7SCatalin Marinas vsnprintf(buf, sizeof(buf), str, ap); 959703d9d7SCatalin Marinas va_end(ap); 969703d9d7SCatalin Marinas 979703d9d7SCatalin Marinas printk("%s", buf); 989703d9d7SCatalin Marinas } 999703d9d7SCatalin Marinas 1009703d9d7SCatalin Marinas static void __init setup_processor(void) 1019703d9d7SCatalin Marinas { 1029703d9d7SCatalin Marinas struct cpu_info *cpu_info; 1039703d9d7SCatalin Marinas 1049703d9d7SCatalin Marinas /* 1059703d9d7SCatalin Marinas * locate processor in the list of supported processor 1069703d9d7SCatalin Marinas * types. The linker builds this table for us from the 1079703d9d7SCatalin Marinas * entries in arch/arm/mm/proc.S 1089703d9d7SCatalin Marinas */ 1099703d9d7SCatalin Marinas cpu_info = lookup_processor_type(read_cpuid_id()); 1109703d9d7SCatalin Marinas if (!cpu_info) { 1119703d9d7SCatalin Marinas printk("CPU configuration botched (ID %08x), unable to continue.\n", 1129703d9d7SCatalin Marinas read_cpuid_id()); 1139703d9d7SCatalin Marinas while (1); 1149703d9d7SCatalin Marinas } 1159703d9d7SCatalin Marinas 1169703d9d7SCatalin Marinas cpu_name = cpu_info->cpu_name; 1179703d9d7SCatalin Marinas 1189703d9d7SCatalin Marinas printk("CPU: %s [%08x] revision %d\n", 1199703d9d7SCatalin Marinas cpu_name, read_cpuid_id(), read_cpuid_id() & 15); 1209703d9d7SCatalin Marinas 1219703d9d7SCatalin Marinas sprintf(init_utsname()->machine, "aarch64"); 1229703d9d7SCatalin Marinas elf_hwcap = 0; 1239703d9d7SCatalin Marinas } 1249703d9d7SCatalin Marinas 1259703d9d7SCatalin Marinas static void __init setup_machine_fdt(phys_addr_t dt_phys) 1269703d9d7SCatalin Marinas { 127d5189cc5SRob Herring if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { 1289703d9d7SCatalin Marinas early_print("\n" 1299703d9d7SCatalin Marinas "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" 130d5189cc5SRob Herring "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" 1319703d9d7SCatalin Marinas "\nPlease check your bootloader.\n", 132d5189cc5SRob Herring dt_phys, phys_to_virt(dt_phys)); 1339703d9d7SCatalin Marinas 1349703d9d7SCatalin Marinas while (true) 1359703d9d7SCatalin Marinas cpu_relax(); 1369703d9d7SCatalin Marinas } 1379703d9d7SCatalin Marinas 138f2b99bccSRob Herring machine_name = of_flat_dt_get_machine_name(); 1399703d9d7SCatalin Marinas } 1409703d9d7SCatalin Marinas 1419703d9d7SCatalin Marinas /* 1429703d9d7SCatalin Marinas * Limit the memory size that was specified via FDT. 1439703d9d7SCatalin Marinas */ 1449703d9d7SCatalin Marinas static int __init early_mem(char *p) 1459703d9d7SCatalin Marinas { 1469703d9d7SCatalin Marinas phys_addr_t limit; 1479703d9d7SCatalin Marinas 1489703d9d7SCatalin Marinas if (!p) 1499703d9d7SCatalin Marinas return 1; 1509703d9d7SCatalin Marinas 1519703d9d7SCatalin Marinas limit = memparse(p, &p) & PAGE_MASK; 1529703d9d7SCatalin Marinas pr_notice("Memory limited to %lldMB\n", limit >> 20); 1539703d9d7SCatalin Marinas 1549703d9d7SCatalin Marinas memblock_enforce_memory_limit(limit); 1559703d9d7SCatalin Marinas 1569703d9d7SCatalin Marinas return 0; 1579703d9d7SCatalin Marinas } 1589703d9d7SCatalin Marinas early_param("mem", early_mem); 1599703d9d7SCatalin Marinas 1609703d9d7SCatalin Marinas static void __init request_standard_resources(void) 1619703d9d7SCatalin Marinas { 1629703d9d7SCatalin Marinas struct memblock_region *region; 1639703d9d7SCatalin Marinas struct resource *res; 1649703d9d7SCatalin Marinas 1659703d9d7SCatalin Marinas kernel_code.start = virt_to_phys(_text); 1669703d9d7SCatalin Marinas kernel_code.end = virt_to_phys(_etext - 1); 1679703d9d7SCatalin Marinas kernel_data.start = virt_to_phys(_sdata); 1689703d9d7SCatalin Marinas kernel_data.end = virt_to_phys(_end - 1); 1699703d9d7SCatalin Marinas 1709703d9d7SCatalin Marinas for_each_memblock(memory, region) { 1719703d9d7SCatalin Marinas res = alloc_bootmem_low(sizeof(*res)); 1729703d9d7SCatalin Marinas res->name = "System RAM"; 1739703d9d7SCatalin Marinas res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 1749703d9d7SCatalin Marinas res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 1759703d9d7SCatalin Marinas res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 1769703d9d7SCatalin Marinas 1779703d9d7SCatalin Marinas request_resource(&iomem_resource, res); 1789703d9d7SCatalin Marinas 1799703d9d7SCatalin Marinas if (kernel_code.start >= res->start && 1809703d9d7SCatalin Marinas kernel_code.end <= res->end) 1819703d9d7SCatalin Marinas request_resource(res, &kernel_code); 1829703d9d7SCatalin Marinas if (kernel_data.start >= res->start && 1839703d9d7SCatalin Marinas kernel_data.end <= res->end) 1849703d9d7SCatalin Marinas request_resource(res, &kernel_data); 1859703d9d7SCatalin Marinas } 1869703d9d7SCatalin Marinas } 1879703d9d7SCatalin Marinas 1884c7aa002SJavi Merino u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 1894c7aa002SJavi Merino 1909703d9d7SCatalin Marinas void __init setup_arch(char **cmdline_p) 1919703d9d7SCatalin Marinas { 1929703d9d7SCatalin Marinas setup_processor(); 1939703d9d7SCatalin Marinas 1949703d9d7SCatalin Marinas setup_machine_fdt(__fdt_pointer); 1959703d9d7SCatalin Marinas 1969703d9d7SCatalin Marinas init_mm.start_code = (unsigned long) _text; 1979703d9d7SCatalin Marinas init_mm.end_code = (unsigned long) _etext; 1989703d9d7SCatalin Marinas init_mm.end_data = (unsigned long) _edata; 1999703d9d7SCatalin Marinas init_mm.brk = (unsigned long) _end; 2009703d9d7SCatalin Marinas 2019703d9d7SCatalin Marinas *cmdline_p = boot_command_line; 2029703d9d7SCatalin Marinas 2039703d9d7SCatalin Marinas parse_early_param(); 2049703d9d7SCatalin Marinas 2059703d9d7SCatalin Marinas arm64_memblock_init(); 2069703d9d7SCatalin Marinas 2079703d9d7SCatalin Marinas paging_init(); 2089703d9d7SCatalin Marinas request_standard_resources(); 2099703d9d7SCatalin Marinas 2109703d9d7SCatalin Marinas unflatten_device_tree(); 2119703d9d7SCatalin Marinas 212e790f1deSWill Deacon psci_init(); 213e790f1deSWill Deacon 2144c7aa002SJavi Merino cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 2159703d9d7SCatalin Marinas #ifdef CONFIG_SMP 2169703d9d7SCatalin Marinas smp_init_cpus(); 2179703d9d7SCatalin Marinas #endif 2189703d9d7SCatalin Marinas 2199703d9d7SCatalin Marinas #ifdef CONFIG_VT 2209703d9d7SCatalin Marinas #if defined(CONFIG_VGA_CONSOLE) 2219703d9d7SCatalin Marinas conswitchp = &vga_con; 2229703d9d7SCatalin Marinas #elif defined(CONFIG_DUMMY_CONSOLE) 2239703d9d7SCatalin Marinas conswitchp = &dummy_con; 2249703d9d7SCatalin Marinas #endif 2259703d9d7SCatalin Marinas #endif 2269703d9d7SCatalin Marinas } 2279703d9d7SCatalin Marinas 228c560ecfeSCatalin Marinas static int __init arm64_device_init(void) 229de79a64dSCatalin Marinas { 230de79a64dSCatalin Marinas of_clk_init(NULL); 231c560ecfeSCatalin Marinas of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 232de79a64dSCatalin Marinas return 0; 233de79a64dSCatalin Marinas } 234c560ecfeSCatalin Marinas arch_initcall(arm64_device_init); 235de79a64dSCatalin Marinas 2369703d9d7SCatalin Marinas static DEFINE_PER_CPU(struct cpu, cpu_data); 2379703d9d7SCatalin Marinas 2389703d9d7SCatalin Marinas static int __init topology_init(void) 2399703d9d7SCatalin Marinas { 2409703d9d7SCatalin Marinas int i; 2419703d9d7SCatalin Marinas 2429703d9d7SCatalin Marinas for_each_possible_cpu(i) { 2439703d9d7SCatalin Marinas struct cpu *cpu = &per_cpu(cpu_data, i); 2449703d9d7SCatalin Marinas cpu->hotpluggable = 1; 2459703d9d7SCatalin Marinas register_cpu(cpu, i); 2469703d9d7SCatalin Marinas } 2479703d9d7SCatalin Marinas 2489703d9d7SCatalin Marinas return 0; 2499703d9d7SCatalin Marinas } 2509703d9d7SCatalin Marinas subsys_initcall(topology_init); 2519703d9d7SCatalin Marinas 2529703d9d7SCatalin Marinas static const char *hwcap_str[] = { 2539703d9d7SCatalin Marinas "fp", 2549703d9d7SCatalin Marinas "asimd", 2559703d9d7SCatalin Marinas NULL 2569703d9d7SCatalin Marinas }; 2579703d9d7SCatalin Marinas 2589703d9d7SCatalin Marinas static int c_show(struct seq_file *m, void *v) 2599703d9d7SCatalin Marinas { 2609703d9d7SCatalin Marinas int i; 2619703d9d7SCatalin Marinas 2629703d9d7SCatalin Marinas seq_printf(m, "Processor\t: %s rev %d (%s)\n", 2639703d9d7SCatalin Marinas cpu_name, read_cpuid_id() & 15, ELF_PLATFORM); 2649703d9d7SCatalin Marinas 2659703d9d7SCatalin Marinas for_each_online_cpu(i) { 2669703d9d7SCatalin Marinas /* 2679703d9d7SCatalin Marinas * glibc reads /proc/cpuinfo to determine the number of 2689703d9d7SCatalin Marinas * online processors, looking for lines beginning with 2699703d9d7SCatalin Marinas * "processor". Give glibc what it expects. 2709703d9d7SCatalin Marinas */ 2719703d9d7SCatalin Marinas #ifdef CONFIG_SMP 2729703d9d7SCatalin Marinas seq_printf(m, "processor\t: %d\n", i); 2739703d9d7SCatalin Marinas #endif 2749703d9d7SCatalin Marinas } 2759703d9d7SCatalin Marinas 2769703d9d7SCatalin Marinas /* dump out the processor features */ 2779703d9d7SCatalin Marinas seq_puts(m, "Features\t: "); 2789703d9d7SCatalin Marinas 2799703d9d7SCatalin Marinas for (i = 0; hwcap_str[i]; i++) 2809703d9d7SCatalin Marinas if (elf_hwcap & (1 << i)) 2819703d9d7SCatalin Marinas seq_printf(m, "%s ", hwcap_str[i]); 2829703d9d7SCatalin Marinas 2839703d9d7SCatalin Marinas seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24); 2849703d9d7SCatalin Marinas seq_printf(m, "CPU architecture: AArch64\n"); 2859703d9d7SCatalin Marinas seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15); 2869703d9d7SCatalin Marinas seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff); 2879703d9d7SCatalin Marinas seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15); 2889703d9d7SCatalin Marinas 2899703d9d7SCatalin Marinas seq_puts(m, "\n"); 2909703d9d7SCatalin Marinas 2919703d9d7SCatalin Marinas seq_printf(m, "Hardware\t: %s\n", machine_name); 2929703d9d7SCatalin Marinas 2939703d9d7SCatalin Marinas return 0; 2949703d9d7SCatalin Marinas } 2959703d9d7SCatalin Marinas 2969703d9d7SCatalin Marinas static void *c_start(struct seq_file *m, loff_t *pos) 2979703d9d7SCatalin Marinas { 2989703d9d7SCatalin Marinas return *pos < 1 ? (void *)1 : NULL; 2999703d9d7SCatalin Marinas } 3009703d9d7SCatalin Marinas 3019703d9d7SCatalin Marinas static void *c_next(struct seq_file *m, void *v, loff_t *pos) 3029703d9d7SCatalin Marinas { 3039703d9d7SCatalin Marinas ++*pos; 3049703d9d7SCatalin Marinas return NULL; 3059703d9d7SCatalin Marinas } 3069703d9d7SCatalin Marinas 3079703d9d7SCatalin Marinas static void c_stop(struct seq_file *m, void *v) 3089703d9d7SCatalin Marinas { 3099703d9d7SCatalin Marinas } 3109703d9d7SCatalin Marinas 3119703d9d7SCatalin Marinas const struct seq_operations cpuinfo_op = { 3129703d9d7SCatalin Marinas .start = c_start, 3139703d9d7SCatalin Marinas .next = c_next, 3149703d9d7SCatalin Marinas .stop = c_stop, 3159703d9d7SCatalin Marinas .show = c_show 3169703d9d7SCatalin Marinas }; 317