xref: /openbmc/linux/arch/arm64/kernel/setup.c (revision d5189cc5)
19703d9d7SCatalin Marinas /*
29703d9d7SCatalin Marinas  * Based on arch/arm/kernel/setup.c
39703d9d7SCatalin Marinas  *
49703d9d7SCatalin Marinas  * Copyright (C) 1995-2001 Russell King
59703d9d7SCatalin Marinas  * Copyright (C) 2012 ARM Ltd.
69703d9d7SCatalin Marinas  *
79703d9d7SCatalin Marinas  * This program is free software; you can redistribute it and/or modify
89703d9d7SCatalin Marinas  * it under the terms of the GNU General Public License version 2 as
99703d9d7SCatalin Marinas  * published by the Free Software Foundation.
109703d9d7SCatalin Marinas  *
119703d9d7SCatalin Marinas  * This program is distributed in the hope that it will be useful,
129703d9d7SCatalin Marinas  * but WITHOUT ANY WARRANTY; without even the implied warranty of
139703d9d7SCatalin Marinas  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
149703d9d7SCatalin Marinas  * GNU General Public License for more details.
159703d9d7SCatalin Marinas  *
169703d9d7SCatalin Marinas  * You should have received a copy of the GNU General Public License
179703d9d7SCatalin Marinas  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
189703d9d7SCatalin Marinas  */
199703d9d7SCatalin Marinas 
209703d9d7SCatalin Marinas #include <linux/export.h>
219703d9d7SCatalin Marinas #include <linux/kernel.h>
229703d9d7SCatalin Marinas #include <linux/stddef.h>
239703d9d7SCatalin Marinas #include <linux/ioport.h>
249703d9d7SCatalin Marinas #include <linux/delay.h>
259703d9d7SCatalin Marinas #include <linux/utsname.h>
269703d9d7SCatalin Marinas #include <linux/initrd.h>
279703d9d7SCatalin Marinas #include <linux/console.h>
289703d9d7SCatalin Marinas #include <linux/bootmem.h>
299703d9d7SCatalin Marinas #include <linux/seq_file.h>
309703d9d7SCatalin Marinas #include <linux/screen_info.h>
319703d9d7SCatalin Marinas #include <linux/init.h>
329703d9d7SCatalin Marinas #include <linux/kexec.h>
339703d9d7SCatalin Marinas #include <linux/crash_dump.h>
349703d9d7SCatalin Marinas #include <linux/root_dev.h>
35de79a64dSCatalin Marinas #include <linux/clk-provider.h>
369703d9d7SCatalin Marinas #include <linux/cpu.h>
379703d9d7SCatalin Marinas #include <linux/interrupt.h>
389703d9d7SCatalin Marinas #include <linux/smp.h>
399703d9d7SCatalin Marinas #include <linux/fs.h>
409703d9d7SCatalin Marinas #include <linux/proc_fs.h>
419703d9d7SCatalin Marinas #include <linux/memblock.h>
429703d9d7SCatalin Marinas #include <linux/of_fdt.h>
43d6bafb9bSCatalin Marinas #include <linux/of_platform.h>
449703d9d7SCatalin Marinas 
459703d9d7SCatalin Marinas #include <asm/cputype.h>
469703d9d7SCatalin Marinas #include <asm/elf.h>
479703d9d7SCatalin Marinas #include <asm/cputable.h>
489703d9d7SCatalin Marinas #include <asm/sections.h>
499703d9d7SCatalin Marinas #include <asm/setup.h>
504c7aa002SJavi Merino #include <asm/smp_plat.h>
519703d9d7SCatalin Marinas #include <asm/cacheflush.h>
529703d9d7SCatalin Marinas #include <asm/tlbflush.h>
539703d9d7SCatalin Marinas #include <asm/traps.h>
549703d9d7SCatalin Marinas #include <asm/memblock.h>
55e790f1deSWill Deacon #include <asm/psci.h>
569703d9d7SCatalin Marinas 
579703d9d7SCatalin Marinas unsigned int processor_id;
589703d9d7SCatalin Marinas EXPORT_SYMBOL(processor_id);
599703d9d7SCatalin Marinas 
6025804e6aSSteve Capper unsigned long elf_hwcap __read_mostly;
619703d9d7SCatalin Marinas EXPORT_SYMBOL_GPL(elf_hwcap);
629703d9d7SCatalin Marinas 
639703d9d7SCatalin Marinas static const char *cpu_name;
649703d9d7SCatalin Marinas static const char *machine_name;
659703d9d7SCatalin Marinas phys_addr_t __fdt_pointer __initdata;
669703d9d7SCatalin Marinas 
679703d9d7SCatalin Marinas /*
689703d9d7SCatalin Marinas  * Standard memory resources
699703d9d7SCatalin Marinas  */
709703d9d7SCatalin Marinas static struct resource mem_res[] = {
719703d9d7SCatalin Marinas 	{
729703d9d7SCatalin Marinas 		.name = "Kernel code",
739703d9d7SCatalin Marinas 		.start = 0,
749703d9d7SCatalin Marinas 		.end = 0,
759703d9d7SCatalin Marinas 		.flags = IORESOURCE_MEM
769703d9d7SCatalin Marinas 	},
779703d9d7SCatalin Marinas 	{
789703d9d7SCatalin Marinas 		.name = "Kernel data",
799703d9d7SCatalin Marinas 		.start = 0,
809703d9d7SCatalin Marinas 		.end = 0,
819703d9d7SCatalin Marinas 		.flags = IORESOURCE_MEM
829703d9d7SCatalin Marinas 	}
839703d9d7SCatalin Marinas };
849703d9d7SCatalin Marinas 
859703d9d7SCatalin Marinas #define kernel_code mem_res[0]
869703d9d7SCatalin Marinas #define kernel_data mem_res[1]
879703d9d7SCatalin Marinas 
889703d9d7SCatalin Marinas void __init early_print(const char *str, ...)
899703d9d7SCatalin Marinas {
909703d9d7SCatalin Marinas 	char buf[256];
919703d9d7SCatalin Marinas 	va_list ap;
929703d9d7SCatalin Marinas 
939703d9d7SCatalin Marinas 	va_start(ap, str);
949703d9d7SCatalin Marinas 	vsnprintf(buf, sizeof(buf), str, ap);
959703d9d7SCatalin Marinas 	va_end(ap);
969703d9d7SCatalin Marinas 
979703d9d7SCatalin Marinas 	printk("%s", buf);
989703d9d7SCatalin Marinas }
999703d9d7SCatalin Marinas 
1009703d9d7SCatalin Marinas static void __init setup_processor(void)
1019703d9d7SCatalin Marinas {
1029703d9d7SCatalin Marinas 	struct cpu_info *cpu_info;
1039703d9d7SCatalin Marinas 
1049703d9d7SCatalin Marinas 	/*
1059703d9d7SCatalin Marinas 	 * locate processor in the list of supported processor
1069703d9d7SCatalin Marinas 	 * types.  The linker builds this table for us from the
1079703d9d7SCatalin Marinas 	 * entries in arch/arm/mm/proc.S
1089703d9d7SCatalin Marinas 	 */
1099703d9d7SCatalin Marinas 	cpu_info = lookup_processor_type(read_cpuid_id());
1109703d9d7SCatalin Marinas 	if (!cpu_info) {
1119703d9d7SCatalin Marinas 		printk("CPU configuration botched (ID %08x), unable to continue.\n",
1129703d9d7SCatalin Marinas 		       read_cpuid_id());
1139703d9d7SCatalin Marinas 		while (1);
1149703d9d7SCatalin Marinas 	}
1159703d9d7SCatalin Marinas 
1169703d9d7SCatalin Marinas 	cpu_name = cpu_info->cpu_name;
1179703d9d7SCatalin Marinas 
1189703d9d7SCatalin Marinas 	printk("CPU: %s [%08x] revision %d\n",
1199703d9d7SCatalin Marinas 	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
1209703d9d7SCatalin Marinas 
1219703d9d7SCatalin Marinas 	sprintf(init_utsname()->machine, "aarch64");
1229703d9d7SCatalin Marinas 	elf_hwcap = 0;
1239703d9d7SCatalin Marinas }
1249703d9d7SCatalin Marinas 
1259703d9d7SCatalin Marinas static void __init setup_machine_fdt(phys_addr_t dt_phys)
1269703d9d7SCatalin Marinas {
1279703d9d7SCatalin Marinas 	unsigned long dt_root;
1289703d9d7SCatalin Marinas 
129d5189cc5SRob Herring 	if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
1309703d9d7SCatalin Marinas 		early_print("\n"
1319703d9d7SCatalin Marinas 			"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
132d5189cc5SRob Herring 			"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
1339703d9d7SCatalin Marinas 			"\nPlease check your bootloader.\n",
134d5189cc5SRob Herring 			dt_phys, phys_to_virt(dt_phys));
1359703d9d7SCatalin Marinas 
1369703d9d7SCatalin Marinas 		while (true)
1379703d9d7SCatalin Marinas 			cpu_relax();
1389703d9d7SCatalin Marinas 	}
1399703d9d7SCatalin Marinas 
1409703d9d7SCatalin Marinas 	dt_root = of_get_flat_dt_root();
1419703d9d7SCatalin Marinas 
1429703d9d7SCatalin Marinas 	machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
1439703d9d7SCatalin Marinas 	if (!machine_name)
1449703d9d7SCatalin Marinas 		machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
1459703d9d7SCatalin Marinas 	if (!machine_name)
1469703d9d7SCatalin Marinas 		machine_name = "<unknown>";
1479703d9d7SCatalin Marinas 	pr_info("Machine: %s\n", machine_name);
1489703d9d7SCatalin Marinas }
1499703d9d7SCatalin Marinas 
1509703d9d7SCatalin Marinas void __init early_init_dt_add_memory_arch(u64 base, u64 size)
1519703d9d7SCatalin Marinas {
152f71a1a42SCatalin Marinas 	base &= PAGE_MASK;
1539703d9d7SCatalin Marinas 	size &= PAGE_MASK;
154f71a1a42SCatalin Marinas 	if (base + size < PHYS_OFFSET) {
155f71a1a42SCatalin Marinas 		pr_warning("Ignoring memory block 0x%llx - 0x%llx\n",
156f71a1a42SCatalin Marinas 			   base, base + size);
157f71a1a42SCatalin Marinas 		return;
158f71a1a42SCatalin Marinas 	}
159f71a1a42SCatalin Marinas 	if (base < PHYS_OFFSET) {
160f71a1a42SCatalin Marinas 		pr_warning("Ignoring memory range 0x%llx - 0x%llx\n",
161f71a1a42SCatalin Marinas 			   base, PHYS_OFFSET);
162f71a1a42SCatalin Marinas 		size -= PHYS_OFFSET - base;
163f71a1a42SCatalin Marinas 		base = PHYS_OFFSET;
164f71a1a42SCatalin Marinas 	}
1659703d9d7SCatalin Marinas 	memblock_add(base, size);
1669703d9d7SCatalin Marinas }
1679703d9d7SCatalin Marinas 
1689703d9d7SCatalin Marinas /*
1699703d9d7SCatalin Marinas  * Limit the memory size that was specified via FDT.
1709703d9d7SCatalin Marinas  */
1719703d9d7SCatalin Marinas static int __init early_mem(char *p)
1729703d9d7SCatalin Marinas {
1739703d9d7SCatalin Marinas 	phys_addr_t limit;
1749703d9d7SCatalin Marinas 
1759703d9d7SCatalin Marinas 	if (!p)
1769703d9d7SCatalin Marinas 		return 1;
1779703d9d7SCatalin Marinas 
1789703d9d7SCatalin Marinas 	limit = memparse(p, &p) & PAGE_MASK;
1799703d9d7SCatalin Marinas 	pr_notice("Memory limited to %lldMB\n", limit >> 20);
1809703d9d7SCatalin Marinas 
1819703d9d7SCatalin Marinas 	memblock_enforce_memory_limit(limit);
1829703d9d7SCatalin Marinas 
1839703d9d7SCatalin Marinas 	return 0;
1849703d9d7SCatalin Marinas }
1859703d9d7SCatalin Marinas early_param("mem", early_mem);
1869703d9d7SCatalin Marinas 
1879703d9d7SCatalin Marinas static void __init request_standard_resources(void)
1889703d9d7SCatalin Marinas {
1899703d9d7SCatalin Marinas 	struct memblock_region *region;
1909703d9d7SCatalin Marinas 	struct resource *res;
1919703d9d7SCatalin Marinas 
1929703d9d7SCatalin Marinas 	kernel_code.start   = virt_to_phys(_text);
1939703d9d7SCatalin Marinas 	kernel_code.end     = virt_to_phys(_etext - 1);
1949703d9d7SCatalin Marinas 	kernel_data.start   = virt_to_phys(_sdata);
1959703d9d7SCatalin Marinas 	kernel_data.end     = virt_to_phys(_end - 1);
1969703d9d7SCatalin Marinas 
1979703d9d7SCatalin Marinas 	for_each_memblock(memory, region) {
1989703d9d7SCatalin Marinas 		res = alloc_bootmem_low(sizeof(*res));
1999703d9d7SCatalin Marinas 		res->name  = "System RAM";
2009703d9d7SCatalin Marinas 		res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
2019703d9d7SCatalin Marinas 		res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
2029703d9d7SCatalin Marinas 		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2039703d9d7SCatalin Marinas 
2049703d9d7SCatalin Marinas 		request_resource(&iomem_resource, res);
2059703d9d7SCatalin Marinas 
2069703d9d7SCatalin Marinas 		if (kernel_code.start >= res->start &&
2079703d9d7SCatalin Marinas 		    kernel_code.end <= res->end)
2089703d9d7SCatalin Marinas 			request_resource(res, &kernel_code);
2099703d9d7SCatalin Marinas 		if (kernel_data.start >= res->start &&
2109703d9d7SCatalin Marinas 		    kernel_data.end <= res->end)
2119703d9d7SCatalin Marinas 			request_resource(res, &kernel_data);
2129703d9d7SCatalin Marinas 	}
2139703d9d7SCatalin Marinas }
2149703d9d7SCatalin Marinas 
2154c7aa002SJavi Merino u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
2164c7aa002SJavi Merino 
2179703d9d7SCatalin Marinas void __init setup_arch(char **cmdline_p)
2189703d9d7SCatalin Marinas {
2199703d9d7SCatalin Marinas 	setup_processor();
2209703d9d7SCatalin Marinas 
2219703d9d7SCatalin Marinas 	setup_machine_fdt(__fdt_pointer);
2229703d9d7SCatalin Marinas 
2239703d9d7SCatalin Marinas 	init_mm.start_code = (unsigned long) _text;
2249703d9d7SCatalin Marinas 	init_mm.end_code   = (unsigned long) _etext;
2259703d9d7SCatalin Marinas 	init_mm.end_data   = (unsigned long) _edata;
2269703d9d7SCatalin Marinas 	init_mm.brk	   = (unsigned long) _end;
2279703d9d7SCatalin Marinas 
2289703d9d7SCatalin Marinas 	*cmdline_p = boot_command_line;
2299703d9d7SCatalin Marinas 
2309703d9d7SCatalin Marinas 	parse_early_param();
2319703d9d7SCatalin Marinas 
2329703d9d7SCatalin Marinas 	arm64_memblock_init();
2339703d9d7SCatalin Marinas 
2349703d9d7SCatalin Marinas 	paging_init();
2359703d9d7SCatalin Marinas 	request_standard_resources();
2369703d9d7SCatalin Marinas 
2379703d9d7SCatalin Marinas 	unflatten_device_tree();
2389703d9d7SCatalin Marinas 
239e790f1deSWill Deacon 	psci_init();
240e790f1deSWill Deacon 
2414c7aa002SJavi Merino 	cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
2429703d9d7SCatalin Marinas #ifdef CONFIG_SMP
2439703d9d7SCatalin Marinas 	smp_init_cpus();
2449703d9d7SCatalin Marinas #endif
2459703d9d7SCatalin Marinas 
2469703d9d7SCatalin Marinas #ifdef CONFIG_VT
2479703d9d7SCatalin Marinas #if defined(CONFIG_VGA_CONSOLE)
2489703d9d7SCatalin Marinas 	conswitchp = &vga_con;
2499703d9d7SCatalin Marinas #elif defined(CONFIG_DUMMY_CONSOLE)
2509703d9d7SCatalin Marinas 	conswitchp = &dummy_con;
2519703d9d7SCatalin Marinas #endif
2529703d9d7SCatalin Marinas #endif
2539703d9d7SCatalin Marinas }
2549703d9d7SCatalin Marinas 
255c560ecfeSCatalin Marinas static int __init arm64_device_init(void)
256de79a64dSCatalin Marinas {
257de79a64dSCatalin Marinas 	of_clk_init(NULL);
258c560ecfeSCatalin Marinas 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
259de79a64dSCatalin Marinas 	return 0;
260de79a64dSCatalin Marinas }
261c560ecfeSCatalin Marinas arch_initcall(arm64_device_init);
262de79a64dSCatalin Marinas 
2639703d9d7SCatalin Marinas static DEFINE_PER_CPU(struct cpu, cpu_data);
2649703d9d7SCatalin Marinas 
2659703d9d7SCatalin Marinas static int __init topology_init(void)
2669703d9d7SCatalin Marinas {
2679703d9d7SCatalin Marinas 	int i;
2689703d9d7SCatalin Marinas 
2699703d9d7SCatalin Marinas 	for_each_possible_cpu(i) {
2709703d9d7SCatalin Marinas 		struct cpu *cpu = &per_cpu(cpu_data, i);
2719703d9d7SCatalin Marinas 		cpu->hotpluggable = 1;
2729703d9d7SCatalin Marinas 		register_cpu(cpu, i);
2739703d9d7SCatalin Marinas 	}
2749703d9d7SCatalin Marinas 
2759703d9d7SCatalin Marinas 	return 0;
2769703d9d7SCatalin Marinas }
2779703d9d7SCatalin Marinas subsys_initcall(topology_init);
2789703d9d7SCatalin Marinas 
2799703d9d7SCatalin Marinas static const char *hwcap_str[] = {
2809703d9d7SCatalin Marinas 	"fp",
2819703d9d7SCatalin Marinas 	"asimd",
2829703d9d7SCatalin Marinas 	NULL
2839703d9d7SCatalin Marinas };
2849703d9d7SCatalin Marinas 
2859703d9d7SCatalin Marinas static int c_show(struct seq_file *m, void *v)
2869703d9d7SCatalin Marinas {
2879703d9d7SCatalin Marinas 	int i;
2889703d9d7SCatalin Marinas 
2899703d9d7SCatalin Marinas 	seq_printf(m, "Processor\t: %s rev %d (%s)\n",
2909703d9d7SCatalin Marinas 		   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
2919703d9d7SCatalin Marinas 
2929703d9d7SCatalin Marinas 	for_each_online_cpu(i) {
2939703d9d7SCatalin Marinas 		/*
2949703d9d7SCatalin Marinas 		 * glibc reads /proc/cpuinfo to determine the number of
2959703d9d7SCatalin Marinas 		 * online processors, looking for lines beginning with
2969703d9d7SCatalin Marinas 		 * "processor".  Give glibc what it expects.
2979703d9d7SCatalin Marinas 		 */
2989703d9d7SCatalin Marinas #ifdef CONFIG_SMP
2999703d9d7SCatalin Marinas 		seq_printf(m, "processor\t: %d\n", i);
3009703d9d7SCatalin Marinas #endif
3019703d9d7SCatalin Marinas 	}
3029703d9d7SCatalin Marinas 
3039703d9d7SCatalin Marinas 	/* dump out the processor features */
3049703d9d7SCatalin Marinas 	seq_puts(m, "Features\t: ");
3059703d9d7SCatalin Marinas 
3069703d9d7SCatalin Marinas 	for (i = 0; hwcap_str[i]; i++)
3079703d9d7SCatalin Marinas 		if (elf_hwcap & (1 << i))
3089703d9d7SCatalin Marinas 			seq_printf(m, "%s ", hwcap_str[i]);
3099703d9d7SCatalin Marinas 
3109703d9d7SCatalin Marinas 	seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
3119703d9d7SCatalin Marinas 	seq_printf(m, "CPU architecture: AArch64\n");
3129703d9d7SCatalin Marinas 	seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
3139703d9d7SCatalin Marinas 	seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
3149703d9d7SCatalin Marinas 	seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
3159703d9d7SCatalin Marinas 
3169703d9d7SCatalin Marinas 	seq_puts(m, "\n");
3179703d9d7SCatalin Marinas 
3189703d9d7SCatalin Marinas 	seq_printf(m, "Hardware\t: %s\n", machine_name);
3199703d9d7SCatalin Marinas 
3209703d9d7SCatalin Marinas 	return 0;
3219703d9d7SCatalin Marinas }
3229703d9d7SCatalin Marinas 
3239703d9d7SCatalin Marinas static void *c_start(struct seq_file *m, loff_t *pos)
3249703d9d7SCatalin Marinas {
3259703d9d7SCatalin Marinas 	return *pos < 1 ? (void *)1 : NULL;
3269703d9d7SCatalin Marinas }
3279703d9d7SCatalin Marinas 
3289703d9d7SCatalin Marinas static void *c_next(struct seq_file *m, void *v, loff_t *pos)
3299703d9d7SCatalin Marinas {
3309703d9d7SCatalin Marinas 	++*pos;
3319703d9d7SCatalin Marinas 	return NULL;
3329703d9d7SCatalin Marinas }
3339703d9d7SCatalin Marinas 
3349703d9d7SCatalin Marinas static void c_stop(struct seq_file *m, void *v)
3359703d9d7SCatalin Marinas {
3369703d9d7SCatalin Marinas }
3379703d9d7SCatalin Marinas 
3389703d9d7SCatalin Marinas const struct seq_operations cpuinfo_op = {
3399703d9d7SCatalin Marinas 	.start	= c_start,
3409703d9d7SCatalin Marinas 	.next	= c_next,
3419703d9d7SCatalin Marinas 	.stop	= c_stop,
3429703d9d7SCatalin Marinas 	.show	= c_show
3439703d9d7SCatalin Marinas };
344