19703d9d7SCatalin Marinas /* 29703d9d7SCatalin Marinas * Based on arch/arm/kernel/setup.c 39703d9d7SCatalin Marinas * 49703d9d7SCatalin Marinas * Copyright (C) 1995-2001 Russell King 59703d9d7SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 69703d9d7SCatalin Marinas * 79703d9d7SCatalin Marinas * This program is free software; you can redistribute it and/or modify 89703d9d7SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 99703d9d7SCatalin Marinas * published by the Free Software Foundation. 109703d9d7SCatalin Marinas * 119703d9d7SCatalin Marinas * This program is distributed in the hope that it will be useful, 129703d9d7SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 139703d9d7SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 149703d9d7SCatalin Marinas * GNU General Public License for more details. 159703d9d7SCatalin Marinas * 169703d9d7SCatalin Marinas * You should have received a copy of the GNU General Public License 179703d9d7SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 189703d9d7SCatalin Marinas */ 199703d9d7SCatalin Marinas 209703d9d7SCatalin Marinas #include <linux/export.h> 219703d9d7SCatalin Marinas #include <linux/kernel.h> 229703d9d7SCatalin Marinas #include <linux/stddef.h> 239703d9d7SCatalin Marinas #include <linux/ioport.h> 249703d9d7SCatalin Marinas #include <linux/delay.h> 259703d9d7SCatalin Marinas #include <linux/utsname.h> 269703d9d7SCatalin Marinas #include <linux/initrd.h> 279703d9d7SCatalin Marinas #include <linux/console.h> 28a41dc0e8SCatalin Marinas #include <linux/cache.h> 299703d9d7SCatalin Marinas #include <linux/bootmem.h> 309703d9d7SCatalin Marinas #include <linux/seq_file.h> 319703d9d7SCatalin Marinas #include <linux/screen_info.h> 329703d9d7SCatalin Marinas #include <linux/init.h> 339703d9d7SCatalin Marinas #include <linux/kexec.h> 349703d9d7SCatalin Marinas #include <linux/crash_dump.h> 359703d9d7SCatalin Marinas #include <linux/root_dev.h> 36de79a64dSCatalin Marinas #include <linux/clk-provider.h> 379703d9d7SCatalin Marinas #include <linux/cpu.h> 389703d9d7SCatalin Marinas #include <linux/interrupt.h> 399703d9d7SCatalin Marinas #include <linux/smp.h> 409703d9d7SCatalin Marinas #include <linux/fs.h> 419703d9d7SCatalin Marinas #include <linux/proc_fs.h> 429703d9d7SCatalin Marinas #include <linux/memblock.h> 4378d51e0bSRobin Murphy #include <linux/of_iommu.h> 449703d9d7SCatalin Marinas #include <linux/of_fdt.h> 45d6bafb9bSCatalin Marinas #include <linux/of_platform.h> 46f84d0275SMark Salter #include <linux/efi.h> 4744b82b77SMark Rutland #include <linux/personality.h> 489703d9d7SCatalin Marinas 49bf4b558eSMark Salter #include <asm/fixmap.h> 50df857416SMark Rutland #include <asm/cpu.h> 519703d9d7SCatalin Marinas #include <asm/cputype.h> 529703d9d7SCatalin Marinas #include <asm/elf.h> 53930da09fSAndre Przywara #include <asm/cpufeature.h> 54e8765b26SMark Rutland #include <asm/cpu_ops.h> 559703d9d7SCatalin Marinas #include <asm/sections.h> 569703d9d7SCatalin Marinas #include <asm/setup.h> 574c7aa002SJavi Merino #include <asm/smp_plat.h> 589703d9d7SCatalin Marinas #include <asm/cacheflush.h> 599703d9d7SCatalin Marinas #include <asm/tlbflush.h> 609703d9d7SCatalin Marinas #include <asm/traps.h> 619703d9d7SCatalin Marinas #include <asm/memblock.h> 62e790f1deSWill Deacon #include <asm/psci.h> 63f84d0275SMark Salter #include <asm/efi.h> 64667f3fd3SMark Rutland #include <asm/virt.h> 659703d9d7SCatalin Marinas 669703d9d7SCatalin Marinas unsigned int processor_id; 679703d9d7SCatalin Marinas EXPORT_SYMBOL(processor_id); 689703d9d7SCatalin Marinas 6925804e6aSSteve Capper unsigned long elf_hwcap __read_mostly; 709703d9d7SCatalin Marinas EXPORT_SYMBOL_GPL(elf_hwcap); 719703d9d7SCatalin Marinas 7246efe547SSudeep KarkadaNagesha #ifdef CONFIG_COMPAT 7346efe547SSudeep KarkadaNagesha #define COMPAT_ELF_HWCAP_DEFAULT \ 7446efe547SSudeep KarkadaNagesha (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 7546efe547SSudeep KarkadaNagesha COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 7646efe547SSudeep KarkadaNagesha COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 7746efe547SSudeep KarkadaNagesha COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 787d57511dSCatalin Marinas COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 797d57511dSCatalin Marinas COMPAT_HWCAP_LPAE) 8046efe547SSudeep KarkadaNagesha unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 8128964d32SArd Biesheuvel unsigned int compat_elf_hwcap2 __read_mostly; 8246efe547SSudeep KarkadaNagesha #endif 8346efe547SSudeep KarkadaNagesha 8406f9eb88SFabio Estevam DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 85930da09fSAndre Przywara 869703d9d7SCatalin Marinas phys_addr_t __fdt_pointer __initdata; 879703d9d7SCatalin Marinas 889703d9d7SCatalin Marinas /* 899703d9d7SCatalin Marinas * Standard memory resources 909703d9d7SCatalin Marinas */ 919703d9d7SCatalin Marinas static struct resource mem_res[] = { 929703d9d7SCatalin Marinas { 939703d9d7SCatalin Marinas .name = "Kernel code", 949703d9d7SCatalin Marinas .start = 0, 959703d9d7SCatalin Marinas .end = 0, 969703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 979703d9d7SCatalin Marinas }, 989703d9d7SCatalin Marinas { 999703d9d7SCatalin Marinas .name = "Kernel data", 1009703d9d7SCatalin Marinas .start = 0, 1019703d9d7SCatalin Marinas .end = 0, 1029703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 1039703d9d7SCatalin Marinas } 1049703d9d7SCatalin Marinas }; 1059703d9d7SCatalin Marinas 1069703d9d7SCatalin Marinas #define kernel_code mem_res[0] 1079703d9d7SCatalin Marinas #define kernel_data mem_res[1] 1089703d9d7SCatalin Marinas 1099703d9d7SCatalin Marinas void __init early_print(const char *str, ...) 1109703d9d7SCatalin Marinas { 1119703d9d7SCatalin Marinas char buf[256]; 1129703d9d7SCatalin Marinas va_list ap; 1139703d9d7SCatalin Marinas 1149703d9d7SCatalin Marinas va_start(ap, str); 1159703d9d7SCatalin Marinas vsnprintf(buf, sizeof(buf), str, ap); 1169703d9d7SCatalin Marinas va_end(ap); 1179703d9d7SCatalin Marinas 1189703d9d7SCatalin Marinas printk("%s", buf); 1199703d9d7SCatalin Marinas } 1209703d9d7SCatalin Marinas 12171586276SWill Deacon void __init smp_setup_processor_id(void) 12271586276SWill Deacon { 12380708677SMark Rutland u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 12480708677SMark Rutland cpu_logical_map(0) = mpidr; 12580708677SMark Rutland 12671586276SWill Deacon /* 12771586276SWill Deacon * clear __my_cpu_offset on boot CPU to avoid hang caused by 12871586276SWill Deacon * using percpu variable early, for example, lockdep will 12971586276SWill Deacon * access percpu variable inside lock_release 13071586276SWill Deacon */ 13171586276SWill Deacon set_my_cpu_offset(0); 13280708677SMark Rutland pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr); 13371586276SWill Deacon } 13471586276SWill Deacon 1356e15d0e0SSudeep KarkadaNagesha bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 1366e15d0e0SSudeep KarkadaNagesha { 1376e15d0e0SSudeep KarkadaNagesha return phys_id == cpu_logical_map(cpu); 1386e15d0e0SSudeep KarkadaNagesha } 1396e15d0e0SSudeep KarkadaNagesha 140976d7d3fSLorenzo Pieralisi struct mpidr_hash mpidr_hash; 141976d7d3fSLorenzo Pieralisi #ifdef CONFIG_SMP 142976d7d3fSLorenzo Pieralisi /** 143976d7d3fSLorenzo Pieralisi * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 144976d7d3fSLorenzo Pieralisi * level in order to build a linear index from an 145976d7d3fSLorenzo Pieralisi * MPIDR value. Resulting algorithm is a collision 146976d7d3fSLorenzo Pieralisi * free hash carried out through shifting and ORing 147976d7d3fSLorenzo Pieralisi */ 148976d7d3fSLorenzo Pieralisi static void __init smp_build_mpidr_hash(void) 149976d7d3fSLorenzo Pieralisi { 150976d7d3fSLorenzo Pieralisi u32 i, affinity, fs[4], bits[4], ls; 151976d7d3fSLorenzo Pieralisi u64 mask = 0; 152976d7d3fSLorenzo Pieralisi /* 153976d7d3fSLorenzo Pieralisi * Pre-scan the list of MPIDRS and filter out bits that do 154976d7d3fSLorenzo Pieralisi * not contribute to affinity levels, ie they never toggle. 155976d7d3fSLorenzo Pieralisi */ 156976d7d3fSLorenzo Pieralisi for_each_possible_cpu(i) 157976d7d3fSLorenzo Pieralisi mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 158976d7d3fSLorenzo Pieralisi pr_debug("mask of set bits %#llx\n", mask); 159976d7d3fSLorenzo Pieralisi /* 160976d7d3fSLorenzo Pieralisi * Find and stash the last and first bit set at all affinity levels to 161976d7d3fSLorenzo Pieralisi * check how many bits are required to represent them. 162976d7d3fSLorenzo Pieralisi */ 163976d7d3fSLorenzo Pieralisi for (i = 0; i < 4; i++) { 164976d7d3fSLorenzo Pieralisi affinity = MPIDR_AFFINITY_LEVEL(mask, i); 165976d7d3fSLorenzo Pieralisi /* 166976d7d3fSLorenzo Pieralisi * Find the MSB bit and LSB bits position 167976d7d3fSLorenzo Pieralisi * to determine how many bits are required 168976d7d3fSLorenzo Pieralisi * to express the affinity level. 169976d7d3fSLorenzo Pieralisi */ 170976d7d3fSLorenzo Pieralisi ls = fls(affinity); 171976d7d3fSLorenzo Pieralisi fs[i] = affinity ? ffs(affinity) - 1 : 0; 172976d7d3fSLorenzo Pieralisi bits[i] = ls - fs[i]; 173976d7d3fSLorenzo Pieralisi } 174976d7d3fSLorenzo Pieralisi /* 175976d7d3fSLorenzo Pieralisi * An index can be created from the MPIDR_EL1 by isolating the 176976d7d3fSLorenzo Pieralisi * significant bits at each affinity level and by shifting 177976d7d3fSLorenzo Pieralisi * them in order to compress the 32 bits values space to a 178976d7d3fSLorenzo Pieralisi * compressed set of values. This is equivalent to hashing 179976d7d3fSLorenzo Pieralisi * the MPIDR_EL1 through shifting and ORing. It is a collision free 180976d7d3fSLorenzo Pieralisi * hash though not minimal since some levels might contain a number 181976d7d3fSLorenzo Pieralisi * of CPUs that is not an exact power of 2 and their bit 182976d7d3fSLorenzo Pieralisi * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. 183976d7d3fSLorenzo Pieralisi */ 184976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; 185976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; 186976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - 187976d7d3fSLorenzo Pieralisi (bits[1] + bits[0]); 188976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + 189976d7d3fSLorenzo Pieralisi fs[3] - (bits[2] + bits[1] + bits[0]); 190976d7d3fSLorenzo Pieralisi mpidr_hash.mask = mask; 191976d7d3fSLorenzo Pieralisi mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; 192976d7d3fSLorenzo Pieralisi pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", 193976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[0], 194976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[1], 195976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[2], 196976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[3], 197976d7d3fSLorenzo Pieralisi mpidr_hash.mask, 198976d7d3fSLorenzo Pieralisi mpidr_hash.bits); 199976d7d3fSLorenzo Pieralisi /* 200976d7d3fSLorenzo Pieralisi * 4x is an arbitrary value used to warn on a hash table much bigger 201976d7d3fSLorenzo Pieralisi * than expected on most systems. 202976d7d3fSLorenzo Pieralisi */ 203976d7d3fSLorenzo Pieralisi if (mpidr_hash_size() > 4 * num_possible_cpus()) 204976d7d3fSLorenzo Pieralisi pr_warn("Large number of MPIDR hash buckets detected\n"); 205976d7d3fSLorenzo Pieralisi __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash)); 206976d7d3fSLorenzo Pieralisi } 207976d7d3fSLorenzo Pieralisi #endif 208976d7d3fSLorenzo Pieralisi 209667f3fd3SMark Rutland static void __init hyp_mode_check(void) 210667f3fd3SMark Rutland { 211667f3fd3SMark Rutland if (is_hyp_mode_available()) 212667f3fd3SMark Rutland pr_info("CPU: All CPU(s) started at EL2\n"); 213667f3fd3SMark Rutland else if (is_hyp_mode_mismatched()) 214667f3fd3SMark Rutland WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, 215667f3fd3SMark Rutland "CPU: CPUs started in inconsistent modes"); 216667f3fd3SMark Rutland else 217667f3fd3SMark Rutland pr_info("CPU: All CPU(s) started at EL1\n"); 218667f3fd3SMark Rutland } 219667f3fd3SMark Rutland 220137650aaSMark Rutland void __init do_post_cpus_up_work(void) 221137650aaSMark Rutland { 222667f3fd3SMark Rutland hyp_mode_check(); 223137650aaSMark Rutland apply_alternatives_all(); 224137650aaSMark Rutland } 225137650aaSMark Rutland 226137650aaSMark Rutland #ifdef CONFIG_UP_LATE_INIT 227137650aaSMark Rutland void __init up_late_init(void) 228137650aaSMark Rutland { 229137650aaSMark Rutland do_post_cpus_up_work(); 230137650aaSMark Rutland } 231137650aaSMark Rutland #endif /* CONFIG_UP_LATE_INIT */ 232137650aaSMark Rutland 2339703d9d7SCatalin Marinas static void __init setup_processor(void) 2349703d9d7SCatalin Marinas { 2354bff28ccSSteve Capper u64 features, block; 236a41dc0e8SCatalin Marinas u32 cwg; 237a41dc0e8SCatalin Marinas int cls; 2389703d9d7SCatalin Marinas 239a591ede4SMarc Zyngier printk("CPU: AArch64 Processor [%08x] revision %d\n", 240a591ede4SMarc Zyngier read_cpuid_id(), read_cpuid_id() & 15); 2419703d9d7SCatalin Marinas 24294ed1f2cSWill Deacon sprintf(init_utsname()->machine, ELF_PLATFORM); 2439703d9d7SCatalin Marinas elf_hwcap = 0; 2444bff28ccSSteve Capper 245df857416SMark Rutland cpuinfo_store_boot_cpu(); 246df857416SMark Rutland 2474bff28ccSSteve Capper /* 248a41dc0e8SCatalin Marinas * Check for sane CTR_EL0.CWG value. 249a41dc0e8SCatalin Marinas */ 250a41dc0e8SCatalin Marinas cwg = cache_type_cwg(); 251a41dc0e8SCatalin Marinas cls = cache_line_size(); 252a41dc0e8SCatalin Marinas if (!cwg) 253a41dc0e8SCatalin Marinas pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", 254a41dc0e8SCatalin Marinas cls); 255a41dc0e8SCatalin Marinas if (L1_CACHE_BYTES < cls) 256a41dc0e8SCatalin Marinas pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", 257a41dc0e8SCatalin Marinas L1_CACHE_BYTES, cls); 258a41dc0e8SCatalin Marinas 259a41dc0e8SCatalin Marinas /* 2604bff28ccSSteve Capper * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. 2614bff28ccSSteve Capper * The blocks we test below represent incremental functionality 2624bff28ccSSteve Capper * for non-negative values. Negative values are reserved. 2634bff28ccSSteve Capper */ 2644bff28ccSSteve Capper features = read_cpuid(ID_AA64ISAR0_EL1); 2654bff28ccSSteve Capper block = (features >> 4) & 0xf; 2664bff28ccSSteve Capper if (!(block & 0x8)) { 2674bff28ccSSteve Capper switch (block) { 2684bff28ccSSteve Capper default: 2694bff28ccSSteve Capper case 2: 2704bff28ccSSteve Capper elf_hwcap |= HWCAP_PMULL; 2714bff28ccSSteve Capper case 1: 2724bff28ccSSteve Capper elf_hwcap |= HWCAP_AES; 2734bff28ccSSteve Capper case 0: 2744bff28ccSSteve Capper break; 2754bff28ccSSteve Capper } 2764bff28ccSSteve Capper } 2774bff28ccSSteve Capper 2784bff28ccSSteve Capper block = (features >> 8) & 0xf; 2794bff28ccSSteve Capper if (block && !(block & 0x8)) 2804bff28ccSSteve Capper elf_hwcap |= HWCAP_SHA1; 2814bff28ccSSteve Capper 2824bff28ccSSteve Capper block = (features >> 12) & 0xf; 2834bff28ccSSteve Capper if (block && !(block & 0x8)) 2844bff28ccSSteve Capper elf_hwcap |= HWCAP_SHA2; 2854bff28ccSSteve Capper 2864bff28ccSSteve Capper block = (features >> 16) & 0xf; 2874bff28ccSSteve Capper if (block && !(block & 0x8)) 2884bff28ccSSteve Capper elf_hwcap |= HWCAP_CRC32; 2894cf761cdSArd Biesheuvel 2904cf761cdSArd Biesheuvel #ifdef CONFIG_COMPAT 2914cf761cdSArd Biesheuvel /* 2924cf761cdSArd Biesheuvel * ID_ISAR5_EL1 carries similar information as above, but pertaining to 2934cf761cdSArd Biesheuvel * the Aarch32 32-bit execution state. 2944cf761cdSArd Biesheuvel */ 2954cf761cdSArd Biesheuvel features = read_cpuid(ID_ISAR5_EL1); 2964cf761cdSArd Biesheuvel block = (features >> 4) & 0xf; 2974cf761cdSArd Biesheuvel if (!(block & 0x8)) { 2984cf761cdSArd Biesheuvel switch (block) { 2994cf761cdSArd Biesheuvel default: 3004cf761cdSArd Biesheuvel case 2: 3014cf761cdSArd Biesheuvel compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL; 3024cf761cdSArd Biesheuvel case 1: 3034cf761cdSArd Biesheuvel compat_elf_hwcap2 |= COMPAT_HWCAP2_AES; 3044cf761cdSArd Biesheuvel case 0: 3054cf761cdSArd Biesheuvel break; 3064cf761cdSArd Biesheuvel } 3074cf761cdSArd Biesheuvel } 3084cf761cdSArd Biesheuvel 3094cf761cdSArd Biesheuvel block = (features >> 8) & 0xf; 3104cf761cdSArd Biesheuvel if (block && !(block & 0x8)) 3114cf761cdSArd Biesheuvel compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1; 3124cf761cdSArd Biesheuvel 3134cf761cdSArd Biesheuvel block = (features >> 12) & 0xf; 3144cf761cdSArd Biesheuvel if (block && !(block & 0x8)) 3154cf761cdSArd Biesheuvel compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2; 3164cf761cdSArd Biesheuvel 3174cf761cdSArd Biesheuvel block = (features >> 16) & 0xf; 3184cf761cdSArd Biesheuvel if (block && !(block & 0x8)) 3194cf761cdSArd Biesheuvel compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32; 3204cf761cdSArd Biesheuvel #endif 3219703d9d7SCatalin Marinas } 3229703d9d7SCatalin Marinas 3239703d9d7SCatalin Marinas static void __init setup_machine_fdt(phys_addr_t dt_phys) 3249703d9d7SCatalin Marinas { 325d5189cc5SRob Herring if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { 3269703d9d7SCatalin Marinas early_print("\n" 3279703d9d7SCatalin Marinas "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" 328d5189cc5SRob Herring "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" 3299703d9d7SCatalin Marinas "\nPlease check your bootloader.\n", 330d5189cc5SRob Herring dt_phys, phys_to_virt(dt_phys)); 3319703d9d7SCatalin Marinas 3329703d9d7SCatalin Marinas while (true) 3339703d9d7SCatalin Marinas cpu_relax(); 3349703d9d7SCatalin Marinas } 3355e39977eSWill Deacon 33644b82b77SMark Rutland dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name()); 3379703d9d7SCatalin Marinas } 3389703d9d7SCatalin Marinas 3399703d9d7SCatalin Marinas static void __init request_standard_resources(void) 3409703d9d7SCatalin Marinas { 3419703d9d7SCatalin Marinas struct memblock_region *region; 3429703d9d7SCatalin Marinas struct resource *res; 3439703d9d7SCatalin Marinas 3449703d9d7SCatalin Marinas kernel_code.start = virt_to_phys(_text); 3459703d9d7SCatalin Marinas kernel_code.end = virt_to_phys(_etext - 1); 3469703d9d7SCatalin Marinas kernel_data.start = virt_to_phys(_sdata); 3479703d9d7SCatalin Marinas kernel_data.end = virt_to_phys(_end - 1); 3489703d9d7SCatalin Marinas 3499703d9d7SCatalin Marinas for_each_memblock(memory, region) { 3509703d9d7SCatalin Marinas res = alloc_bootmem_low(sizeof(*res)); 3519703d9d7SCatalin Marinas res->name = "System RAM"; 3529703d9d7SCatalin Marinas res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 3539703d9d7SCatalin Marinas res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 3549703d9d7SCatalin Marinas res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 3559703d9d7SCatalin Marinas 3569703d9d7SCatalin Marinas request_resource(&iomem_resource, res); 3579703d9d7SCatalin Marinas 3589703d9d7SCatalin Marinas if (kernel_code.start >= res->start && 3599703d9d7SCatalin Marinas kernel_code.end <= res->end) 3609703d9d7SCatalin Marinas request_resource(res, &kernel_code); 3619703d9d7SCatalin Marinas if (kernel_data.start >= res->start && 3629703d9d7SCatalin Marinas kernel_data.end <= res->end) 3639703d9d7SCatalin Marinas request_resource(res, &kernel_data); 3649703d9d7SCatalin Marinas } 3659703d9d7SCatalin Marinas } 3669703d9d7SCatalin Marinas 3674c7aa002SJavi Merino u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 3684c7aa002SJavi Merino 3699703d9d7SCatalin Marinas void __init setup_arch(char **cmdline_p) 3709703d9d7SCatalin Marinas { 3719703d9d7SCatalin Marinas setup_processor(); 3729703d9d7SCatalin Marinas 3739703d9d7SCatalin Marinas setup_machine_fdt(__fdt_pointer); 3749703d9d7SCatalin Marinas 3759703d9d7SCatalin Marinas init_mm.start_code = (unsigned long) _text; 3769703d9d7SCatalin Marinas init_mm.end_code = (unsigned long) _etext; 3779703d9d7SCatalin Marinas init_mm.end_data = (unsigned long) _edata; 3789703d9d7SCatalin Marinas init_mm.brk = (unsigned long) _end; 3799703d9d7SCatalin Marinas 3809703d9d7SCatalin Marinas *cmdline_p = boot_command_line; 3819703d9d7SCatalin Marinas 382af86e597SLaura Abbott early_fixmap_init(); 383bf4b558eSMark Salter early_ioremap_init(); 3840bf757c7SMark Salter 3859703d9d7SCatalin Marinas parse_early_param(); 3869703d9d7SCatalin Marinas 3877a9c43beSJon Masters /* 3887a9c43beSJon Masters * Unmask asynchronous aborts after bringing up possible earlycon. 3897a9c43beSJon Masters * (Report possible System Errors once we can report this occurred) 3907a9c43beSJon Masters */ 3917a9c43beSJon Masters local_async_enable(); 3927a9c43beSJon Masters 393f84d0275SMark Salter efi_init(); 3949703d9d7SCatalin Marinas arm64_memblock_init(); 3959703d9d7SCatalin Marinas 3969703d9d7SCatalin Marinas paging_init(); 3979703d9d7SCatalin Marinas request_standard_resources(); 3989703d9d7SCatalin Marinas 3990e63ea48SArd Biesheuvel early_ioremap_reset(); 400f84d0275SMark Salter 4019703d9d7SCatalin Marinas unflatten_device_tree(); 4029703d9d7SCatalin Marinas 403e790f1deSWill Deacon psci_init(); 404e790f1deSWill Deacon 405e8765b26SMark Rutland cpu_read_bootcpu_ops(); 4069703d9d7SCatalin Marinas #ifdef CONFIG_SMP 4079703d9d7SCatalin Marinas smp_init_cpus(); 408976d7d3fSLorenzo Pieralisi smp_build_mpidr_hash(); 4099703d9d7SCatalin Marinas #endif 4109703d9d7SCatalin Marinas 4119703d9d7SCatalin Marinas #ifdef CONFIG_VT 4129703d9d7SCatalin Marinas #if defined(CONFIG_VGA_CONSOLE) 4139703d9d7SCatalin Marinas conswitchp = &vga_con; 4149703d9d7SCatalin Marinas #elif defined(CONFIG_DUMMY_CONSOLE) 4159703d9d7SCatalin Marinas conswitchp = &dummy_con; 4169703d9d7SCatalin Marinas #endif 4179703d9d7SCatalin Marinas #endif 4189703d9d7SCatalin Marinas } 4199703d9d7SCatalin Marinas 420c560ecfeSCatalin Marinas static int __init arm64_device_init(void) 421de79a64dSCatalin Marinas { 42278d51e0bSRobin Murphy of_iommu_init(); 423c560ecfeSCatalin Marinas of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 424de79a64dSCatalin Marinas return 0; 425de79a64dSCatalin Marinas } 4266ecba8ebSCatalin Marinas arch_initcall_sync(arm64_device_init); 427de79a64dSCatalin Marinas 4289703d9d7SCatalin Marinas static int __init topology_init(void) 4299703d9d7SCatalin Marinas { 4309703d9d7SCatalin Marinas int i; 4319703d9d7SCatalin Marinas 4329703d9d7SCatalin Marinas for_each_possible_cpu(i) { 433df857416SMark Rutland struct cpu *cpu = &per_cpu(cpu_data.cpu, i); 4349703d9d7SCatalin Marinas cpu->hotpluggable = 1; 4359703d9d7SCatalin Marinas register_cpu(cpu, i); 4369703d9d7SCatalin Marinas } 4379703d9d7SCatalin Marinas 4389703d9d7SCatalin Marinas return 0; 4399703d9d7SCatalin Marinas } 4409703d9d7SCatalin Marinas subsys_initcall(topology_init); 4419703d9d7SCatalin Marinas 4429703d9d7SCatalin Marinas static const char *hwcap_str[] = { 4439703d9d7SCatalin Marinas "fp", 4449703d9d7SCatalin Marinas "asimd", 44546efe547SSudeep KarkadaNagesha "evtstrm", 4464bff28ccSSteve Capper "aes", 4474bff28ccSSteve Capper "pmull", 4484bff28ccSSteve Capper "sha1", 4494bff28ccSSteve Capper "sha2", 4504bff28ccSSteve Capper "crc32", 4519703d9d7SCatalin Marinas NULL 4529703d9d7SCatalin Marinas }; 4539703d9d7SCatalin Marinas 45444b82b77SMark Rutland #ifdef CONFIG_COMPAT 45544b82b77SMark Rutland static const char *compat_hwcap_str[] = { 45644b82b77SMark Rutland "swp", 45744b82b77SMark Rutland "half", 45844b82b77SMark Rutland "thumb", 45944b82b77SMark Rutland "26bit", 46044b82b77SMark Rutland "fastmult", 46144b82b77SMark Rutland "fpa", 46244b82b77SMark Rutland "vfp", 46344b82b77SMark Rutland "edsp", 46444b82b77SMark Rutland "java", 46544b82b77SMark Rutland "iwmmxt", 46644b82b77SMark Rutland "crunch", 46744b82b77SMark Rutland "thumbee", 46844b82b77SMark Rutland "neon", 46944b82b77SMark Rutland "vfpv3", 47044b82b77SMark Rutland "vfpv3d16", 47144b82b77SMark Rutland "tls", 47244b82b77SMark Rutland "vfpv4", 47344b82b77SMark Rutland "idiva", 47444b82b77SMark Rutland "idivt", 47544b82b77SMark Rutland "vfpd32", 47644b82b77SMark Rutland "lpae", 47744b82b77SMark Rutland "evtstrm" 47844b82b77SMark Rutland }; 47944b82b77SMark Rutland 48044b82b77SMark Rutland static const char *compat_hwcap2_str[] = { 48144b82b77SMark Rutland "aes", 48244b82b77SMark Rutland "pmull", 48344b82b77SMark Rutland "sha1", 48444b82b77SMark Rutland "sha2", 48544b82b77SMark Rutland "crc32", 48644b82b77SMark Rutland NULL 48744b82b77SMark Rutland }; 48844b82b77SMark Rutland #endif /* CONFIG_COMPAT */ 48944b82b77SMark Rutland 4909703d9d7SCatalin Marinas static int c_show(struct seq_file *m, void *v) 4919703d9d7SCatalin Marinas { 49244b82b77SMark Rutland int i, j; 4939703d9d7SCatalin Marinas 4949703d9d7SCatalin Marinas for_each_online_cpu(i) { 49544b82b77SMark Rutland struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 49644b82b77SMark Rutland u32 midr = cpuinfo->reg_midr; 49744b82b77SMark Rutland 4989703d9d7SCatalin Marinas /* 4999703d9d7SCatalin Marinas * glibc reads /proc/cpuinfo to determine the number of 5009703d9d7SCatalin Marinas * online processors, looking for lines beginning with 5019703d9d7SCatalin Marinas * "processor". Give glibc what it expects. 5029703d9d7SCatalin Marinas */ 5039703d9d7SCatalin Marinas #ifdef CONFIG_SMP 5049703d9d7SCatalin Marinas seq_printf(m, "processor\t: %d\n", i); 5059703d9d7SCatalin Marinas #endif 5069703d9d7SCatalin Marinas 50744b82b77SMark Rutland /* 50844b82b77SMark Rutland * Dump out the common processor features in a single line. 50944b82b77SMark Rutland * Userspace should read the hwcaps with getauxval(AT_HWCAP) 51044b82b77SMark Rutland * rather than attempting to parse this, but there's a body of 51144b82b77SMark Rutland * software which does already (at least for 32-bit). 51244b82b77SMark Rutland */ 5135e39977eSWill Deacon seq_puts(m, "Features\t:"); 51444b82b77SMark Rutland if (personality(current->personality) == PER_LINUX32) { 51544b82b77SMark Rutland #ifdef CONFIG_COMPAT 51644b82b77SMark Rutland for (j = 0; compat_hwcap_str[j]; j++) 51744b82b77SMark Rutland if (compat_elf_hwcap & (1 << j)) 51844b82b77SMark Rutland seq_printf(m, " %s", compat_hwcap_str[j]); 5195e39977eSWill Deacon 52044b82b77SMark Rutland for (j = 0; compat_hwcap2_str[j]; j++) 52144b82b77SMark Rutland if (compat_elf_hwcap2 & (1 << j)) 52244b82b77SMark Rutland seq_printf(m, " %s", compat_hwcap2_str[j]); 52344b82b77SMark Rutland #endif /* CONFIG_COMPAT */ 52444b82b77SMark Rutland } else { 52544b82b77SMark Rutland for (j = 0; hwcap_str[j]; j++) 52644b82b77SMark Rutland if (elf_hwcap & (1 << j)) 52744b82b77SMark Rutland seq_printf(m, " %s", hwcap_str[j]); 52844b82b77SMark Rutland } 5295e39977eSWill Deacon seq_puts(m, "\n"); 5305e39977eSWill Deacon 53144b82b77SMark Rutland seq_printf(m, "CPU implementer\t: 0x%02x\n", 53244b82b77SMark Rutland MIDR_IMPLEMENTOR(midr)); 53344b82b77SMark Rutland seq_printf(m, "CPU architecture: 8\n"); 53444b82b77SMark Rutland seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 53544b82b77SMark Rutland seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 53644b82b77SMark Rutland seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 53744b82b77SMark Rutland } 5385e39977eSWill Deacon 5399703d9d7SCatalin Marinas return 0; 5409703d9d7SCatalin Marinas } 5419703d9d7SCatalin Marinas 5429703d9d7SCatalin Marinas static void *c_start(struct seq_file *m, loff_t *pos) 5439703d9d7SCatalin Marinas { 5449703d9d7SCatalin Marinas return *pos < 1 ? (void *)1 : NULL; 5459703d9d7SCatalin Marinas } 5469703d9d7SCatalin Marinas 5479703d9d7SCatalin Marinas static void *c_next(struct seq_file *m, void *v, loff_t *pos) 5489703d9d7SCatalin Marinas { 5499703d9d7SCatalin Marinas ++*pos; 5509703d9d7SCatalin Marinas return NULL; 5519703d9d7SCatalin Marinas } 5529703d9d7SCatalin Marinas 5539703d9d7SCatalin Marinas static void c_stop(struct seq_file *m, void *v) 5549703d9d7SCatalin Marinas { 5559703d9d7SCatalin Marinas } 5569703d9d7SCatalin Marinas 5579703d9d7SCatalin Marinas const struct seq_operations cpuinfo_op = { 5589703d9d7SCatalin Marinas .start = c_start, 5599703d9d7SCatalin Marinas .next = c_next, 5609703d9d7SCatalin Marinas .stop = c_stop, 5619703d9d7SCatalin Marinas .show = c_show 5629703d9d7SCatalin Marinas }; 563