19703d9d7SCatalin Marinas /* 29703d9d7SCatalin Marinas * Based on arch/arm/kernel/setup.c 39703d9d7SCatalin Marinas * 49703d9d7SCatalin Marinas * Copyright (C) 1995-2001 Russell King 59703d9d7SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 69703d9d7SCatalin Marinas * 79703d9d7SCatalin Marinas * This program is free software; you can redistribute it and/or modify 89703d9d7SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 99703d9d7SCatalin Marinas * published by the Free Software Foundation. 109703d9d7SCatalin Marinas * 119703d9d7SCatalin Marinas * This program is distributed in the hope that it will be useful, 129703d9d7SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 139703d9d7SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 149703d9d7SCatalin Marinas * GNU General Public License for more details. 159703d9d7SCatalin Marinas * 169703d9d7SCatalin Marinas * You should have received a copy of the GNU General Public License 179703d9d7SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 189703d9d7SCatalin Marinas */ 199703d9d7SCatalin Marinas 209703d9d7SCatalin Marinas #include <linux/export.h> 219703d9d7SCatalin Marinas #include <linux/kernel.h> 229703d9d7SCatalin Marinas #include <linux/stddef.h> 239703d9d7SCatalin Marinas #include <linux/ioport.h> 249703d9d7SCatalin Marinas #include <linux/delay.h> 259703d9d7SCatalin Marinas #include <linux/utsname.h> 269703d9d7SCatalin Marinas #include <linux/initrd.h> 279703d9d7SCatalin Marinas #include <linux/console.h> 289703d9d7SCatalin Marinas #include <linux/bootmem.h> 299703d9d7SCatalin Marinas #include <linux/seq_file.h> 309703d9d7SCatalin Marinas #include <linux/screen_info.h> 319703d9d7SCatalin Marinas #include <linux/init.h> 329703d9d7SCatalin Marinas #include <linux/kexec.h> 339703d9d7SCatalin Marinas #include <linux/crash_dump.h> 349703d9d7SCatalin Marinas #include <linux/root_dev.h> 35de79a64dSCatalin Marinas #include <linux/clk-provider.h> 369703d9d7SCatalin Marinas #include <linux/cpu.h> 379703d9d7SCatalin Marinas #include <linux/interrupt.h> 389703d9d7SCatalin Marinas #include <linux/smp.h> 399703d9d7SCatalin Marinas #include <linux/fs.h> 409703d9d7SCatalin Marinas #include <linux/proc_fs.h> 419703d9d7SCatalin Marinas #include <linux/memblock.h> 429703d9d7SCatalin Marinas #include <linux/of_fdt.h> 43d6bafb9bSCatalin Marinas #include <linux/of_platform.h> 449703d9d7SCatalin Marinas 459703d9d7SCatalin Marinas #include <asm/cputype.h> 469703d9d7SCatalin Marinas #include <asm/elf.h> 479703d9d7SCatalin Marinas #include <asm/cputable.h> 48e8765b26SMark Rutland #include <asm/cpu_ops.h> 499703d9d7SCatalin Marinas #include <asm/sections.h> 509703d9d7SCatalin Marinas #include <asm/setup.h> 514c7aa002SJavi Merino #include <asm/smp_plat.h> 529703d9d7SCatalin Marinas #include <asm/cacheflush.h> 539703d9d7SCatalin Marinas #include <asm/tlbflush.h> 549703d9d7SCatalin Marinas #include <asm/traps.h> 559703d9d7SCatalin Marinas #include <asm/memblock.h> 56e790f1deSWill Deacon #include <asm/psci.h> 579703d9d7SCatalin Marinas 589703d9d7SCatalin Marinas unsigned int processor_id; 599703d9d7SCatalin Marinas EXPORT_SYMBOL(processor_id); 609703d9d7SCatalin Marinas 6125804e6aSSteve Capper unsigned long elf_hwcap __read_mostly; 629703d9d7SCatalin Marinas EXPORT_SYMBOL_GPL(elf_hwcap); 639703d9d7SCatalin Marinas 6446efe547SSudeep KarkadaNagesha #ifdef CONFIG_COMPAT 6546efe547SSudeep KarkadaNagesha #define COMPAT_ELF_HWCAP_DEFAULT \ 6646efe547SSudeep KarkadaNagesha (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 6746efe547SSudeep KarkadaNagesha COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 6846efe547SSudeep KarkadaNagesha COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 6946efe547SSudeep KarkadaNagesha COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 7046efe547SSudeep KarkadaNagesha COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) 7146efe547SSudeep KarkadaNagesha unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 7246efe547SSudeep KarkadaNagesha #endif 7346efe547SSudeep KarkadaNagesha 749703d9d7SCatalin Marinas static const char *cpu_name; 759703d9d7SCatalin Marinas static const char *machine_name; 769703d9d7SCatalin Marinas phys_addr_t __fdt_pointer __initdata; 779703d9d7SCatalin Marinas 789703d9d7SCatalin Marinas /* 799703d9d7SCatalin Marinas * Standard memory resources 809703d9d7SCatalin Marinas */ 819703d9d7SCatalin Marinas static struct resource mem_res[] = { 829703d9d7SCatalin Marinas { 839703d9d7SCatalin Marinas .name = "Kernel code", 849703d9d7SCatalin Marinas .start = 0, 859703d9d7SCatalin Marinas .end = 0, 869703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 879703d9d7SCatalin Marinas }, 889703d9d7SCatalin Marinas { 899703d9d7SCatalin Marinas .name = "Kernel data", 909703d9d7SCatalin Marinas .start = 0, 919703d9d7SCatalin Marinas .end = 0, 929703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 939703d9d7SCatalin Marinas } 949703d9d7SCatalin Marinas }; 959703d9d7SCatalin Marinas 969703d9d7SCatalin Marinas #define kernel_code mem_res[0] 979703d9d7SCatalin Marinas #define kernel_data mem_res[1] 989703d9d7SCatalin Marinas 999703d9d7SCatalin Marinas void __init early_print(const char *str, ...) 1009703d9d7SCatalin Marinas { 1019703d9d7SCatalin Marinas char buf[256]; 1029703d9d7SCatalin Marinas va_list ap; 1039703d9d7SCatalin Marinas 1049703d9d7SCatalin Marinas va_start(ap, str); 1059703d9d7SCatalin Marinas vsnprintf(buf, sizeof(buf), str, ap); 1069703d9d7SCatalin Marinas va_end(ap); 1079703d9d7SCatalin Marinas 1089703d9d7SCatalin Marinas printk("%s", buf); 1099703d9d7SCatalin Marinas } 1109703d9d7SCatalin Marinas 1116e15d0e0SSudeep KarkadaNagesha bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 1126e15d0e0SSudeep KarkadaNagesha { 1136e15d0e0SSudeep KarkadaNagesha return phys_id == cpu_logical_map(cpu); 1146e15d0e0SSudeep KarkadaNagesha } 1156e15d0e0SSudeep KarkadaNagesha 116976d7d3fSLorenzo Pieralisi struct mpidr_hash mpidr_hash; 117976d7d3fSLorenzo Pieralisi #ifdef CONFIG_SMP 118976d7d3fSLorenzo Pieralisi /** 119976d7d3fSLorenzo Pieralisi * smp_build_mpidr_hash - Pre-compute shifts required at each affinity 120976d7d3fSLorenzo Pieralisi * level in order to build a linear index from an 121976d7d3fSLorenzo Pieralisi * MPIDR value. Resulting algorithm is a collision 122976d7d3fSLorenzo Pieralisi * free hash carried out through shifting and ORing 123976d7d3fSLorenzo Pieralisi */ 124976d7d3fSLorenzo Pieralisi static void __init smp_build_mpidr_hash(void) 125976d7d3fSLorenzo Pieralisi { 126976d7d3fSLorenzo Pieralisi u32 i, affinity, fs[4], bits[4], ls; 127976d7d3fSLorenzo Pieralisi u64 mask = 0; 128976d7d3fSLorenzo Pieralisi /* 129976d7d3fSLorenzo Pieralisi * Pre-scan the list of MPIDRS and filter out bits that do 130976d7d3fSLorenzo Pieralisi * not contribute to affinity levels, ie they never toggle. 131976d7d3fSLorenzo Pieralisi */ 132976d7d3fSLorenzo Pieralisi for_each_possible_cpu(i) 133976d7d3fSLorenzo Pieralisi mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); 134976d7d3fSLorenzo Pieralisi pr_debug("mask of set bits %#llx\n", mask); 135976d7d3fSLorenzo Pieralisi /* 136976d7d3fSLorenzo Pieralisi * Find and stash the last and first bit set at all affinity levels to 137976d7d3fSLorenzo Pieralisi * check how many bits are required to represent them. 138976d7d3fSLorenzo Pieralisi */ 139976d7d3fSLorenzo Pieralisi for (i = 0; i < 4; i++) { 140976d7d3fSLorenzo Pieralisi affinity = MPIDR_AFFINITY_LEVEL(mask, i); 141976d7d3fSLorenzo Pieralisi /* 142976d7d3fSLorenzo Pieralisi * Find the MSB bit and LSB bits position 143976d7d3fSLorenzo Pieralisi * to determine how many bits are required 144976d7d3fSLorenzo Pieralisi * to express the affinity level. 145976d7d3fSLorenzo Pieralisi */ 146976d7d3fSLorenzo Pieralisi ls = fls(affinity); 147976d7d3fSLorenzo Pieralisi fs[i] = affinity ? ffs(affinity) - 1 : 0; 148976d7d3fSLorenzo Pieralisi bits[i] = ls - fs[i]; 149976d7d3fSLorenzo Pieralisi } 150976d7d3fSLorenzo Pieralisi /* 151976d7d3fSLorenzo Pieralisi * An index can be created from the MPIDR_EL1 by isolating the 152976d7d3fSLorenzo Pieralisi * significant bits at each affinity level and by shifting 153976d7d3fSLorenzo Pieralisi * them in order to compress the 32 bits values space to a 154976d7d3fSLorenzo Pieralisi * compressed set of values. This is equivalent to hashing 155976d7d3fSLorenzo Pieralisi * the MPIDR_EL1 through shifting and ORing. It is a collision free 156976d7d3fSLorenzo Pieralisi * hash though not minimal since some levels might contain a number 157976d7d3fSLorenzo Pieralisi * of CPUs that is not an exact power of 2 and their bit 158976d7d3fSLorenzo Pieralisi * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. 159976d7d3fSLorenzo Pieralisi */ 160976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; 161976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; 162976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - 163976d7d3fSLorenzo Pieralisi (bits[1] + bits[0]); 164976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + 165976d7d3fSLorenzo Pieralisi fs[3] - (bits[2] + bits[1] + bits[0]); 166976d7d3fSLorenzo Pieralisi mpidr_hash.mask = mask; 167976d7d3fSLorenzo Pieralisi mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; 168976d7d3fSLorenzo Pieralisi pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", 169976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[0], 170976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[1], 171976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[2], 172976d7d3fSLorenzo Pieralisi mpidr_hash.shift_aff[3], 173976d7d3fSLorenzo Pieralisi mpidr_hash.mask, 174976d7d3fSLorenzo Pieralisi mpidr_hash.bits); 175976d7d3fSLorenzo Pieralisi /* 176976d7d3fSLorenzo Pieralisi * 4x is an arbitrary value used to warn on a hash table much bigger 177976d7d3fSLorenzo Pieralisi * than expected on most systems. 178976d7d3fSLorenzo Pieralisi */ 179976d7d3fSLorenzo Pieralisi if (mpidr_hash_size() > 4 * num_possible_cpus()) 180976d7d3fSLorenzo Pieralisi pr_warn("Large number of MPIDR hash buckets detected\n"); 181976d7d3fSLorenzo Pieralisi __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash)); 182976d7d3fSLorenzo Pieralisi } 183976d7d3fSLorenzo Pieralisi #endif 184976d7d3fSLorenzo Pieralisi 1859703d9d7SCatalin Marinas static void __init setup_processor(void) 1869703d9d7SCatalin Marinas { 1879703d9d7SCatalin Marinas struct cpu_info *cpu_info; 1889703d9d7SCatalin Marinas 1899703d9d7SCatalin Marinas /* 1909703d9d7SCatalin Marinas * locate processor in the list of supported processor 1919703d9d7SCatalin Marinas * types. The linker builds this table for us from the 1929703d9d7SCatalin Marinas * entries in arch/arm/mm/proc.S 1939703d9d7SCatalin Marinas */ 1949703d9d7SCatalin Marinas cpu_info = lookup_processor_type(read_cpuid_id()); 1959703d9d7SCatalin Marinas if (!cpu_info) { 1969703d9d7SCatalin Marinas printk("CPU configuration botched (ID %08x), unable to continue.\n", 1979703d9d7SCatalin Marinas read_cpuid_id()); 1989703d9d7SCatalin Marinas while (1); 1999703d9d7SCatalin Marinas } 2009703d9d7SCatalin Marinas 2019703d9d7SCatalin Marinas cpu_name = cpu_info->cpu_name; 2029703d9d7SCatalin Marinas 2039703d9d7SCatalin Marinas printk("CPU: %s [%08x] revision %d\n", 2049703d9d7SCatalin Marinas cpu_name, read_cpuid_id(), read_cpuid_id() & 15); 2059703d9d7SCatalin Marinas 20694ed1f2cSWill Deacon sprintf(init_utsname()->machine, ELF_PLATFORM); 2079703d9d7SCatalin Marinas elf_hwcap = 0; 2089703d9d7SCatalin Marinas } 2099703d9d7SCatalin Marinas 2109703d9d7SCatalin Marinas static void __init setup_machine_fdt(phys_addr_t dt_phys) 2119703d9d7SCatalin Marinas { 212d5189cc5SRob Herring if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { 2139703d9d7SCatalin Marinas early_print("\n" 2149703d9d7SCatalin Marinas "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" 215d5189cc5SRob Herring "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" 2169703d9d7SCatalin Marinas "\nPlease check your bootloader.\n", 217d5189cc5SRob Herring dt_phys, phys_to_virt(dt_phys)); 2189703d9d7SCatalin Marinas 2199703d9d7SCatalin Marinas while (true) 2209703d9d7SCatalin Marinas cpu_relax(); 2219703d9d7SCatalin Marinas } 2229703d9d7SCatalin Marinas 223f2b99bccSRob Herring machine_name = of_flat_dt_get_machine_name(); 2249703d9d7SCatalin Marinas } 2259703d9d7SCatalin Marinas 2269703d9d7SCatalin Marinas /* 2279703d9d7SCatalin Marinas * Limit the memory size that was specified via FDT. 2289703d9d7SCatalin Marinas */ 2299703d9d7SCatalin Marinas static int __init early_mem(char *p) 2309703d9d7SCatalin Marinas { 2319703d9d7SCatalin Marinas phys_addr_t limit; 2329703d9d7SCatalin Marinas 2339703d9d7SCatalin Marinas if (!p) 2349703d9d7SCatalin Marinas return 1; 2359703d9d7SCatalin Marinas 2369703d9d7SCatalin Marinas limit = memparse(p, &p) & PAGE_MASK; 2379703d9d7SCatalin Marinas pr_notice("Memory limited to %lldMB\n", limit >> 20); 2389703d9d7SCatalin Marinas 2399703d9d7SCatalin Marinas memblock_enforce_memory_limit(limit); 2409703d9d7SCatalin Marinas 2419703d9d7SCatalin Marinas return 0; 2429703d9d7SCatalin Marinas } 2439703d9d7SCatalin Marinas early_param("mem", early_mem); 2449703d9d7SCatalin Marinas 2459703d9d7SCatalin Marinas static void __init request_standard_resources(void) 2469703d9d7SCatalin Marinas { 2479703d9d7SCatalin Marinas struct memblock_region *region; 2489703d9d7SCatalin Marinas struct resource *res; 2499703d9d7SCatalin Marinas 2509703d9d7SCatalin Marinas kernel_code.start = virt_to_phys(_text); 2519703d9d7SCatalin Marinas kernel_code.end = virt_to_phys(_etext - 1); 2529703d9d7SCatalin Marinas kernel_data.start = virt_to_phys(_sdata); 2539703d9d7SCatalin Marinas kernel_data.end = virt_to_phys(_end - 1); 2549703d9d7SCatalin Marinas 2559703d9d7SCatalin Marinas for_each_memblock(memory, region) { 2569703d9d7SCatalin Marinas res = alloc_bootmem_low(sizeof(*res)); 2579703d9d7SCatalin Marinas res->name = "System RAM"; 2589703d9d7SCatalin Marinas res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 2599703d9d7SCatalin Marinas res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 2609703d9d7SCatalin Marinas res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 2619703d9d7SCatalin Marinas 2629703d9d7SCatalin Marinas request_resource(&iomem_resource, res); 2639703d9d7SCatalin Marinas 2649703d9d7SCatalin Marinas if (kernel_code.start >= res->start && 2659703d9d7SCatalin Marinas kernel_code.end <= res->end) 2669703d9d7SCatalin Marinas request_resource(res, &kernel_code); 2679703d9d7SCatalin Marinas if (kernel_data.start >= res->start && 2689703d9d7SCatalin Marinas kernel_data.end <= res->end) 2699703d9d7SCatalin Marinas request_resource(res, &kernel_data); 2709703d9d7SCatalin Marinas } 2719703d9d7SCatalin Marinas } 2729703d9d7SCatalin Marinas 2734c7aa002SJavi Merino u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 2744c7aa002SJavi Merino 2759703d9d7SCatalin Marinas void __init setup_arch(char **cmdline_p) 2769703d9d7SCatalin Marinas { 277b3bf6aa7SCatalin Marinas /* 278b3bf6aa7SCatalin Marinas * Unmask asynchronous aborts early to catch possible system errors. 279b3bf6aa7SCatalin Marinas */ 280b3bf6aa7SCatalin Marinas local_async_enable(); 281b3bf6aa7SCatalin Marinas 2829703d9d7SCatalin Marinas setup_processor(); 2839703d9d7SCatalin Marinas 2849703d9d7SCatalin Marinas setup_machine_fdt(__fdt_pointer); 2859703d9d7SCatalin Marinas 2869703d9d7SCatalin Marinas init_mm.start_code = (unsigned long) _text; 2879703d9d7SCatalin Marinas init_mm.end_code = (unsigned long) _etext; 2889703d9d7SCatalin Marinas init_mm.end_data = (unsigned long) _edata; 2899703d9d7SCatalin Marinas init_mm.brk = (unsigned long) _end; 2909703d9d7SCatalin Marinas 2919703d9d7SCatalin Marinas *cmdline_p = boot_command_line; 2929703d9d7SCatalin Marinas 2939703d9d7SCatalin Marinas parse_early_param(); 2949703d9d7SCatalin Marinas 2959703d9d7SCatalin Marinas arm64_memblock_init(); 2969703d9d7SCatalin Marinas 2979703d9d7SCatalin Marinas paging_init(); 2989703d9d7SCatalin Marinas request_standard_resources(); 2999703d9d7SCatalin Marinas 3009703d9d7SCatalin Marinas unflatten_device_tree(); 3019703d9d7SCatalin Marinas 302e790f1deSWill Deacon psci_init(); 303e790f1deSWill Deacon 3044c7aa002SJavi Merino cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 305e8765b26SMark Rutland cpu_read_bootcpu_ops(); 3069703d9d7SCatalin Marinas #ifdef CONFIG_SMP 3079703d9d7SCatalin Marinas smp_init_cpus(); 308976d7d3fSLorenzo Pieralisi smp_build_mpidr_hash(); 3099703d9d7SCatalin Marinas #endif 3109703d9d7SCatalin Marinas 3119703d9d7SCatalin Marinas #ifdef CONFIG_VT 3129703d9d7SCatalin Marinas #if defined(CONFIG_VGA_CONSOLE) 3139703d9d7SCatalin Marinas conswitchp = &vga_con; 3149703d9d7SCatalin Marinas #elif defined(CONFIG_DUMMY_CONSOLE) 3159703d9d7SCatalin Marinas conswitchp = &dummy_con; 3169703d9d7SCatalin Marinas #endif 3179703d9d7SCatalin Marinas #endif 3189703d9d7SCatalin Marinas } 3199703d9d7SCatalin Marinas 320c560ecfeSCatalin Marinas static int __init arm64_device_init(void) 321de79a64dSCatalin Marinas { 322de79a64dSCatalin Marinas of_clk_init(NULL); 323c560ecfeSCatalin Marinas of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 324de79a64dSCatalin Marinas return 0; 325de79a64dSCatalin Marinas } 326c560ecfeSCatalin Marinas arch_initcall(arm64_device_init); 327de79a64dSCatalin Marinas 3289703d9d7SCatalin Marinas static DEFINE_PER_CPU(struct cpu, cpu_data); 3299703d9d7SCatalin Marinas 3309703d9d7SCatalin Marinas static int __init topology_init(void) 3319703d9d7SCatalin Marinas { 3329703d9d7SCatalin Marinas int i; 3339703d9d7SCatalin Marinas 3349703d9d7SCatalin Marinas for_each_possible_cpu(i) { 3359703d9d7SCatalin Marinas struct cpu *cpu = &per_cpu(cpu_data, i); 3369703d9d7SCatalin Marinas cpu->hotpluggable = 1; 3379703d9d7SCatalin Marinas register_cpu(cpu, i); 3389703d9d7SCatalin Marinas } 3399703d9d7SCatalin Marinas 3409703d9d7SCatalin Marinas return 0; 3419703d9d7SCatalin Marinas } 3429703d9d7SCatalin Marinas subsys_initcall(topology_init); 3439703d9d7SCatalin Marinas 3449703d9d7SCatalin Marinas static const char *hwcap_str[] = { 3459703d9d7SCatalin Marinas "fp", 3469703d9d7SCatalin Marinas "asimd", 34746efe547SSudeep KarkadaNagesha "evtstrm", 3489703d9d7SCatalin Marinas NULL 3499703d9d7SCatalin Marinas }; 3509703d9d7SCatalin Marinas 3519703d9d7SCatalin Marinas static int c_show(struct seq_file *m, void *v) 3529703d9d7SCatalin Marinas { 3539703d9d7SCatalin Marinas int i; 3549703d9d7SCatalin Marinas 3559703d9d7SCatalin Marinas seq_printf(m, "Processor\t: %s rev %d (%s)\n", 3569703d9d7SCatalin Marinas cpu_name, read_cpuid_id() & 15, ELF_PLATFORM); 3579703d9d7SCatalin Marinas 3589703d9d7SCatalin Marinas for_each_online_cpu(i) { 3599703d9d7SCatalin Marinas /* 3609703d9d7SCatalin Marinas * glibc reads /proc/cpuinfo to determine the number of 3619703d9d7SCatalin Marinas * online processors, looking for lines beginning with 3629703d9d7SCatalin Marinas * "processor". Give glibc what it expects. 3639703d9d7SCatalin Marinas */ 3649703d9d7SCatalin Marinas #ifdef CONFIG_SMP 3659703d9d7SCatalin Marinas seq_printf(m, "processor\t: %d\n", i); 3669703d9d7SCatalin Marinas #endif 3679703d9d7SCatalin Marinas } 3689703d9d7SCatalin Marinas 3699703d9d7SCatalin Marinas /* dump out the processor features */ 3709703d9d7SCatalin Marinas seq_puts(m, "Features\t: "); 3719703d9d7SCatalin Marinas 3729703d9d7SCatalin Marinas for (i = 0; hwcap_str[i]; i++) 3739703d9d7SCatalin Marinas if (elf_hwcap & (1 << i)) 3749703d9d7SCatalin Marinas seq_printf(m, "%s ", hwcap_str[i]); 3759703d9d7SCatalin Marinas 3769703d9d7SCatalin Marinas seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24); 3779703d9d7SCatalin Marinas seq_printf(m, "CPU architecture: AArch64\n"); 3789703d9d7SCatalin Marinas seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15); 3799703d9d7SCatalin Marinas seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff); 3809703d9d7SCatalin Marinas seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15); 3819703d9d7SCatalin Marinas 3829703d9d7SCatalin Marinas seq_puts(m, "\n"); 3839703d9d7SCatalin Marinas 3849703d9d7SCatalin Marinas seq_printf(m, "Hardware\t: %s\n", machine_name); 3859703d9d7SCatalin Marinas 3869703d9d7SCatalin Marinas return 0; 3879703d9d7SCatalin Marinas } 3889703d9d7SCatalin Marinas 3899703d9d7SCatalin Marinas static void *c_start(struct seq_file *m, loff_t *pos) 3909703d9d7SCatalin Marinas { 3919703d9d7SCatalin Marinas return *pos < 1 ? (void *)1 : NULL; 3929703d9d7SCatalin Marinas } 3939703d9d7SCatalin Marinas 3949703d9d7SCatalin Marinas static void *c_next(struct seq_file *m, void *v, loff_t *pos) 3959703d9d7SCatalin Marinas { 3969703d9d7SCatalin Marinas ++*pos; 3979703d9d7SCatalin Marinas return NULL; 3989703d9d7SCatalin Marinas } 3999703d9d7SCatalin Marinas 4009703d9d7SCatalin Marinas static void c_stop(struct seq_file *m, void *v) 4019703d9d7SCatalin Marinas { 4029703d9d7SCatalin Marinas } 4039703d9d7SCatalin Marinas 4049703d9d7SCatalin Marinas const struct seq_operations cpuinfo_op = { 4059703d9d7SCatalin Marinas .start = c_start, 4069703d9d7SCatalin Marinas .next = c_next, 4079703d9d7SCatalin Marinas .stop = c_stop, 4089703d9d7SCatalin Marinas .show = c_show 4099703d9d7SCatalin Marinas }; 410