19703d9d7SCatalin Marinas /* 29703d9d7SCatalin Marinas * Based on arch/arm/kernel/setup.c 39703d9d7SCatalin Marinas * 49703d9d7SCatalin Marinas * Copyright (C) 1995-2001 Russell King 59703d9d7SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 69703d9d7SCatalin Marinas * 79703d9d7SCatalin Marinas * This program is free software; you can redistribute it and/or modify 89703d9d7SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 99703d9d7SCatalin Marinas * published by the Free Software Foundation. 109703d9d7SCatalin Marinas * 119703d9d7SCatalin Marinas * This program is distributed in the hope that it will be useful, 129703d9d7SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 139703d9d7SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 149703d9d7SCatalin Marinas * GNU General Public License for more details. 159703d9d7SCatalin Marinas * 169703d9d7SCatalin Marinas * You should have received a copy of the GNU General Public License 179703d9d7SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 189703d9d7SCatalin Marinas */ 199703d9d7SCatalin Marinas 209703d9d7SCatalin Marinas #include <linux/export.h> 219703d9d7SCatalin Marinas #include <linux/kernel.h> 229703d9d7SCatalin Marinas #include <linux/stddef.h> 239703d9d7SCatalin Marinas #include <linux/ioport.h> 249703d9d7SCatalin Marinas #include <linux/delay.h> 259703d9d7SCatalin Marinas #include <linux/utsname.h> 269703d9d7SCatalin Marinas #include <linux/initrd.h> 279703d9d7SCatalin Marinas #include <linux/console.h> 289703d9d7SCatalin Marinas #include <linux/bootmem.h> 299703d9d7SCatalin Marinas #include <linux/seq_file.h> 309703d9d7SCatalin Marinas #include <linux/screen_info.h> 319703d9d7SCatalin Marinas #include <linux/init.h> 329703d9d7SCatalin Marinas #include <linux/kexec.h> 339703d9d7SCatalin Marinas #include <linux/crash_dump.h> 349703d9d7SCatalin Marinas #include <linux/root_dev.h> 35de79a64dSCatalin Marinas #include <linux/clk-provider.h> 369703d9d7SCatalin Marinas #include <linux/cpu.h> 379703d9d7SCatalin Marinas #include <linux/interrupt.h> 389703d9d7SCatalin Marinas #include <linux/smp.h> 399703d9d7SCatalin Marinas #include <linux/fs.h> 409703d9d7SCatalin Marinas #include <linux/proc_fs.h> 419703d9d7SCatalin Marinas #include <linux/memblock.h> 429703d9d7SCatalin Marinas #include <linux/of_fdt.h> 43d6bafb9bSCatalin Marinas #include <linux/of_platform.h> 449703d9d7SCatalin Marinas 459703d9d7SCatalin Marinas #include <asm/cputype.h> 469703d9d7SCatalin Marinas #include <asm/elf.h> 479703d9d7SCatalin Marinas #include <asm/cputable.h> 48e8765b26SMark Rutland #include <asm/cpu_ops.h> 499703d9d7SCatalin Marinas #include <asm/sections.h> 509703d9d7SCatalin Marinas #include <asm/setup.h> 514c7aa002SJavi Merino #include <asm/smp_plat.h> 529703d9d7SCatalin Marinas #include <asm/cacheflush.h> 539703d9d7SCatalin Marinas #include <asm/tlbflush.h> 549703d9d7SCatalin Marinas #include <asm/traps.h> 559703d9d7SCatalin Marinas #include <asm/memblock.h> 56e790f1deSWill Deacon #include <asm/psci.h> 579703d9d7SCatalin Marinas 589703d9d7SCatalin Marinas unsigned int processor_id; 599703d9d7SCatalin Marinas EXPORT_SYMBOL(processor_id); 609703d9d7SCatalin Marinas 6125804e6aSSteve Capper unsigned long elf_hwcap __read_mostly; 629703d9d7SCatalin Marinas EXPORT_SYMBOL_GPL(elf_hwcap); 639703d9d7SCatalin Marinas 6446efe547SSudeep KarkadaNagesha #ifdef CONFIG_COMPAT 6546efe547SSudeep KarkadaNagesha #define COMPAT_ELF_HWCAP_DEFAULT \ 6646efe547SSudeep KarkadaNagesha (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 6746efe547SSudeep KarkadaNagesha COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 6846efe547SSudeep KarkadaNagesha COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 6946efe547SSudeep KarkadaNagesha COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 7046efe547SSudeep KarkadaNagesha COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) 7146efe547SSudeep KarkadaNagesha unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 7246efe547SSudeep KarkadaNagesha #endif 7346efe547SSudeep KarkadaNagesha 749703d9d7SCatalin Marinas static const char *cpu_name; 759703d9d7SCatalin Marinas static const char *machine_name; 769703d9d7SCatalin Marinas phys_addr_t __fdt_pointer __initdata; 779703d9d7SCatalin Marinas 789703d9d7SCatalin Marinas /* 799703d9d7SCatalin Marinas * Standard memory resources 809703d9d7SCatalin Marinas */ 819703d9d7SCatalin Marinas static struct resource mem_res[] = { 829703d9d7SCatalin Marinas { 839703d9d7SCatalin Marinas .name = "Kernel code", 849703d9d7SCatalin Marinas .start = 0, 859703d9d7SCatalin Marinas .end = 0, 869703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 879703d9d7SCatalin Marinas }, 889703d9d7SCatalin Marinas { 899703d9d7SCatalin Marinas .name = "Kernel data", 909703d9d7SCatalin Marinas .start = 0, 919703d9d7SCatalin Marinas .end = 0, 929703d9d7SCatalin Marinas .flags = IORESOURCE_MEM 939703d9d7SCatalin Marinas } 949703d9d7SCatalin Marinas }; 959703d9d7SCatalin Marinas 969703d9d7SCatalin Marinas #define kernel_code mem_res[0] 979703d9d7SCatalin Marinas #define kernel_data mem_res[1] 989703d9d7SCatalin Marinas 999703d9d7SCatalin Marinas void __init early_print(const char *str, ...) 1009703d9d7SCatalin Marinas { 1019703d9d7SCatalin Marinas char buf[256]; 1029703d9d7SCatalin Marinas va_list ap; 1039703d9d7SCatalin Marinas 1049703d9d7SCatalin Marinas va_start(ap, str); 1059703d9d7SCatalin Marinas vsnprintf(buf, sizeof(buf), str, ap); 1069703d9d7SCatalin Marinas va_end(ap); 1079703d9d7SCatalin Marinas 1089703d9d7SCatalin Marinas printk("%s", buf); 1099703d9d7SCatalin Marinas } 1109703d9d7SCatalin Marinas 11171586276SWill Deacon void __init smp_setup_processor_id(void) 11271586276SWill Deacon { 11371586276SWill Deacon /* 11471586276SWill Deacon * clear __my_cpu_offset on boot CPU to avoid hang caused by 11571586276SWill Deacon * using percpu variable early, for example, lockdep will 11671586276SWill Deacon * access percpu variable inside lock_release 11771586276SWill Deacon */ 11871586276SWill Deacon set_my_cpu_offset(0); 11971586276SWill Deacon } 12071586276SWill Deacon 1216e15d0e0SSudeep KarkadaNagesha bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 1226e15d0e0SSudeep KarkadaNagesha { 1236e15d0e0SSudeep KarkadaNagesha return phys_id == cpu_logical_map(cpu); 1246e15d0e0SSudeep KarkadaNagesha } 1256e15d0e0SSudeep KarkadaNagesha 1269703d9d7SCatalin Marinas static void __init setup_processor(void) 1279703d9d7SCatalin Marinas { 1289703d9d7SCatalin Marinas struct cpu_info *cpu_info; 1294bff28ccSSteve Capper u64 features, block; 1309703d9d7SCatalin Marinas 1319703d9d7SCatalin Marinas cpu_info = lookup_processor_type(read_cpuid_id()); 1329703d9d7SCatalin Marinas if (!cpu_info) { 1339703d9d7SCatalin Marinas printk("CPU configuration botched (ID %08x), unable to continue.\n", 1349703d9d7SCatalin Marinas read_cpuid_id()); 1359703d9d7SCatalin Marinas while (1); 1369703d9d7SCatalin Marinas } 1379703d9d7SCatalin Marinas 1389703d9d7SCatalin Marinas cpu_name = cpu_info->cpu_name; 1399703d9d7SCatalin Marinas 1409703d9d7SCatalin Marinas printk("CPU: %s [%08x] revision %d\n", 1419703d9d7SCatalin Marinas cpu_name, read_cpuid_id(), read_cpuid_id() & 15); 1429703d9d7SCatalin Marinas 14394ed1f2cSWill Deacon sprintf(init_utsname()->machine, ELF_PLATFORM); 1449703d9d7SCatalin Marinas elf_hwcap = 0; 1454bff28ccSSteve Capper 1464bff28ccSSteve Capper /* 1474bff28ccSSteve Capper * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. 1484bff28ccSSteve Capper * The blocks we test below represent incremental functionality 1494bff28ccSSteve Capper * for non-negative values. Negative values are reserved. 1504bff28ccSSteve Capper */ 1514bff28ccSSteve Capper features = read_cpuid(ID_AA64ISAR0_EL1); 1524bff28ccSSteve Capper block = (features >> 4) & 0xf; 1534bff28ccSSteve Capper if (!(block & 0x8)) { 1544bff28ccSSteve Capper switch (block) { 1554bff28ccSSteve Capper default: 1564bff28ccSSteve Capper case 2: 1574bff28ccSSteve Capper elf_hwcap |= HWCAP_PMULL; 1584bff28ccSSteve Capper case 1: 1594bff28ccSSteve Capper elf_hwcap |= HWCAP_AES; 1604bff28ccSSteve Capper case 0: 1614bff28ccSSteve Capper break; 1624bff28ccSSteve Capper } 1634bff28ccSSteve Capper } 1644bff28ccSSteve Capper 1654bff28ccSSteve Capper block = (features >> 8) & 0xf; 1664bff28ccSSteve Capper if (block && !(block & 0x8)) 1674bff28ccSSteve Capper elf_hwcap |= HWCAP_SHA1; 1684bff28ccSSteve Capper 1694bff28ccSSteve Capper block = (features >> 12) & 0xf; 1704bff28ccSSteve Capper if (block && !(block & 0x8)) 1714bff28ccSSteve Capper elf_hwcap |= HWCAP_SHA2; 1724bff28ccSSteve Capper 1734bff28ccSSteve Capper block = (features >> 16) & 0xf; 1744bff28ccSSteve Capper if (block && !(block & 0x8)) 1754bff28ccSSteve Capper elf_hwcap |= HWCAP_CRC32; 1769703d9d7SCatalin Marinas } 1779703d9d7SCatalin Marinas 1789703d9d7SCatalin Marinas static void __init setup_machine_fdt(phys_addr_t dt_phys) 1799703d9d7SCatalin Marinas { 180d5189cc5SRob Herring if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { 1819703d9d7SCatalin Marinas early_print("\n" 1829703d9d7SCatalin Marinas "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" 183d5189cc5SRob Herring "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" 1849703d9d7SCatalin Marinas "\nPlease check your bootloader.\n", 185d5189cc5SRob Herring dt_phys, phys_to_virt(dt_phys)); 1869703d9d7SCatalin Marinas 1879703d9d7SCatalin Marinas while (true) 1889703d9d7SCatalin Marinas cpu_relax(); 1899703d9d7SCatalin Marinas } 1909703d9d7SCatalin Marinas 191f2b99bccSRob Herring machine_name = of_flat_dt_get_machine_name(); 1929703d9d7SCatalin Marinas } 1939703d9d7SCatalin Marinas 1949703d9d7SCatalin Marinas /* 1959703d9d7SCatalin Marinas * Limit the memory size that was specified via FDT. 1969703d9d7SCatalin Marinas */ 1979703d9d7SCatalin Marinas static int __init early_mem(char *p) 1989703d9d7SCatalin Marinas { 1999703d9d7SCatalin Marinas phys_addr_t limit; 2009703d9d7SCatalin Marinas 2019703d9d7SCatalin Marinas if (!p) 2029703d9d7SCatalin Marinas return 1; 2039703d9d7SCatalin Marinas 2049703d9d7SCatalin Marinas limit = memparse(p, &p) & PAGE_MASK; 2059703d9d7SCatalin Marinas pr_notice("Memory limited to %lldMB\n", limit >> 20); 2069703d9d7SCatalin Marinas 2079703d9d7SCatalin Marinas memblock_enforce_memory_limit(limit); 2089703d9d7SCatalin Marinas 2099703d9d7SCatalin Marinas return 0; 2109703d9d7SCatalin Marinas } 2119703d9d7SCatalin Marinas early_param("mem", early_mem); 2129703d9d7SCatalin Marinas 2139703d9d7SCatalin Marinas static void __init request_standard_resources(void) 2149703d9d7SCatalin Marinas { 2159703d9d7SCatalin Marinas struct memblock_region *region; 2169703d9d7SCatalin Marinas struct resource *res; 2179703d9d7SCatalin Marinas 2189703d9d7SCatalin Marinas kernel_code.start = virt_to_phys(_text); 2199703d9d7SCatalin Marinas kernel_code.end = virt_to_phys(_etext - 1); 2209703d9d7SCatalin Marinas kernel_data.start = virt_to_phys(_sdata); 2219703d9d7SCatalin Marinas kernel_data.end = virt_to_phys(_end - 1); 2229703d9d7SCatalin Marinas 2239703d9d7SCatalin Marinas for_each_memblock(memory, region) { 2249703d9d7SCatalin Marinas res = alloc_bootmem_low(sizeof(*res)); 2259703d9d7SCatalin Marinas res->name = "System RAM"; 2269703d9d7SCatalin Marinas res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); 2279703d9d7SCatalin Marinas res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; 2289703d9d7SCatalin Marinas res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 2299703d9d7SCatalin Marinas 2309703d9d7SCatalin Marinas request_resource(&iomem_resource, res); 2319703d9d7SCatalin Marinas 2329703d9d7SCatalin Marinas if (kernel_code.start >= res->start && 2339703d9d7SCatalin Marinas kernel_code.end <= res->end) 2349703d9d7SCatalin Marinas request_resource(res, &kernel_code); 2359703d9d7SCatalin Marinas if (kernel_data.start >= res->start && 2369703d9d7SCatalin Marinas kernel_data.end <= res->end) 2379703d9d7SCatalin Marinas request_resource(res, &kernel_data); 2389703d9d7SCatalin Marinas } 2399703d9d7SCatalin Marinas } 2409703d9d7SCatalin Marinas 2414c7aa002SJavi Merino u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; 2424c7aa002SJavi Merino 2439703d9d7SCatalin Marinas void __init setup_arch(char **cmdline_p) 2449703d9d7SCatalin Marinas { 245b3bf6aa7SCatalin Marinas /* 246b3bf6aa7SCatalin Marinas * Unmask asynchronous aborts early to catch possible system errors. 247b3bf6aa7SCatalin Marinas */ 248b3bf6aa7SCatalin Marinas local_async_enable(); 249b3bf6aa7SCatalin Marinas 2509703d9d7SCatalin Marinas setup_processor(); 2519703d9d7SCatalin Marinas 2529703d9d7SCatalin Marinas setup_machine_fdt(__fdt_pointer); 2539703d9d7SCatalin Marinas 2549703d9d7SCatalin Marinas init_mm.start_code = (unsigned long) _text; 2559703d9d7SCatalin Marinas init_mm.end_code = (unsigned long) _etext; 2569703d9d7SCatalin Marinas init_mm.end_data = (unsigned long) _edata; 2579703d9d7SCatalin Marinas init_mm.brk = (unsigned long) _end; 2589703d9d7SCatalin Marinas 2599703d9d7SCatalin Marinas *cmdline_p = boot_command_line; 2609703d9d7SCatalin Marinas 2619703d9d7SCatalin Marinas parse_early_param(); 2629703d9d7SCatalin Marinas 2639703d9d7SCatalin Marinas arm64_memblock_init(); 2649703d9d7SCatalin Marinas 2659703d9d7SCatalin Marinas paging_init(); 2669703d9d7SCatalin Marinas request_standard_resources(); 2679703d9d7SCatalin Marinas 2689703d9d7SCatalin Marinas unflatten_device_tree(); 2699703d9d7SCatalin Marinas 270e790f1deSWill Deacon psci_init(); 271e790f1deSWill Deacon 2724c7aa002SJavi Merino cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 273e8765b26SMark Rutland cpu_read_bootcpu_ops(); 2749703d9d7SCatalin Marinas #ifdef CONFIG_SMP 2759703d9d7SCatalin Marinas smp_init_cpus(); 2769703d9d7SCatalin Marinas #endif 2779703d9d7SCatalin Marinas 2789703d9d7SCatalin Marinas #ifdef CONFIG_VT 2799703d9d7SCatalin Marinas #if defined(CONFIG_VGA_CONSOLE) 2809703d9d7SCatalin Marinas conswitchp = &vga_con; 2819703d9d7SCatalin Marinas #elif defined(CONFIG_DUMMY_CONSOLE) 2829703d9d7SCatalin Marinas conswitchp = &dummy_con; 2839703d9d7SCatalin Marinas #endif 2849703d9d7SCatalin Marinas #endif 2859703d9d7SCatalin Marinas } 2869703d9d7SCatalin Marinas 287c560ecfeSCatalin Marinas static int __init arm64_device_init(void) 288de79a64dSCatalin Marinas { 289de79a64dSCatalin Marinas of_clk_init(NULL); 290c560ecfeSCatalin Marinas of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 291de79a64dSCatalin Marinas return 0; 292de79a64dSCatalin Marinas } 293c560ecfeSCatalin Marinas arch_initcall(arm64_device_init); 294de79a64dSCatalin Marinas 2959703d9d7SCatalin Marinas static DEFINE_PER_CPU(struct cpu, cpu_data); 2969703d9d7SCatalin Marinas 2979703d9d7SCatalin Marinas static int __init topology_init(void) 2989703d9d7SCatalin Marinas { 2999703d9d7SCatalin Marinas int i; 3009703d9d7SCatalin Marinas 3019703d9d7SCatalin Marinas for_each_possible_cpu(i) { 3029703d9d7SCatalin Marinas struct cpu *cpu = &per_cpu(cpu_data, i); 3039703d9d7SCatalin Marinas cpu->hotpluggable = 1; 3049703d9d7SCatalin Marinas register_cpu(cpu, i); 3059703d9d7SCatalin Marinas } 3069703d9d7SCatalin Marinas 3079703d9d7SCatalin Marinas return 0; 3089703d9d7SCatalin Marinas } 3099703d9d7SCatalin Marinas subsys_initcall(topology_init); 3109703d9d7SCatalin Marinas 3119703d9d7SCatalin Marinas static const char *hwcap_str[] = { 3129703d9d7SCatalin Marinas "fp", 3139703d9d7SCatalin Marinas "asimd", 31446efe547SSudeep KarkadaNagesha "evtstrm", 3154bff28ccSSteve Capper "aes", 3164bff28ccSSteve Capper "pmull", 3174bff28ccSSteve Capper "sha1", 3184bff28ccSSteve Capper "sha2", 3194bff28ccSSteve Capper "crc32", 3209703d9d7SCatalin Marinas NULL 3219703d9d7SCatalin Marinas }; 3229703d9d7SCatalin Marinas 3239703d9d7SCatalin Marinas static int c_show(struct seq_file *m, void *v) 3249703d9d7SCatalin Marinas { 3259703d9d7SCatalin Marinas int i; 3269703d9d7SCatalin Marinas 3279703d9d7SCatalin Marinas seq_printf(m, "Processor\t: %s rev %d (%s)\n", 3289703d9d7SCatalin Marinas cpu_name, read_cpuid_id() & 15, ELF_PLATFORM); 3299703d9d7SCatalin Marinas 3309703d9d7SCatalin Marinas for_each_online_cpu(i) { 3319703d9d7SCatalin Marinas /* 3329703d9d7SCatalin Marinas * glibc reads /proc/cpuinfo to determine the number of 3339703d9d7SCatalin Marinas * online processors, looking for lines beginning with 3349703d9d7SCatalin Marinas * "processor". Give glibc what it expects. 3359703d9d7SCatalin Marinas */ 3369703d9d7SCatalin Marinas #ifdef CONFIG_SMP 3379703d9d7SCatalin Marinas seq_printf(m, "processor\t: %d\n", i); 3389703d9d7SCatalin Marinas #endif 3399703d9d7SCatalin Marinas } 3409703d9d7SCatalin Marinas 3419703d9d7SCatalin Marinas /* dump out the processor features */ 3429703d9d7SCatalin Marinas seq_puts(m, "Features\t: "); 3439703d9d7SCatalin Marinas 3449703d9d7SCatalin Marinas for (i = 0; hwcap_str[i]; i++) 3459703d9d7SCatalin Marinas if (elf_hwcap & (1 << i)) 3469703d9d7SCatalin Marinas seq_printf(m, "%s ", hwcap_str[i]); 3479703d9d7SCatalin Marinas 3489703d9d7SCatalin Marinas seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24); 3499703d9d7SCatalin Marinas seq_printf(m, "CPU architecture: AArch64\n"); 3509703d9d7SCatalin Marinas seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15); 3519703d9d7SCatalin Marinas seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff); 3529703d9d7SCatalin Marinas seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15); 3539703d9d7SCatalin Marinas 3549703d9d7SCatalin Marinas seq_puts(m, "\n"); 3559703d9d7SCatalin Marinas 3569703d9d7SCatalin Marinas seq_printf(m, "Hardware\t: %s\n", machine_name); 3579703d9d7SCatalin Marinas 3589703d9d7SCatalin Marinas return 0; 3599703d9d7SCatalin Marinas } 3609703d9d7SCatalin Marinas 3619703d9d7SCatalin Marinas static void *c_start(struct seq_file *m, loff_t *pos) 3629703d9d7SCatalin Marinas { 3639703d9d7SCatalin Marinas return *pos < 1 ? (void *)1 : NULL; 3649703d9d7SCatalin Marinas } 3659703d9d7SCatalin Marinas 3669703d9d7SCatalin Marinas static void *c_next(struct seq_file *m, void *v, loff_t *pos) 3679703d9d7SCatalin Marinas { 3689703d9d7SCatalin Marinas ++*pos; 3699703d9d7SCatalin Marinas return NULL; 3709703d9d7SCatalin Marinas } 3719703d9d7SCatalin Marinas 3729703d9d7SCatalin Marinas static void c_stop(struct seq_file *m, void *v) 3739703d9d7SCatalin Marinas { 3749703d9d7SCatalin Marinas } 3759703d9d7SCatalin Marinas 3769703d9d7SCatalin Marinas const struct seq_operations cpuinfo_op = { 3779703d9d7SCatalin Marinas .start = c_start, 3789703d9d7SCatalin Marinas .next = c_next, 3799703d9d7SCatalin Marinas .stop = c_stop, 3809703d9d7SCatalin Marinas .show = c_show 3819703d9d7SCatalin Marinas }; 382