1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/ptrace.c 4 * 5 * By Ross Biro 1/23/92 6 * edited by Linus Torvalds 7 * ARM modifications Copyright (C) 2000 Russell King 8 * Copyright (C) 2012 ARM Ltd. 9 */ 10 11 #include <linux/audit.h> 12 #include <linux/compat.h> 13 #include <linux/kernel.h> 14 #include <linux/sched/signal.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/mm.h> 17 #include <linux/nospec.h> 18 #include <linux/smp.h> 19 #include <linux/ptrace.h> 20 #include <linux/user.h> 21 #include <linux/seccomp.h> 22 #include <linux/security.h> 23 #include <linux/init.h> 24 #include <linux/signal.h> 25 #include <linux/string.h> 26 #include <linux/uaccess.h> 27 #include <linux/perf_event.h> 28 #include <linux/hw_breakpoint.h> 29 #include <linux/regset.h> 30 #include <linux/elf.h> 31 32 #include <asm/compat.h> 33 #include <asm/cpufeature.h> 34 #include <asm/debug-monitors.h> 35 #include <asm/fpsimd.h> 36 #include <asm/mte.h> 37 #include <asm/pointer_auth.h> 38 #include <asm/stacktrace.h> 39 #include <asm/syscall.h> 40 #include <asm/traps.h> 41 #include <asm/system_misc.h> 42 43 #define CREATE_TRACE_POINTS 44 #include <trace/events/syscalls.h> 45 46 struct pt_regs_offset { 47 const char *name; 48 int offset; 49 }; 50 51 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 52 #define REG_OFFSET_END {.name = NULL, .offset = 0} 53 #define GPR_OFFSET_NAME(r) \ 54 {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])} 55 56 static const struct pt_regs_offset regoffset_table[] = { 57 GPR_OFFSET_NAME(0), 58 GPR_OFFSET_NAME(1), 59 GPR_OFFSET_NAME(2), 60 GPR_OFFSET_NAME(3), 61 GPR_OFFSET_NAME(4), 62 GPR_OFFSET_NAME(5), 63 GPR_OFFSET_NAME(6), 64 GPR_OFFSET_NAME(7), 65 GPR_OFFSET_NAME(8), 66 GPR_OFFSET_NAME(9), 67 GPR_OFFSET_NAME(10), 68 GPR_OFFSET_NAME(11), 69 GPR_OFFSET_NAME(12), 70 GPR_OFFSET_NAME(13), 71 GPR_OFFSET_NAME(14), 72 GPR_OFFSET_NAME(15), 73 GPR_OFFSET_NAME(16), 74 GPR_OFFSET_NAME(17), 75 GPR_OFFSET_NAME(18), 76 GPR_OFFSET_NAME(19), 77 GPR_OFFSET_NAME(20), 78 GPR_OFFSET_NAME(21), 79 GPR_OFFSET_NAME(22), 80 GPR_OFFSET_NAME(23), 81 GPR_OFFSET_NAME(24), 82 GPR_OFFSET_NAME(25), 83 GPR_OFFSET_NAME(26), 84 GPR_OFFSET_NAME(27), 85 GPR_OFFSET_NAME(28), 86 GPR_OFFSET_NAME(29), 87 GPR_OFFSET_NAME(30), 88 {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])}, 89 REG_OFFSET_NAME(sp), 90 REG_OFFSET_NAME(pc), 91 REG_OFFSET_NAME(pstate), 92 REG_OFFSET_END, 93 }; 94 95 /** 96 * regs_query_register_offset() - query register offset from its name 97 * @name: the name of a register 98 * 99 * regs_query_register_offset() returns the offset of a register in struct 100 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 101 */ 102 int regs_query_register_offset(const char *name) 103 { 104 const struct pt_regs_offset *roff; 105 106 for (roff = regoffset_table; roff->name != NULL; roff++) 107 if (!strcmp(roff->name, name)) 108 return roff->offset; 109 return -EINVAL; 110 } 111 112 /** 113 * regs_within_kernel_stack() - check the address in the stack 114 * @regs: pt_regs which contains kernel stack pointer. 115 * @addr: address which is checked. 116 * 117 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 118 * If @addr is within the kernel stack, it returns true. If not, returns false. 119 */ 120 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) 121 { 122 return ((addr & ~(THREAD_SIZE - 1)) == 123 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))) || 124 on_irq_stack(addr, sizeof(unsigned long)); 125 } 126 127 /** 128 * regs_get_kernel_stack_nth() - get Nth entry of the stack 129 * @regs: pt_regs which contains kernel stack pointer. 130 * @n: stack entry number. 131 * 132 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 133 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 134 * this returns 0. 135 */ 136 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) 137 { 138 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 139 140 addr += n; 141 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 142 return *addr; 143 else 144 return 0; 145 } 146 147 /* 148 * TODO: does not yet catch signals sent when the child dies. 149 * in exit.c or in signal.c. 150 */ 151 152 /* 153 * Called by kernel/ptrace.c when detaching.. 154 */ 155 void ptrace_disable(struct task_struct *child) 156 { 157 /* 158 * This would be better off in core code, but PTRACE_DETACH has 159 * grown its fair share of arch-specific worts and changing it 160 * is likely to cause regressions on obscure architectures. 161 */ 162 user_disable_single_step(child); 163 } 164 165 #ifdef CONFIG_HAVE_HW_BREAKPOINT 166 /* 167 * Handle hitting a HW-breakpoint. 168 */ 169 static void ptrace_hbptriggered(struct perf_event *bp, 170 struct perf_sample_data *data, 171 struct pt_regs *regs) 172 { 173 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); 174 const char *desc = "Hardware breakpoint trap (ptrace)"; 175 176 #ifdef CONFIG_COMPAT 177 if (is_compat_task()) { 178 int si_errno = 0; 179 int i; 180 181 for (i = 0; i < ARM_MAX_BRP; ++i) { 182 if (current->thread.debug.hbp_break[i] == bp) { 183 si_errno = (i << 1) + 1; 184 break; 185 } 186 } 187 188 for (i = 0; i < ARM_MAX_WRP; ++i) { 189 if (current->thread.debug.hbp_watch[i] == bp) { 190 si_errno = -((i << 1) + 1); 191 break; 192 } 193 } 194 arm64_force_sig_ptrace_errno_trap(si_errno, bkpt->trigger, 195 desc); 196 return; 197 } 198 #endif 199 arm64_force_sig_fault(SIGTRAP, TRAP_HWBKPT, bkpt->trigger, desc); 200 } 201 202 /* 203 * Unregister breakpoints from this task and reset the pointers in 204 * the thread_struct. 205 */ 206 void flush_ptrace_hw_breakpoint(struct task_struct *tsk) 207 { 208 int i; 209 struct thread_struct *t = &tsk->thread; 210 211 for (i = 0; i < ARM_MAX_BRP; i++) { 212 if (t->debug.hbp_break[i]) { 213 unregister_hw_breakpoint(t->debug.hbp_break[i]); 214 t->debug.hbp_break[i] = NULL; 215 } 216 } 217 218 for (i = 0; i < ARM_MAX_WRP; i++) { 219 if (t->debug.hbp_watch[i]) { 220 unregister_hw_breakpoint(t->debug.hbp_watch[i]); 221 t->debug.hbp_watch[i] = NULL; 222 } 223 } 224 } 225 226 void ptrace_hw_copy_thread(struct task_struct *tsk) 227 { 228 memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); 229 } 230 231 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type, 232 struct task_struct *tsk, 233 unsigned long idx) 234 { 235 struct perf_event *bp = ERR_PTR(-EINVAL); 236 237 switch (note_type) { 238 case NT_ARM_HW_BREAK: 239 if (idx >= ARM_MAX_BRP) 240 goto out; 241 idx = array_index_nospec(idx, ARM_MAX_BRP); 242 bp = tsk->thread.debug.hbp_break[idx]; 243 break; 244 case NT_ARM_HW_WATCH: 245 if (idx >= ARM_MAX_WRP) 246 goto out; 247 idx = array_index_nospec(idx, ARM_MAX_WRP); 248 bp = tsk->thread.debug.hbp_watch[idx]; 249 break; 250 } 251 252 out: 253 return bp; 254 } 255 256 static int ptrace_hbp_set_event(unsigned int note_type, 257 struct task_struct *tsk, 258 unsigned long idx, 259 struct perf_event *bp) 260 { 261 int err = -EINVAL; 262 263 switch (note_type) { 264 case NT_ARM_HW_BREAK: 265 if (idx >= ARM_MAX_BRP) 266 goto out; 267 idx = array_index_nospec(idx, ARM_MAX_BRP); 268 tsk->thread.debug.hbp_break[idx] = bp; 269 err = 0; 270 break; 271 case NT_ARM_HW_WATCH: 272 if (idx >= ARM_MAX_WRP) 273 goto out; 274 idx = array_index_nospec(idx, ARM_MAX_WRP); 275 tsk->thread.debug.hbp_watch[idx] = bp; 276 err = 0; 277 break; 278 } 279 280 out: 281 return err; 282 } 283 284 static struct perf_event *ptrace_hbp_create(unsigned int note_type, 285 struct task_struct *tsk, 286 unsigned long idx) 287 { 288 struct perf_event *bp; 289 struct perf_event_attr attr; 290 int err, type; 291 292 switch (note_type) { 293 case NT_ARM_HW_BREAK: 294 type = HW_BREAKPOINT_X; 295 break; 296 case NT_ARM_HW_WATCH: 297 type = HW_BREAKPOINT_RW; 298 break; 299 default: 300 return ERR_PTR(-EINVAL); 301 } 302 303 ptrace_breakpoint_init(&attr); 304 305 /* 306 * Initialise fields to sane defaults 307 * (i.e. values that will pass validation). 308 */ 309 attr.bp_addr = 0; 310 attr.bp_len = HW_BREAKPOINT_LEN_4; 311 attr.bp_type = type; 312 attr.disabled = 1; 313 314 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); 315 if (IS_ERR(bp)) 316 return bp; 317 318 err = ptrace_hbp_set_event(note_type, tsk, idx, bp); 319 if (err) 320 return ERR_PTR(err); 321 322 return bp; 323 } 324 325 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, 326 struct arch_hw_breakpoint_ctrl ctrl, 327 struct perf_event_attr *attr) 328 { 329 int err, len, type, offset, disabled = !ctrl.enabled; 330 331 attr->disabled = disabled; 332 if (disabled) 333 return 0; 334 335 err = arch_bp_generic_fields(ctrl, &len, &type, &offset); 336 if (err) 337 return err; 338 339 switch (note_type) { 340 case NT_ARM_HW_BREAK: 341 if ((type & HW_BREAKPOINT_X) != type) 342 return -EINVAL; 343 break; 344 case NT_ARM_HW_WATCH: 345 if ((type & HW_BREAKPOINT_RW) != type) 346 return -EINVAL; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 attr->bp_len = len; 353 attr->bp_type = type; 354 attr->bp_addr += offset; 355 356 return 0; 357 } 358 359 static int ptrace_hbp_get_resource_info(unsigned int note_type, u32 *info) 360 { 361 u8 num; 362 u32 reg = 0; 363 364 switch (note_type) { 365 case NT_ARM_HW_BREAK: 366 num = hw_breakpoint_slots(TYPE_INST); 367 break; 368 case NT_ARM_HW_WATCH: 369 num = hw_breakpoint_slots(TYPE_DATA); 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 reg |= debug_monitors_arch(); 376 reg <<= 8; 377 reg |= num; 378 379 *info = reg; 380 return 0; 381 } 382 383 static int ptrace_hbp_get_ctrl(unsigned int note_type, 384 struct task_struct *tsk, 385 unsigned long idx, 386 u32 *ctrl) 387 { 388 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 389 390 if (IS_ERR(bp)) 391 return PTR_ERR(bp); 392 393 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0; 394 return 0; 395 } 396 397 static int ptrace_hbp_get_addr(unsigned int note_type, 398 struct task_struct *tsk, 399 unsigned long idx, 400 u64 *addr) 401 { 402 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 403 404 if (IS_ERR(bp)) 405 return PTR_ERR(bp); 406 407 *addr = bp ? counter_arch_bp(bp)->address : 0; 408 return 0; 409 } 410 411 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type, 412 struct task_struct *tsk, 413 unsigned long idx) 414 { 415 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 416 417 if (!bp) 418 bp = ptrace_hbp_create(note_type, tsk, idx); 419 420 return bp; 421 } 422 423 static int ptrace_hbp_set_ctrl(unsigned int note_type, 424 struct task_struct *tsk, 425 unsigned long idx, 426 u32 uctrl) 427 { 428 int err; 429 struct perf_event *bp; 430 struct perf_event_attr attr; 431 struct arch_hw_breakpoint_ctrl ctrl; 432 433 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 434 if (IS_ERR(bp)) { 435 err = PTR_ERR(bp); 436 return err; 437 } 438 439 attr = bp->attr; 440 decode_ctrl_reg(uctrl, &ctrl); 441 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr); 442 if (err) 443 return err; 444 445 return modify_user_hw_breakpoint(bp, &attr); 446 } 447 448 static int ptrace_hbp_set_addr(unsigned int note_type, 449 struct task_struct *tsk, 450 unsigned long idx, 451 u64 addr) 452 { 453 int err; 454 struct perf_event *bp; 455 struct perf_event_attr attr; 456 457 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 458 if (IS_ERR(bp)) { 459 err = PTR_ERR(bp); 460 return err; 461 } 462 463 attr = bp->attr; 464 attr.bp_addr = addr; 465 err = modify_user_hw_breakpoint(bp, &attr); 466 return err; 467 } 468 469 #define PTRACE_HBP_ADDR_SZ sizeof(u64) 470 #define PTRACE_HBP_CTRL_SZ sizeof(u32) 471 #define PTRACE_HBP_PAD_SZ sizeof(u32) 472 473 static int hw_break_get(struct task_struct *target, 474 const struct user_regset *regset, 475 struct membuf to) 476 { 477 unsigned int note_type = regset->core_note_type; 478 int ret, idx = 0; 479 u32 info, ctrl; 480 u64 addr; 481 482 /* Resource info */ 483 ret = ptrace_hbp_get_resource_info(note_type, &info); 484 if (ret) 485 return ret; 486 487 membuf_write(&to, &info, sizeof(info)); 488 membuf_zero(&to, sizeof(u32)); 489 /* (address, ctrl) registers */ 490 while (to.left) { 491 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr); 492 if (ret) 493 return ret; 494 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl); 495 if (ret) 496 return ret; 497 membuf_store(&to, addr); 498 membuf_store(&to, ctrl); 499 membuf_zero(&to, sizeof(u32)); 500 idx++; 501 } 502 return 0; 503 } 504 505 static int hw_break_set(struct task_struct *target, 506 const struct user_regset *regset, 507 unsigned int pos, unsigned int count, 508 const void *kbuf, const void __user *ubuf) 509 { 510 unsigned int note_type = regset->core_note_type; 511 int ret, idx = 0, offset, limit; 512 u32 ctrl; 513 u64 addr; 514 515 /* Resource info and pad */ 516 offset = offsetof(struct user_hwdebug_state, dbg_regs); 517 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset); 518 if (ret) 519 return ret; 520 521 /* (address, ctrl) registers */ 522 limit = regset->n * regset->size; 523 while (count && offset < limit) { 524 if (count < PTRACE_HBP_ADDR_SZ) 525 return -EINVAL; 526 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr, 527 offset, offset + PTRACE_HBP_ADDR_SZ); 528 if (ret) 529 return ret; 530 ret = ptrace_hbp_set_addr(note_type, target, idx, addr); 531 if (ret) 532 return ret; 533 offset += PTRACE_HBP_ADDR_SZ; 534 535 if (!count) 536 break; 537 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 538 offset, offset + PTRACE_HBP_CTRL_SZ); 539 if (ret) 540 return ret; 541 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl); 542 if (ret) 543 return ret; 544 offset += PTRACE_HBP_CTRL_SZ; 545 546 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 547 offset, 548 offset + PTRACE_HBP_PAD_SZ); 549 if (ret) 550 return ret; 551 offset += PTRACE_HBP_PAD_SZ; 552 idx++; 553 } 554 555 return 0; 556 } 557 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 558 559 static int gpr_get(struct task_struct *target, 560 const struct user_regset *regset, 561 struct membuf to) 562 { 563 struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs; 564 return membuf_write(&to, uregs, sizeof(*uregs)); 565 } 566 567 static int gpr_set(struct task_struct *target, const struct user_regset *regset, 568 unsigned int pos, unsigned int count, 569 const void *kbuf, const void __user *ubuf) 570 { 571 int ret; 572 struct user_pt_regs newregs = task_pt_regs(target)->user_regs; 573 574 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1); 575 if (ret) 576 return ret; 577 578 if (!valid_user_regs(&newregs, target)) 579 return -EINVAL; 580 581 task_pt_regs(target)->user_regs = newregs; 582 return 0; 583 } 584 585 static int fpr_active(struct task_struct *target, const struct user_regset *regset) 586 { 587 if (!system_supports_fpsimd()) 588 return -ENODEV; 589 return regset->n; 590 } 591 592 /* 593 * TODO: update fp accessors for lazy context switching (sync/flush hwstate) 594 */ 595 static int __fpr_get(struct task_struct *target, 596 const struct user_regset *regset, 597 struct membuf to) 598 { 599 struct user_fpsimd_state *uregs; 600 601 sve_sync_to_fpsimd(target); 602 603 uregs = &target->thread.uw.fpsimd_state; 604 605 return membuf_write(&to, uregs, sizeof(*uregs)); 606 } 607 608 static int fpr_get(struct task_struct *target, const struct user_regset *regset, 609 struct membuf to) 610 { 611 if (!system_supports_fpsimd()) 612 return -EINVAL; 613 614 if (target == current) 615 fpsimd_preserve_current_state(); 616 617 return __fpr_get(target, regset, to); 618 } 619 620 static int __fpr_set(struct task_struct *target, 621 const struct user_regset *regset, 622 unsigned int pos, unsigned int count, 623 const void *kbuf, const void __user *ubuf, 624 unsigned int start_pos) 625 { 626 int ret; 627 struct user_fpsimd_state newstate; 628 629 /* 630 * Ensure target->thread.uw.fpsimd_state is up to date, so that a 631 * short copyin can't resurrect stale data. 632 */ 633 sve_sync_to_fpsimd(target); 634 635 newstate = target->thread.uw.fpsimd_state; 636 637 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 638 start_pos, start_pos + sizeof(newstate)); 639 if (ret) 640 return ret; 641 642 target->thread.uw.fpsimd_state = newstate; 643 644 return ret; 645 } 646 647 static int fpr_set(struct task_struct *target, const struct user_regset *regset, 648 unsigned int pos, unsigned int count, 649 const void *kbuf, const void __user *ubuf) 650 { 651 int ret; 652 653 if (!system_supports_fpsimd()) 654 return -EINVAL; 655 656 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0); 657 if (ret) 658 return ret; 659 660 sve_sync_from_fpsimd_zeropad(target); 661 fpsimd_flush_task_state(target); 662 663 return ret; 664 } 665 666 static int tls_get(struct task_struct *target, const struct user_regset *regset, 667 struct membuf to) 668 { 669 int ret; 670 671 if (target == current) 672 tls_preserve_current_state(); 673 674 ret = membuf_store(&to, target->thread.uw.tp_value); 675 if (system_supports_tpidr2()) 676 ret = membuf_store(&to, target->thread.tpidr2_el0); 677 else 678 ret = membuf_zero(&to, sizeof(u64)); 679 680 return ret; 681 } 682 683 static int tls_set(struct task_struct *target, const struct user_regset *regset, 684 unsigned int pos, unsigned int count, 685 const void *kbuf, const void __user *ubuf) 686 { 687 int ret; 688 unsigned long tls[2]; 689 690 tls[0] = target->thread.uw.tp_value; 691 if (system_supports_sme()) 692 tls[1] = target->thread.tpidr2_el0; 693 694 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, tls, 0, count); 695 if (ret) 696 return ret; 697 698 target->thread.uw.tp_value = tls[0]; 699 if (system_supports_sme()) 700 target->thread.tpidr2_el0 = tls[1]; 701 702 return ret; 703 } 704 705 static int system_call_get(struct task_struct *target, 706 const struct user_regset *regset, 707 struct membuf to) 708 { 709 return membuf_store(&to, task_pt_regs(target)->syscallno); 710 } 711 712 static int system_call_set(struct task_struct *target, 713 const struct user_regset *regset, 714 unsigned int pos, unsigned int count, 715 const void *kbuf, const void __user *ubuf) 716 { 717 int syscallno = task_pt_regs(target)->syscallno; 718 int ret; 719 720 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1); 721 if (ret) 722 return ret; 723 724 task_pt_regs(target)->syscallno = syscallno; 725 return ret; 726 } 727 728 #ifdef CONFIG_ARM64_SVE 729 730 static void sve_init_header_from_task(struct user_sve_header *header, 731 struct task_struct *target, 732 enum vec_type type) 733 { 734 unsigned int vq; 735 bool active; 736 bool fpsimd_only; 737 enum vec_type task_type; 738 739 memset(header, 0, sizeof(*header)); 740 741 /* Check if the requested registers are active for the task */ 742 if (thread_sm_enabled(&target->thread)) 743 task_type = ARM64_VEC_SME; 744 else 745 task_type = ARM64_VEC_SVE; 746 active = (task_type == type); 747 748 switch (type) { 749 case ARM64_VEC_SVE: 750 if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT)) 751 header->flags |= SVE_PT_VL_INHERIT; 752 fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE); 753 break; 754 case ARM64_VEC_SME: 755 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 756 header->flags |= SVE_PT_VL_INHERIT; 757 fpsimd_only = false; 758 break; 759 default: 760 WARN_ON_ONCE(1); 761 return; 762 } 763 764 if (active) { 765 if (fpsimd_only) { 766 header->flags |= SVE_PT_REGS_FPSIMD; 767 } else { 768 header->flags |= SVE_PT_REGS_SVE; 769 } 770 } 771 772 header->vl = task_get_vl(target, type); 773 vq = sve_vq_from_vl(header->vl); 774 775 header->max_vl = vec_max_vl(type); 776 header->size = SVE_PT_SIZE(vq, header->flags); 777 header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl), 778 SVE_PT_REGS_SVE); 779 } 780 781 static unsigned int sve_size_from_header(struct user_sve_header const *header) 782 { 783 return ALIGN(header->size, SVE_VQ_BYTES); 784 } 785 786 static int sve_get_common(struct task_struct *target, 787 const struct user_regset *regset, 788 struct membuf to, 789 enum vec_type type) 790 { 791 struct user_sve_header header; 792 unsigned int vq; 793 unsigned long start, end; 794 795 /* Header */ 796 sve_init_header_from_task(&header, target, type); 797 vq = sve_vq_from_vl(header.vl); 798 799 membuf_write(&to, &header, sizeof(header)); 800 801 if (target == current) 802 fpsimd_preserve_current_state(); 803 804 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 805 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 806 807 switch ((header.flags & SVE_PT_REGS_MASK)) { 808 case SVE_PT_REGS_FPSIMD: 809 return __fpr_get(target, regset, to); 810 811 case SVE_PT_REGS_SVE: 812 start = SVE_PT_SVE_OFFSET; 813 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 814 membuf_write(&to, target->thread.sve_state, end - start); 815 816 start = end; 817 end = SVE_PT_SVE_FPSR_OFFSET(vq); 818 membuf_zero(&to, end - start); 819 820 /* 821 * Copy fpsr, and fpcr which must follow contiguously in 822 * struct fpsimd_state: 823 */ 824 start = end; 825 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 826 membuf_write(&to, &target->thread.uw.fpsimd_state.fpsr, 827 end - start); 828 829 start = end; 830 end = sve_size_from_header(&header); 831 return membuf_zero(&to, end - start); 832 833 default: 834 return 0; 835 } 836 } 837 838 static int sve_get(struct task_struct *target, 839 const struct user_regset *regset, 840 struct membuf to) 841 { 842 if (!system_supports_sve()) 843 return -EINVAL; 844 845 return sve_get_common(target, regset, to, ARM64_VEC_SVE); 846 } 847 848 static int sve_set_common(struct task_struct *target, 849 const struct user_regset *regset, 850 unsigned int pos, unsigned int count, 851 const void *kbuf, const void __user *ubuf, 852 enum vec_type type) 853 { 854 int ret; 855 struct user_sve_header header; 856 unsigned int vq; 857 unsigned long start, end; 858 859 /* Header */ 860 if (count < sizeof(header)) 861 return -EINVAL; 862 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 863 0, sizeof(header)); 864 if (ret) 865 goto out; 866 867 /* 868 * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by 869 * vec_set_vector_length(), which will also validate them for us: 870 */ 871 ret = vec_set_vector_length(target, type, header.vl, 872 ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16); 873 if (ret) 874 goto out; 875 876 /* Actual VL set may be less than the user asked for: */ 877 vq = sve_vq_from_vl(task_get_vl(target, type)); 878 879 /* Enter/exit streaming mode */ 880 if (system_supports_sme()) { 881 u64 old_svcr = target->thread.svcr; 882 883 switch (type) { 884 case ARM64_VEC_SVE: 885 target->thread.svcr &= ~SVCR_SM_MASK; 886 break; 887 case ARM64_VEC_SME: 888 target->thread.svcr |= SVCR_SM_MASK; 889 break; 890 default: 891 WARN_ON_ONCE(1); 892 return -EINVAL; 893 } 894 895 /* 896 * If we switched then invalidate any existing SVE 897 * state and ensure there's storage. 898 */ 899 if (target->thread.svcr != old_svcr) 900 sve_alloc(target, true); 901 } 902 903 /* Registers: FPSIMD-only case */ 904 905 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 906 if ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) { 907 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 908 SVE_PT_FPSIMD_OFFSET); 909 clear_tsk_thread_flag(target, TIF_SVE); 910 if (type == ARM64_VEC_SME) 911 fpsimd_force_sync_to_sve(target); 912 goto out; 913 } 914 915 /* 916 * Otherwise: no registers or full SVE case. For backwards 917 * compatibility reasons we treat empty flags as SVE registers. 918 */ 919 920 /* 921 * If setting a different VL from the requested VL and there is 922 * register data, the data layout will be wrong: don't even 923 * try to set the registers in this case. 924 */ 925 if (count && vq != sve_vq_from_vl(header.vl)) { 926 ret = -EIO; 927 goto out; 928 } 929 930 sve_alloc(target, true); 931 if (!target->thread.sve_state) { 932 ret = -ENOMEM; 933 clear_tsk_thread_flag(target, TIF_SVE); 934 goto out; 935 } 936 937 /* 938 * Ensure target->thread.sve_state is up to date with target's 939 * FPSIMD regs, so that a short copyin leaves trailing 940 * registers unmodified. Always enable SVE even if going into 941 * streaming mode. 942 */ 943 fpsimd_sync_to_sve(target); 944 set_tsk_thread_flag(target, TIF_SVE); 945 946 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 947 start = SVE_PT_SVE_OFFSET; 948 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 949 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 950 target->thread.sve_state, 951 start, end); 952 if (ret) 953 goto out; 954 955 start = end; 956 end = SVE_PT_SVE_FPSR_OFFSET(vq); 957 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 958 start, end); 959 if (ret) 960 goto out; 961 962 /* 963 * Copy fpsr, and fpcr which must follow contiguously in 964 * struct fpsimd_state: 965 */ 966 start = end; 967 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 968 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 969 &target->thread.uw.fpsimd_state.fpsr, 970 start, end); 971 972 out: 973 fpsimd_flush_task_state(target); 974 return ret; 975 } 976 977 static int sve_set(struct task_struct *target, 978 const struct user_regset *regset, 979 unsigned int pos, unsigned int count, 980 const void *kbuf, const void __user *ubuf) 981 { 982 if (!system_supports_sve()) 983 return -EINVAL; 984 985 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 986 ARM64_VEC_SVE); 987 } 988 989 #endif /* CONFIG_ARM64_SVE */ 990 991 #ifdef CONFIG_ARM64_SME 992 993 static int ssve_get(struct task_struct *target, 994 const struct user_regset *regset, 995 struct membuf to) 996 { 997 if (!system_supports_sme()) 998 return -EINVAL; 999 1000 return sve_get_common(target, regset, to, ARM64_VEC_SME); 1001 } 1002 1003 static int ssve_set(struct task_struct *target, 1004 const struct user_regset *regset, 1005 unsigned int pos, unsigned int count, 1006 const void *kbuf, const void __user *ubuf) 1007 { 1008 if (!system_supports_sme()) 1009 return -EINVAL; 1010 1011 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 1012 ARM64_VEC_SME); 1013 } 1014 1015 static int za_get(struct task_struct *target, 1016 const struct user_regset *regset, 1017 struct membuf to) 1018 { 1019 struct user_za_header header; 1020 unsigned int vq; 1021 unsigned long start, end; 1022 1023 if (!system_supports_sme()) 1024 return -EINVAL; 1025 1026 /* Header */ 1027 memset(&header, 0, sizeof(header)); 1028 1029 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 1030 header.flags |= ZA_PT_VL_INHERIT; 1031 1032 header.vl = task_get_sme_vl(target); 1033 vq = sve_vq_from_vl(header.vl); 1034 header.max_vl = sme_max_vl(); 1035 header.max_size = ZA_PT_SIZE(vq); 1036 1037 /* If ZA is not active there is only the header */ 1038 if (thread_za_enabled(&target->thread)) 1039 header.size = ZA_PT_SIZE(vq); 1040 else 1041 header.size = ZA_PT_ZA_OFFSET; 1042 1043 membuf_write(&to, &header, sizeof(header)); 1044 1045 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1046 end = ZA_PT_ZA_OFFSET; 1047 1048 if (target == current) 1049 fpsimd_preserve_current_state(); 1050 1051 /* Any register data to include? */ 1052 if (thread_za_enabled(&target->thread)) { 1053 start = end; 1054 end = ZA_PT_SIZE(vq); 1055 membuf_write(&to, target->thread.za_state, end - start); 1056 } 1057 1058 /* Zero any trailing padding */ 1059 start = end; 1060 end = ALIGN(header.size, SVE_VQ_BYTES); 1061 return membuf_zero(&to, end - start); 1062 } 1063 1064 static int za_set(struct task_struct *target, 1065 const struct user_regset *regset, 1066 unsigned int pos, unsigned int count, 1067 const void *kbuf, const void __user *ubuf) 1068 { 1069 int ret; 1070 struct user_za_header header; 1071 unsigned int vq; 1072 unsigned long start, end; 1073 1074 if (!system_supports_sme()) 1075 return -EINVAL; 1076 1077 /* Header */ 1078 if (count < sizeof(header)) 1079 return -EINVAL; 1080 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 1081 0, sizeof(header)); 1082 if (ret) 1083 goto out; 1084 1085 /* 1086 * All current ZA_PT_* flags are consumed by 1087 * vec_set_vector_length(), which will also validate them for 1088 * us: 1089 */ 1090 ret = vec_set_vector_length(target, ARM64_VEC_SME, header.vl, 1091 ((unsigned long)header.flags) << 16); 1092 if (ret) 1093 goto out; 1094 1095 /* Actual VL set may be less than the user asked for: */ 1096 vq = sve_vq_from_vl(task_get_sme_vl(target)); 1097 1098 /* Ensure there is some SVE storage for streaming mode */ 1099 if (!target->thread.sve_state) { 1100 sve_alloc(target, false); 1101 if (!target->thread.sve_state) { 1102 ret = -ENOMEM; 1103 goto out; 1104 } 1105 } 1106 1107 /* Allocate/reinit ZA storage */ 1108 sme_alloc(target); 1109 if (!target->thread.za_state) { 1110 ret = -ENOMEM; 1111 goto out; 1112 } 1113 1114 /* If there is no data then disable ZA */ 1115 if (!count) { 1116 target->thread.svcr &= ~SVCR_ZA_MASK; 1117 goto out; 1118 } 1119 1120 /* 1121 * If setting a different VL from the requested VL and there is 1122 * register data, the data layout will be wrong: don't even 1123 * try to set the registers in this case. 1124 */ 1125 if (vq != sve_vq_from_vl(header.vl)) { 1126 ret = -EIO; 1127 goto out; 1128 } 1129 1130 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1131 start = ZA_PT_ZA_OFFSET; 1132 end = ZA_PT_SIZE(vq); 1133 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1134 target->thread.za_state, 1135 start, end); 1136 if (ret) 1137 goto out; 1138 1139 /* Mark ZA as active and let userspace use it */ 1140 set_tsk_thread_flag(target, TIF_SME); 1141 target->thread.svcr |= SVCR_ZA_MASK; 1142 1143 out: 1144 fpsimd_flush_task_state(target); 1145 return ret; 1146 } 1147 1148 #endif /* CONFIG_ARM64_SME */ 1149 1150 #ifdef CONFIG_ARM64_PTR_AUTH 1151 static int pac_mask_get(struct task_struct *target, 1152 const struct user_regset *regset, 1153 struct membuf to) 1154 { 1155 /* 1156 * The PAC bits can differ across data and instruction pointers 1157 * depending on TCR_EL1.TBID*, which we may make use of in future, so 1158 * we expose separate masks. 1159 */ 1160 unsigned long mask = ptrauth_user_pac_mask(); 1161 struct user_pac_mask uregs = { 1162 .data_mask = mask, 1163 .insn_mask = mask, 1164 }; 1165 1166 if (!system_supports_address_auth()) 1167 return -EINVAL; 1168 1169 return membuf_write(&to, &uregs, sizeof(uregs)); 1170 } 1171 1172 static int pac_enabled_keys_get(struct task_struct *target, 1173 const struct user_regset *regset, 1174 struct membuf to) 1175 { 1176 long enabled_keys = ptrauth_get_enabled_keys(target); 1177 1178 if (IS_ERR_VALUE(enabled_keys)) 1179 return enabled_keys; 1180 1181 return membuf_write(&to, &enabled_keys, sizeof(enabled_keys)); 1182 } 1183 1184 static int pac_enabled_keys_set(struct task_struct *target, 1185 const struct user_regset *regset, 1186 unsigned int pos, unsigned int count, 1187 const void *kbuf, const void __user *ubuf) 1188 { 1189 int ret; 1190 long enabled_keys = ptrauth_get_enabled_keys(target); 1191 1192 if (IS_ERR_VALUE(enabled_keys)) 1193 return enabled_keys; 1194 1195 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &enabled_keys, 0, 1196 sizeof(long)); 1197 if (ret) 1198 return ret; 1199 1200 return ptrauth_set_enabled_keys(target, PR_PAC_ENABLED_KEYS_MASK, 1201 enabled_keys); 1202 } 1203 1204 #ifdef CONFIG_CHECKPOINT_RESTORE 1205 static __uint128_t pac_key_to_user(const struct ptrauth_key *key) 1206 { 1207 return (__uint128_t)key->hi << 64 | key->lo; 1208 } 1209 1210 static struct ptrauth_key pac_key_from_user(__uint128_t ukey) 1211 { 1212 struct ptrauth_key key = { 1213 .lo = (unsigned long)ukey, 1214 .hi = (unsigned long)(ukey >> 64), 1215 }; 1216 1217 return key; 1218 } 1219 1220 static void pac_address_keys_to_user(struct user_pac_address_keys *ukeys, 1221 const struct ptrauth_keys_user *keys) 1222 { 1223 ukeys->apiakey = pac_key_to_user(&keys->apia); 1224 ukeys->apibkey = pac_key_to_user(&keys->apib); 1225 ukeys->apdakey = pac_key_to_user(&keys->apda); 1226 ukeys->apdbkey = pac_key_to_user(&keys->apdb); 1227 } 1228 1229 static void pac_address_keys_from_user(struct ptrauth_keys_user *keys, 1230 const struct user_pac_address_keys *ukeys) 1231 { 1232 keys->apia = pac_key_from_user(ukeys->apiakey); 1233 keys->apib = pac_key_from_user(ukeys->apibkey); 1234 keys->apda = pac_key_from_user(ukeys->apdakey); 1235 keys->apdb = pac_key_from_user(ukeys->apdbkey); 1236 } 1237 1238 static int pac_address_keys_get(struct task_struct *target, 1239 const struct user_regset *regset, 1240 struct membuf to) 1241 { 1242 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1243 struct user_pac_address_keys user_keys; 1244 1245 if (!system_supports_address_auth()) 1246 return -EINVAL; 1247 1248 pac_address_keys_to_user(&user_keys, keys); 1249 1250 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1251 } 1252 1253 static int pac_address_keys_set(struct task_struct *target, 1254 const struct user_regset *regset, 1255 unsigned int pos, unsigned int count, 1256 const void *kbuf, const void __user *ubuf) 1257 { 1258 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1259 struct user_pac_address_keys user_keys; 1260 int ret; 1261 1262 if (!system_supports_address_auth()) 1263 return -EINVAL; 1264 1265 pac_address_keys_to_user(&user_keys, keys); 1266 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1267 &user_keys, 0, -1); 1268 if (ret) 1269 return ret; 1270 pac_address_keys_from_user(keys, &user_keys); 1271 1272 return 0; 1273 } 1274 1275 static void pac_generic_keys_to_user(struct user_pac_generic_keys *ukeys, 1276 const struct ptrauth_keys_user *keys) 1277 { 1278 ukeys->apgakey = pac_key_to_user(&keys->apga); 1279 } 1280 1281 static void pac_generic_keys_from_user(struct ptrauth_keys_user *keys, 1282 const struct user_pac_generic_keys *ukeys) 1283 { 1284 keys->apga = pac_key_from_user(ukeys->apgakey); 1285 } 1286 1287 static int pac_generic_keys_get(struct task_struct *target, 1288 const struct user_regset *regset, 1289 struct membuf to) 1290 { 1291 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1292 struct user_pac_generic_keys user_keys; 1293 1294 if (!system_supports_generic_auth()) 1295 return -EINVAL; 1296 1297 pac_generic_keys_to_user(&user_keys, keys); 1298 1299 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1300 } 1301 1302 static int pac_generic_keys_set(struct task_struct *target, 1303 const struct user_regset *regset, 1304 unsigned int pos, unsigned int count, 1305 const void *kbuf, const void __user *ubuf) 1306 { 1307 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1308 struct user_pac_generic_keys user_keys; 1309 int ret; 1310 1311 if (!system_supports_generic_auth()) 1312 return -EINVAL; 1313 1314 pac_generic_keys_to_user(&user_keys, keys); 1315 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1316 &user_keys, 0, -1); 1317 if (ret) 1318 return ret; 1319 pac_generic_keys_from_user(keys, &user_keys); 1320 1321 return 0; 1322 } 1323 #endif /* CONFIG_CHECKPOINT_RESTORE */ 1324 #endif /* CONFIG_ARM64_PTR_AUTH */ 1325 1326 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1327 static int tagged_addr_ctrl_get(struct task_struct *target, 1328 const struct user_regset *regset, 1329 struct membuf to) 1330 { 1331 long ctrl = get_tagged_addr_ctrl(target); 1332 1333 if (IS_ERR_VALUE(ctrl)) 1334 return ctrl; 1335 1336 return membuf_write(&to, &ctrl, sizeof(ctrl)); 1337 } 1338 1339 static int tagged_addr_ctrl_set(struct task_struct *target, const struct 1340 user_regset *regset, unsigned int pos, 1341 unsigned int count, const void *kbuf, const 1342 void __user *ubuf) 1343 { 1344 int ret; 1345 long ctrl; 1346 1347 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); 1348 if (ret) 1349 return ret; 1350 1351 return set_tagged_addr_ctrl(target, ctrl); 1352 } 1353 #endif 1354 1355 enum aarch64_regset { 1356 REGSET_GPR, 1357 REGSET_FPR, 1358 REGSET_TLS, 1359 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1360 REGSET_HW_BREAK, 1361 REGSET_HW_WATCH, 1362 #endif 1363 REGSET_SYSTEM_CALL, 1364 #ifdef CONFIG_ARM64_SVE 1365 REGSET_SVE, 1366 #endif 1367 #ifdef CONFIG_ARM64_SVE 1368 REGSET_SSVE, 1369 REGSET_ZA, 1370 #endif 1371 #ifdef CONFIG_ARM64_PTR_AUTH 1372 REGSET_PAC_MASK, 1373 REGSET_PAC_ENABLED_KEYS, 1374 #ifdef CONFIG_CHECKPOINT_RESTORE 1375 REGSET_PACA_KEYS, 1376 REGSET_PACG_KEYS, 1377 #endif 1378 #endif 1379 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1380 REGSET_TAGGED_ADDR_CTRL, 1381 #endif 1382 }; 1383 1384 static const struct user_regset aarch64_regsets[] = { 1385 [REGSET_GPR] = { 1386 .core_note_type = NT_PRSTATUS, 1387 .n = sizeof(struct user_pt_regs) / sizeof(u64), 1388 .size = sizeof(u64), 1389 .align = sizeof(u64), 1390 .regset_get = gpr_get, 1391 .set = gpr_set 1392 }, 1393 [REGSET_FPR] = { 1394 .core_note_type = NT_PRFPREG, 1395 .n = sizeof(struct user_fpsimd_state) / sizeof(u32), 1396 /* 1397 * We pretend we have 32-bit registers because the fpsr and 1398 * fpcr are 32-bits wide. 1399 */ 1400 .size = sizeof(u32), 1401 .align = sizeof(u32), 1402 .active = fpr_active, 1403 .regset_get = fpr_get, 1404 .set = fpr_set 1405 }, 1406 [REGSET_TLS] = { 1407 .core_note_type = NT_ARM_TLS, 1408 .n = 2, 1409 .size = sizeof(void *), 1410 .align = sizeof(void *), 1411 .regset_get = tls_get, 1412 .set = tls_set, 1413 }, 1414 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1415 [REGSET_HW_BREAK] = { 1416 .core_note_type = NT_ARM_HW_BREAK, 1417 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1418 .size = sizeof(u32), 1419 .align = sizeof(u32), 1420 .regset_get = hw_break_get, 1421 .set = hw_break_set, 1422 }, 1423 [REGSET_HW_WATCH] = { 1424 .core_note_type = NT_ARM_HW_WATCH, 1425 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1426 .size = sizeof(u32), 1427 .align = sizeof(u32), 1428 .regset_get = hw_break_get, 1429 .set = hw_break_set, 1430 }, 1431 #endif 1432 [REGSET_SYSTEM_CALL] = { 1433 .core_note_type = NT_ARM_SYSTEM_CALL, 1434 .n = 1, 1435 .size = sizeof(int), 1436 .align = sizeof(int), 1437 .regset_get = system_call_get, 1438 .set = system_call_set, 1439 }, 1440 #ifdef CONFIG_ARM64_SVE 1441 [REGSET_SVE] = { /* Scalable Vector Extension */ 1442 .core_note_type = NT_ARM_SVE, 1443 .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE), 1444 SVE_VQ_BYTES), 1445 .size = SVE_VQ_BYTES, 1446 .align = SVE_VQ_BYTES, 1447 .regset_get = sve_get, 1448 .set = sve_set, 1449 }, 1450 #endif 1451 #ifdef CONFIG_ARM64_SME 1452 [REGSET_SSVE] = { /* Streaming mode SVE */ 1453 .core_note_type = NT_ARM_SSVE, 1454 .n = DIV_ROUND_UP(SVE_PT_SIZE(SME_VQ_MAX, SVE_PT_REGS_SVE), 1455 SVE_VQ_BYTES), 1456 .size = SVE_VQ_BYTES, 1457 .align = SVE_VQ_BYTES, 1458 .regset_get = ssve_get, 1459 .set = ssve_set, 1460 }, 1461 [REGSET_ZA] = { /* SME ZA */ 1462 .core_note_type = NT_ARM_ZA, 1463 /* 1464 * ZA is a single register but it's variably sized and 1465 * the ptrace core requires that the size of any data 1466 * be an exact multiple of the configured register 1467 * size so report as though we had SVE_VQ_BYTES 1468 * registers. These values aren't exposed to 1469 * userspace. 1470 */ 1471 .n = DIV_ROUND_UP(ZA_PT_SIZE(SME_VQ_MAX), SVE_VQ_BYTES), 1472 .size = SVE_VQ_BYTES, 1473 .align = SVE_VQ_BYTES, 1474 .regset_get = za_get, 1475 .set = za_set, 1476 }, 1477 #endif 1478 #ifdef CONFIG_ARM64_PTR_AUTH 1479 [REGSET_PAC_MASK] = { 1480 .core_note_type = NT_ARM_PAC_MASK, 1481 .n = sizeof(struct user_pac_mask) / sizeof(u64), 1482 .size = sizeof(u64), 1483 .align = sizeof(u64), 1484 .regset_get = pac_mask_get, 1485 /* this cannot be set dynamically */ 1486 }, 1487 [REGSET_PAC_ENABLED_KEYS] = { 1488 .core_note_type = NT_ARM_PAC_ENABLED_KEYS, 1489 .n = 1, 1490 .size = sizeof(long), 1491 .align = sizeof(long), 1492 .regset_get = pac_enabled_keys_get, 1493 .set = pac_enabled_keys_set, 1494 }, 1495 #ifdef CONFIG_CHECKPOINT_RESTORE 1496 [REGSET_PACA_KEYS] = { 1497 .core_note_type = NT_ARM_PACA_KEYS, 1498 .n = sizeof(struct user_pac_address_keys) / sizeof(__uint128_t), 1499 .size = sizeof(__uint128_t), 1500 .align = sizeof(__uint128_t), 1501 .regset_get = pac_address_keys_get, 1502 .set = pac_address_keys_set, 1503 }, 1504 [REGSET_PACG_KEYS] = { 1505 .core_note_type = NT_ARM_PACG_KEYS, 1506 .n = sizeof(struct user_pac_generic_keys) / sizeof(__uint128_t), 1507 .size = sizeof(__uint128_t), 1508 .align = sizeof(__uint128_t), 1509 .regset_get = pac_generic_keys_get, 1510 .set = pac_generic_keys_set, 1511 }, 1512 #endif 1513 #endif 1514 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1515 [REGSET_TAGGED_ADDR_CTRL] = { 1516 .core_note_type = NT_ARM_TAGGED_ADDR_CTRL, 1517 .n = 1, 1518 .size = sizeof(long), 1519 .align = sizeof(long), 1520 .regset_get = tagged_addr_ctrl_get, 1521 .set = tagged_addr_ctrl_set, 1522 }, 1523 #endif 1524 }; 1525 1526 static const struct user_regset_view user_aarch64_view = { 1527 .name = "aarch64", .e_machine = EM_AARCH64, 1528 .regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets) 1529 }; 1530 1531 #ifdef CONFIG_COMPAT 1532 enum compat_regset { 1533 REGSET_COMPAT_GPR, 1534 REGSET_COMPAT_VFP, 1535 }; 1536 1537 static inline compat_ulong_t compat_get_user_reg(struct task_struct *task, int idx) 1538 { 1539 struct pt_regs *regs = task_pt_regs(task); 1540 1541 switch (idx) { 1542 case 15: 1543 return regs->pc; 1544 case 16: 1545 return pstate_to_compat_psr(regs->pstate); 1546 case 17: 1547 return regs->orig_x0; 1548 default: 1549 return regs->regs[idx]; 1550 } 1551 } 1552 1553 static int compat_gpr_get(struct task_struct *target, 1554 const struct user_regset *regset, 1555 struct membuf to) 1556 { 1557 int i = 0; 1558 1559 while (to.left) 1560 membuf_store(&to, compat_get_user_reg(target, i++)); 1561 return 0; 1562 } 1563 1564 static int compat_gpr_set(struct task_struct *target, 1565 const struct user_regset *regset, 1566 unsigned int pos, unsigned int count, 1567 const void *kbuf, const void __user *ubuf) 1568 { 1569 struct pt_regs newregs; 1570 int ret = 0; 1571 unsigned int i, start, num_regs; 1572 1573 /* Calculate the number of AArch32 registers contained in count */ 1574 num_regs = count / regset->size; 1575 1576 /* Convert pos into an register number */ 1577 start = pos / regset->size; 1578 1579 if (start + num_regs > regset->n) 1580 return -EIO; 1581 1582 newregs = *task_pt_regs(target); 1583 1584 for (i = 0; i < num_regs; ++i) { 1585 unsigned int idx = start + i; 1586 compat_ulong_t reg; 1587 1588 if (kbuf) { 1589 memcpy(®, kbuf, sizeof(reg)); 1590 kbuf += sizeof(reg); 1591 } else { 1592 ret = copy_from_user(®, ubuf, sizeof(reg)); 1593 if (ret) { 1594 ret = -EFAULT; 1595 break; 1596 } 1597 1598 ubuf += sizeof(reg); 1599 } 1600 1601 switch (idx) { 1602 case 15: 1603 newregs.pc = reg; 1604 break; 1605 case 16: 1606 reg = compat_psr_to_pstate(reg); 1607 newregs.pstate = reg; 1608 break; 1609 case 17: 1610 newregs.orig_x0 = reg; 1611 break; 1612 default: 1613 newregs.regs[idx] = reg; 1614 } 1615 1616 } 1617 1618 if (valid_user_regs(&newregs.user_regs, target)) 1619 *task_pt_regs(target) = newregs; 1620 else 1621 ret = -EINVAL; 1622 1623 return ret; 1624 } 1625 1626 static int compat_vfp_get(struct task_struct *target, 1627 const struct user_regset *regset, 1628 struct membuf to) 1629 { 1630 struct user_fpsimd_state *uregs; 1631 compat_ulong_t fpscr; 1632 1633 if (!system_supports_fpsimd()) 1634 return -EINVAL; 1635 1636 uregs = &target->thread.uw.fpsimd_state; 1637 1638 if (target == current) 1639 fpsimd_preserve_current_state(); 1640 1641 /* 1642 * The VFP registers are packed into the fpsimd_state, so they all sit 1643 * nicely together for us. We just need to create the fpscr separately. 1644 */ 1645 membuf_write(&to, uregs, VFP_STATE_SIZE - sizeof(compat_ulong_t)); 1646 fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) | 1647 (uregs->fpcr & VFP_FPSCR_CTRL_MASK); 1648 return membuf_store(&to, fpscr); 1649 } 1650 1651 static int compat_vfp_set(struct task_struct *target, 1652 const struct user_regset *regset, 1653 unsigned int pos, unsigned int count, 1654 const void *kbuf, const void __user *ubuf) 1655 { 1656 struct user_fpsimd_state *uregs; 1657 compat_ulong_t fpscr; 1658 int ret, vregs_end_pos; 1659 1660 if (!system_supports_fpsimd()) 1661 return -EINVAL; 1662 1663 uregs = &target->thread.uw.fpsimd_state; 1664 1665 vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t); 1666 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 1667 vregs_end_pos); 1668 1669 if (count && !ret) { 1670 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpscr, 1671 vregs_end_pos, VFP_STATE_SIZE); 1672 if (!ret) { 1673 uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK; 1674 uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK; 1675 } 1676 } 1677 1678 fpsimd_flush_task_state(target); 1679 return ret; 1680 } 1681 1682 static int compat_tls_get(struct task_struct *target, 1683 const struct user_regset *regset, 1684 struct membuf to) 1685 { 1686 return membuf_store(&to, (compat_ulong_t)target->thread.uw.tp_value); 1687 } 1688 1689 static int compat_tls_set(struct task_struct *target, 1690 const struct user_regset *regset, unsigned int pos, 1691 unsigned int count, const void *kbuf, 1692 const void __user *ubuf) 1693 { 1694 int ret; 1695 compat_ulong_t tls = target->thread.uw.tp_value; 1696 1697 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1); 1698 if (ret) 1699 return ret; 1700 1701 target->thread.uw.tp_value = tls; 1702 return ret; 1703 } 1704 1705 static const struct user_regset aarch32_regsets[] = { 1706 [REGSET_COMPAT_GPR] = { 1707 .core_note_type = NT_PRSTATUS, 1708 .n = COMPAT_ELF_NGREG, 1709 .size = sizeof(compat_elf_greg_t), 1710 .align = sizeof(compat_elf_greg_t), 1711 .regset_get = compat_gpr_get, 1712 .set = compat_gpr_set 1713 }, 1714 [REGSET_COMPAT_VFP] = { 1715 .core_note_type = NT_ARM_VFP, 1716 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1717 .size = sizeof(compat_ulong_t), 1718 .align = sizeof(compat_ulong_t), 1719 .active = fpr_active, 1720 .regset_get = compat_vfp_get, 1721 .set = compat_vfp_set 1722 }, 1723 }; 1724 1725 static const struct user_regset_view user_aarch32_view = { 1726 .name = "aarch32", .e_machine = EM_ARM, 1727 .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets) 1728 }; 1729 1730 static const struct user_regset aarch32_ptrace_regsets[] = { 1731 [REGSET_GPR] = { 1732 .core_note_type = NT_PRSTATUS, 1733 .n = COMPAT_ELF_NGREG, 1734 .size = sizeof(compat_elf_greg_t), 1735 .align = sizeof(compat_elf_greg_t), 1736 .regset_get = compat_gpr_get, 1737 .set = compat_gpr_set 1738 }, 1739 [REGSET_FPR] = { 1740 .core_note_type = NT_ARM_VFP, 1741 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1742 .size = sizeof(compat_ulong_t), 1743 .align = sizeof(compat_ulong_t), 1744 .regset_get = compat_vfp_get, 1745 .set = compat_vfp_set 1746 }, 1747 [REGSET_TLS] = { 1748 .core_note_type = NT_ARM_TLS, 1749 .n = 1, 1750 .size = sizeof(compat_ulong_t), 1751 .align = sizeof(compat_ulong_t), 1752 .regset_get = compat_tls_get, 1753 .set = compat_tls_set, 1754 }, 1755 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1756 [REGSET_HW_BREAK] = { 1757 .core_note_type = NT_ARM_HW_BREAK, 1758 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1759 .size = sizeof(u32), 1760 .align = sizeof(u32), 1761 .regset_get = hw_break_get, 1762 .set = hw_break_set, 1763 }, 1764 [REGSET_HW_WATCH] = { 1765 .core_note_type = NT_ARM_HW_WATCH, 1766 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1767 .size = sizeof(u32), 1768 .align = sizeof(u32), 1769 .regset_get = hw_break_get, 1770 .set = hw_break_set, 1771 }, 1772 #endif 1773 [REGSET_SYSTEM_CALL] = { 1774 .core_note_type = NT_ARM_SYSTEM_CALL, 1775 .n = 1, 1776 .size = sizeof(int), 1777 .align = sizeof(int), 1778 .regset_get = system_call_get, 1779 .set = system_call_set, 1780 }, 1781 }; 1782 1783 static const struct user_regset_view user_aarch32_ptrace_view = { 1784 .name = "aarch32", .e_machine = EM_ARM, 1785 .regsets = aarch32_ptrace_regsets, .n = ARRAY_SIZE(aarch32_ptrace_regsets) 1786 }; 1787 1788 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off, 1789 compat_ulong_t __user *ret) 1790 { 1791 compat_ulong_t tmp; 1792 1793 if (off & 3) 1794 return -EIO; 1795 1796 if (off == COMPAT_PT_TEXT_ADDR) 1797 tmp = tsk->mm->start_code; 1798 else if (off == COMPAT_PT_DATA_ADDR) 1799 tmp = tsk->mm->start_data; 1800 else if (off == COMPAT_PT_TEXT_END_ADDR) 1801 tmp = tsk->mm->end_code; 1802 else if (off < sizeof(compat_elf_gregset_t)) 1803 tmp = compat_get_user_reg(tsk, off >> 2); 1804 else if (off >= COMPAT_USER_SZ) 1805 return -EIO; 1806 else 1807 tmp = 0; 1808 1809 return put_user(tmp, ret); 1810 } 1811 1812 static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off, 1813 compat_ulong_t val) 1814 { 1815 struct pt_regs newregs = *task_pt_regs(tsk); 1816 unsigned int idx = off / 4; 1817 1818 if (off & 3 || off >= COMPAT_USER_SZ) 1819 return -EIO; 1820 1821 if (off >= sizeof(compat_elf_gregset_t)) 1822 return 0; 1823 1824 switch (idx) { 1825 case 15: 1826 newregs.pc = val; 1827 break; 1828 case 16: 1829 newregs.pstate = compat_psr_to_pstate(val); 1830 break; 1831 case 17: 1832 newregs.orig_x0 = val; 1833 break; 1834 default: 1835 newregs.regs[idx] = val; 1836 } 1837 1838 if (!valid_user_regs(&newregs.user_regs, tsk)) 1839 return -EINVAL; 1840 1841 *task_pt_regs(tsk) = newregs; 1842 return 0; 1843 } 1844 1845 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1846 1847 /* 1848 * Convert a virtual register number into an index for a thread_info 1849 * breakpoint array. Breakpoints are identified using positive numbers 1850 * whilst watchpoints are negative. The registers are laid out as pairs 1851 * of (address, control), each pair mapping to a unique hw_breakpoint struct. 1852 * Register 0 is reserved for describing resource information. 1853 */ 1854 static int compat_ptrace_hbp_num_to_idx(compat_long_t num) 1855 { 1856 return (abs(num) - 1) >> 1; 1857 } 1858 1859 static int compat_ptrace_hbp_get_resource_info(u32 *kdata) 1860 { 1861 u8 num_brps, num_wrps, debug_arch, wp_len; 1862 u32 reg = 0; 1863 1864 num_brps = hw_breakpoint_slots(TYPE_INST); 1865 num_wrps = hw_breakpoint_slots(TYPE_DATA); 1866 1867 debug_arch = debug_monitors_arch(); 1868 wp_len = 8; 1869 reg |= debug_arch; 1870 reg <<= 8; 1871 reg |= wp_len; 1872 reg <<= 8; 1873 reg |= num_wrps; 1874 reg <<= 8; 1875 reg |= num_brps; 1876 1877 *kdata = reg; 1878 return 0; 1879 } 1880 1881 static int compat_ptrace_hbp_get(unsigned int note_type, 1882 struct task_struct *tsk, 1883 compat_long_t num, 1884 u32 *kdata) 1885 { 1886 u64 addr = 0; 1887 u32 ctrl = 0; 1888 1889 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1890 1891 if (num & 1) { 1892 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr); 1893 *kdata = (u32)addr; 1894 } else { 1895 err = ptrace_hbp_get_ctrl(note_type, tsk, idx, &ctrl); 1896 *kdata = ctrl; 1897 } 1898 1899 return err; 1900 } 1901 1902 static int compat_ptrace_hbp_set(unsigned int note_type, 1903 struct task_struct *tsk, 1904 compat_long_t num, 1905 u32 *kdata) 1906 { 1907 u64 addr; 1908 u32 ctrl; 1909 1910 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1911 1912 if (num & 1) { 1913 addr = *kdata; 1914 err = ptrace_hbp_set_addr(note_type, tsk, idx, addr); 1915 } else { 1916 ctrl = *kdata; 1917 err = ptrace_hbp_set_ctrl(note_type, tsk, idx, ctrl); 1918 } 1919 1920 return err; 1921 } 1922 1923 static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num, 1924 compat_ulong_t __user *data) 1925 { 1926 int ret; 1927 u32 kdata; 1928 1929 /* Watchpoint */ 1930 if (num < 0) { 1931 ret = compat_ptrace_hbp_get(NT_ARM_HW_WATCH, tsk, num, &kdata); 1932 /* Resource info */ 1933 } else if (num == 0) { 1934 ret = compat_ptrace_hbp_get_resource_info(&kdata); 1935 /* Breakpoint */ 1936 } else { 1937 ret = compat_ptrace_hbp_get(NT_ARM_HW_BREAK, tsk, num, &kdata); 1938 } 1939 1940 if (!ret) 1941 ret = put_user(kdata, data); 1942 1943 return ret; 1944 } 1945 1946 static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num, 1947 compat_ulong_t __user *data) 1948 { 1949 int ret; 1950 u32 kdata = 0; 1951 1952 if (num == 0) 1953 return 0; 1954 1955 ret = get_user(kdata, data); 1956 if (ret) 1957 return ret; 1958 1959 if (num < 0) 1960 ret = compat_ptrace_hbp_set(NT_ARM_HW_WATCH, tsk, num, &kdata); 1961 else 1962 ret = compat_ptrace_hbp_set(NT_ARM_HW_BREAK, tsk, num, &kdata); 1963 1964 return ret; 1965 } 1966 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1967 1968 long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 1969 compat_ulong_t caddr, compat_ulong_t cdata) 1970 { 1971 unsigned long addr = caddr; 1972 unsigned long data = cdata; 1973 void __user *datap = compat_ptr(data); 1974 int ret; 1975 1976 switch (request) { 1977 case PTRACE_PEEKUSR: 1978 ret = compat_ptrace_read_user(child, addr, datap); 1979 break; 1980 1981 case PTRACE_POKEUSR: 1982 ret = compat_ptrace_write_user(child, addr, data); 1983 break; 1984 1985 case COMPAT_PTRACE_GETREGS: 1986 ret = copy_regset_to_user(child, 1987 &user_aarch32_view, 1988 REGSET_COMPAT_GPR, 1989 0, sizeof(compat_elf_gregset_t), 1990 datap); 1991 break; 1992 1993 case COMPAT_PTRACE_SETREGS: 1994 ret = copy_regset_from_user(child, 1995 &user_aarch32_view, 1996 REGSET_COMPAT_GPR, 1997 0, sizeof(compat_elf_gregset_t), 1998 datap); 1999 break; 2000 2001 case COMPAT_PTRACE_GET_THREAD_AREA: 2002 ret = put_user((compat_ulong_t)child->thread.uw.tp_value, 2003 (compat_ulong_t __user *)datap); 2004 break; 2005 2006 case COMPAT_PTRACE_SET_SYSCALL: 2007 task_pt_regs(child)->syscallno = data; 2008 ret = 0; 2009 break; 2010 2011 case COMPAT_PTRACE_GETVFPREGS: 2012 ret = copy_regset_to_user(child, 2013 &user_aarch32_view, 2014 REGSET_COMPAT_VFP, 2015 0, VFP_STATE_SIZE, 2016 datap); 2017 break; 2018 2019 case COMPAT_PTRACE_SETVFPREGS: 2020 ret = copy_regset_from_user(child, 2021 &user_aarch32_view, 2022 REGSET_COMPAT_VFP, 2023 0, VFP_STATE_SIZE, 2024 datap); 2025 break; 2026 2027 #ifdef CONFIG_HAVE_HW_BREAKPOINT 2028 case COMPAT_PTRACE_GETHBPREGS: 2029 ret = compat_ptrace_gethbpregs(child, addr, datap); 2030 break; 2031 2032 case COMPAT_PTRACE_SETHBPREGS: 2033 ret = compat_ptrace_sethbpregs(child, addr, datap); 2034 break; 2035 #endif 2036 2037 default: 2038 ret = compat_ptrace_request(child, request, addr, 2039 data); 2040 break; 2041 } 2042 2043 return ret; 2044 } 2045 #endif /* CONFIG_COMPAT */ 2046 2047 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 2048 { 2049 #ifdef CONFIG_COMPAT 2050 /* 2051 * Core dumping of 32-bit tasks or compat ptrace requests must use the 2052 * user_aarch32_view compatible with arm32. Native ptrace requests on 2053 * 32-bit children use an extended user_aarch32_ptrace_view to allow 2054 * access to the TLS register. 2055 */ 2056 if (is_compat_task()) 2057 return &user_aarch32_view; 2058 else if (is_compat_thread(task_thread_info(task))) 2059 return &user_aarch32_ptrace_view; 2060 #endif 2061 return &user_aarch64_view; 2062 } 2063 2064 long arch_ptrace(struct task_struct *child, long request, 2065 unsigned long addr, unsigned long data) 2066 { 2067 switch (request) { 2068 case PTRACE_PEEKMTETAGS: 2069 case PTRACE_POKEMTETAGS: 2070 return mte_ptrace_copy_tags(child, request, addr, data); 2071 } 2072 2073 return ptrace_request(child, request, addr, data); 2074 } 2075 2076 enum ptrace_syscall_dir { 2077 PTRACE_SYSCALL_ENTER = 0, 2078 PTRACE_SYSCALL_EXIT, 2079 }; 2080 2081 static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir) 2082 { 2083 int regno; 2084 unsigned long saved_reg; 2085 2086 /* 2087 * We have some ABI weirdness here in the way that we handle syscall 2088 * exit stops because we indicate whether or not the stop has been 2089 * signalled from syscall entry or syscall exit by clobbering a general 2090 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee 2091 * and restoring its old value after the stop. This means that: 2092 * 2093 * - Any writes by the tracer to this register during the stop are 2094 * ignored/discarded. 2095 * 2096 * - The actual value of the register is not available during the stop, 2097 * so the tracer cannot save it and restore it later. 2098 * 2099 * - Syscall stops behave differently to seccomp and pseudo-step traps 2100 * (the latter do not nobble any registers). 2101 */ 2102 regno = (is_compat_task() ? 12 : 7); 2103 saved_reg = regs->regs[regno]; 2104 regs->regs[regno] = dir; 2105 2106 if (dir == PTRACE_SYSCALL_ENTER) { 2107 if (ptrace_report_syscall_entry(regs)) 2108 forget_syscall(regs); 2109 regs->regs[regno] = saved_reg; 2110 } else if (!test_thread_flag(TIF_SINGLESTEP)) { 2111 ptrace_report_syscall_exit(regs, 0); 2112 regs->regs[regno] = saved_reg; 2113 } else { 2114 regs->regs[regno] = saved_reg; 2115 2116 /* 2117 * Signal a pseudo-step exception since we are stepping but 2118 * tracer modifications to the registers may have rewound the 2119 * state machine. 2120 */ 2121 ptrace_report_syscall_exit(regs, 1); 2122 } 2123 } 2124 2125 int syscall_trace_enter(struct pt_regs *regs) 2126 { 2127 unsigned long flags = read_thread_flags(); 2128 2129 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { 2130 report_syscall(regs, PTRACE_SYSCALL_ENTER); 2131 if (flags & _TIF_SYSCALL_EMU) 2132 return NO_SYSCALL; 2133 } 2134 2135 /* Do the secure computing after ptrace; failures should be fast. */ 2136 if (secure_computing() == -1) 2137 return NO_SYSCALL; 2138 2139 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) 2140 trace_sys_enter(regs, regs->syscallno); 2141 2142 audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1], 2143 regs->regs[2], regs->regs[3]); 2144 2145 return regs->syscallno; 2146 } 2147 2148 void syscall_trace_exit(struct pt_regs *regs) 2149 { 2150 unsigned long flags = read_thread_flags(); 2151 2152 audit_syscall_exit(regs); 2153 2154 if (flags & _TIF_SYSCALL_TRACEPOINT) 2155 trace_sys_exit(regs, syscall_get_return_value(current, regs)); 2156 2157 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) 2158 report_syscall(regs, PTRACE_SYSCALL_EXIT); 2159 2160 rseq_syscall(regs); 2161 } 2162 2163 /* 2164 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. 2165 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is 2166 * not described in ARM DDI 0487D.a. 2167 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may 2168 * be allocated an EL0 meaning in future. 2169 * Userspace cannot use these until they have an architectural meaning. 2170 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format. 2171 * We also reserve IL for the kernel; SS is handled dynamically. 2172 */ 2173 #define SPSR_EL1_AARCH64_RES0_BITS \ 2174 (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \ 2175 GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5)) 2176 #define SPSR_EL1_AARCH32_RES0_BITS \ 2177 (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) 2178 2179 static int valid_compat_regs(struct user_pt_regs *regs) 2180 { 2181 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; 2182 2183 if (!system_supports_mixed_endian_el0()) { 2184 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 2185 regs->pstate |= PSR_AA32_E_BIT; 2186 else 2187 regs->pstate &= ~PSR_AA32_E_BIT; 2188 } 2189 2190 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && 2191 (regs->pstate & PSR_AA32_A_BIT) == 0 && 2192 (regs->pstate & PSR_AA32_I_BIT) == 0 && 2193 (regs->pstate & PSR_AA32_F_BIT) == 0) { 2194 return 1; 2195 } 2196 2197 /* 2198 * Force PSR to a valid 32-bit EL0t, preserving the same bits as 2199 * arch/arm. 2200 */ 2201 regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT | 2202 PSR_AA32_C_BIT | PSR_AA32_V_BIT | 2203 PSR_AA32_Q_BIT | PSR_AA32_IT_MASK | 2204 PSR_AA32_GE_MASK | PSR_AA32_E_BIT | 2205 PSR_AA32_T_BIT; 2206 regs->pstate |= PSR_MODE32_BIT; 2207 2208 return 0; 2209 } 2210 2211 static int valid_native_regs(struct user_pt_regs *regs) 2212 { 2213 regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; 2214 2215 if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) && 2216 (regs->pstate & PSR_D_BIT) == 0 && 2217 (regs->pstate & PSR_A_BIT) == 0 && 2218 (regs->pstate & PSR_I_BIT) == 0 && 2219 (regs->pstate & PSR_F_BIT) == 0) { 2220 return 1; 2221 } 2222 2223 /* Force PSR to a valid 64-bit EL0t */ 2224 regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; 2225 2226 return 0; 2227 } 2228 2229 /* 2230 * Are the current registers suitable for user mode? (used to maintain 2231 * security in signal handlers) 2232 */ 2233 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task) 2234 { 2235 /* https://lore.kernel.org/lkml/20191118131525.GA4180@willie-the-truck */ 2236 user_regs_reset_single_step(regs, task); 2237 2238 if (is_compat_thread(task_thread_info(task))) 2239 return valid_compat_regs(regs); 2240 else 2241 return valid_native_regs(regs); 2242 } 2243