1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/ptrace.c 4 * 5 * By Ross Biro 1/23/92 6 * edited by Linus Torvalds 7 * ARM modifications Copyright (C) 2000 Russell King 8 * Copyright (C) 2012 ARM Ltd. 9 */ 10 11 #include <linux/audit.h> 12 #include <linux/compat.h> 13 #include <linux/kernel.h> 14 #include <linux/sched/signal.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/mm.h> 17 #include <linux/nospec.h> 18 #include <linux/smp.h> 19 #include <linux/ptrace.h> 20 #include <linux/user.h> 21 #include <linux/seccomp.h> 22 #include <linux/security.h> 23 #include <linux/init.h> 24 #include <linux/signal.h> 25 #include <linux/string.h> 26 #include <linux/uaccess.h> 27 #include <linux/perf_event.h> 28 #include <linux/hw_breakpoint.h> 29 #include <linux/regset.h> 30 #include <linux/elf.h> 31 32 #include <asm/compat.h> 33 #include <asm/cpufeature.h> 34 #include <asm/debug-monitors.h> 35 #include <asm/fpsimd.h> 36 #include <asm/mte.h> 37 #include <asm/pointer_auth.h> 38 #include <asm/stacktrace.h> 39 #include <asm/syscall.h> 40 #include <asm/traps.h> 41 #include <asm/system_misc.h> 42 43 #define CREATE_TRACE_POINTS 44 #include <trace/events/syscalls.h> 45 46 struct pt_regs_offset { 47 const char *name; 48 int offset; 49 }; 50 51 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 52 #define REG_OFFSET_END {.name = NULL, .offset = 0} 53 #define GPR_OFFSET_NAME(r) \ 54 {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])} 55 56 static const struct pt_regs_offset regoffset_table[] = { 57 GPR_OFFSET_NAME(0), 58 GPR_OFFSET_NAME(1), 59 GPR_OFFSET_NAME(2), 60 GPR_OFFSET_NAME(3), 61 GPR_OFFSET_NAME(4), 62 GPR_OFFSET_NAME(5), 63 GPR_OFFSET_NAME(6), 64 GPR_OFFSET_NAME(7), 65 GPR_OFFSET_NAME(8), 66 GPR_OFFSET_NAME(9), 67 GPR_OFFSET_NAME(10), 68 GPR_OFFSET_NAME(11), 69 GPR_OFFSET_NAME(12), 70 GPR_OFFSET_NAME(13), 71 GPR_OFFSET_NAME(14), 72 GPR_OFFSET_NAME(15), 73 GPR_OFFSET_NAME(16), 74 GPR_OFFSET_NAME(17), 75 GPR_OFFSET_NAME(18), 76 GPR_OFFSET_NAME(19), 77 GPR_OFFSET_NAME(20), 78 GPR_OFFSET_NAME(21), 79 GPR_OFFSET_NAME(22), 80 GPR_OFFSET_NAME(23), 81 GPR_OFFSET_NAME(24), 82 GPR_OFFSET_NAME(25), 83 GPR_OFFSET_NAME(26), 84 GPR_OFFSET_NAME(27), 85 GPR_OFFSET_NAME(28), 86 GPR_OFFSET_NAME(29), 87 GPR_OFFSET_NAME(30), 88 {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])}, 89 REG_OFFSET_NAME(sp), 90 REG_OFFSET_NAME(pc), 91 REG_OFFSET_NAME(pstate), 92 REG_OFFSET_END, 93 }; 94 95 /** 96 * regs_query_register_offset() - query register offset from its name 97 * @name: the name of a register 98 * 99 * regs_query_register_offset() returns the offset of a register in struct 100 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 101 */ 102 int regs_query_register_offset(const char *name) 103 { 104 const struct pt_regs_offset *roff; 105 106 for (roff = regoffset_table; roff->name != NULL; roff++) 107 if (!strcmp(roff->name, name)) 108 return roff->offset; 109 return -EINVAL; 110 } 111 112 /** 113 * regs_within_kernel_stack() - check the address in the stack 114 * @regs: pt_regs which contains kernel stack pointer. 115 * @addr: address which is checked. 116 * 117 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 118 * If @addr is within the kernel stack, it returns true. If not, returns false. 119 */ 120 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) 121 { 122 return ((addr & ~(THREAD_SIZE - 1)) == 123 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))) || 124 on_irq_stack(addr, sizeof(unsigned long)); 125 } 126 127 /** 128 * regs_get_kernel_stack_nth() - get Nth entry of the stack 129 * @regs: pt_regs which contains kernel stack pointer. 130 * @n: stack entry number. 131 * 132 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 133 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 134 * this returns 0. 135 */ 136 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) 137 { 138 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 139 140 addr += n; 141 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 142 return *addr; 143 else 144 return 0; 145 } 146 147 /* 148 * TODO: does not yet catch signals sent when the child dies. 149 * in exit.c or in signal.c. 150 */ 151 152 /* 153 * Called by kernel/ptrace.c when detaching.. 154 */ 155 void ptrace_disable(struct task_struct *child) 156 { 157 /* 158 * This would be better off in core code, but PTRACE_DETACH has 159 * grown its fair share of arch-specific worts and changing it 160 * is likely to cause regressions on obscure architectures. 161 */ 162 user_disable_single_step(child); 163 } 164 165 #ifdef CONFIG_HAVE_HW_BREAKPOINT 166 /* 167 * Handle hitting a HW-breakpoint. 168 */ 169 static void ptrace_hbptriggered(struct perf_event *bp, 170 struct perf_sample_data *data, 171 struct pt_regs *regs) 172 { 173 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); 174 const char *desc = "Hardware breakpoint trap (ptrace)"; 175 176 #ifdef CONFIG_COMPAT 177 if (is_compat_task()) { 178 int si_errno = 0; 179 int i; 180 181 for (i = 0; i < ARM_MAX_BRP; ++i) { 182 if (current->thread.debug.hbp_break[i] == bp) { 183 si_errno = (i << 1) + 1; 184 break; 185 } 186 } 187 188 for (i = 0; i < ARM_MAX_WRP; ++i) { 189 if (current->thread.debug.hbp_watch[i] == bp) { 190 si_errno = -((i << 1) + 1); 191 break; 192 } 193 } 194 arm64_force_sig_ptrace_errno_trap(si_errno, bkpt->trigger, 195 desc); 196 return; 197 } 198 #endif 199 arm64_force_sig_fault(SIGTRAP, TRAP_HWBKPT, bkpt->trigger, desc); 200 } 201 202 /* 203 * Unregister breakpoints from this task and reset the pointers in 204 * the thread_struct. 205 */ 206 void flush_ptrace_hw_breakpoint(struct task_struct *tsk) 207 { 208 int i; 209 struct thread_struct *t = &tsk->thread; 210 211 for (i = 0; i < ARM_MAX_BRP; i++) { 212 if (t->debug.hbp_break[i]) { 213 unregister_hw_breakpoint(t->debug.hbp_break[i]); 214 t->debug.hbp_break[i] = NULL; 215 } 216 } 217 218 for (i = 0; i < ARM_MAX_WRP; i++) { 219 if (t->debug.hbp_watch[i]) { 220 unregister_hw_breakpoint(t->debug.hbp_watch[i]); 221 t->debug.hbp_watch[i] = NULL; 222 } 223 } 224 } 225 226 void ptrace_hw_copy_thread(struct task_struct *tsk) 227 { 228 memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); 229 } 230 231 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type, 232 struct task_struct *tsk, 233 unsigned long idx) 234 { 235 struct perf_event *bp = ERR_PTR(-EINVAL); 236 237 switch (note_type) { 238 case NT_ARM_HW_BREAK: 239 if (idx >= ARM_MAX_BRP) 240 goto out; 241 idx = array_index_nospec(idx, ARM_MAX_BRP); 242 bp = tsk->thread.debug.hbp_break[idx]; 243 break; 244 case NT_ARM_HW_WATCH: 245 if (idx >= ARM_MAX_WRP) 246 goto out; 247 idx = array_index_nospec(idx, ARM_MAX_WRP); 248 bp = tsk->thread.debug.hbp_watch[idx]; 249 break; 250 } 251 252 out: 253 return bp; 254 } 255 256 static int ptrace_hbp_set_event(unsigned int note_type, 257 struct task_struct *tsk, 258 unsigned long idx, 259 struct perf_event *bp) 260 { 261 int err = -EINVAL; 262 263 switch (note_type) { 264 case NT_ARM_HW_BREAK: 265 if (idx >= ARM_MAX_BRP) 266 goto out; 267 idx = array_index_nospec(idx, ARM_MAX_BRP); 268 tsk->thread.debug.hbp_break[idx] = bp; 269 err = 0; 270 break; 271 case NT_ARM_HW_WATCH: 272 if (idx >= ARM_MAX_WRP) 273 goto out; 274 idx = array_index_nospec(idx, ARM_MAX_WRP); 275 tsk->thread.debug.hbp_watch[idx] = bp; 276 err = 0; 277 break; 278 } 279 280 out: 281 return err; 282 } 283 284 static struct perf_event *ptrace_hbp_create(unsigned int note_type, 285 struct task_struct *tsk, 286 unsigned long idx) 287 { 288 struct perf_event *bp; 289 struct perf_event_attr attr; 290 int err, type; 291 292 switch (note_type) { 293 case NT_ARM_HW_BREAK: 294 type = HW_BREAKPOINT_X; 295 break; 296 case NT_ARM_HW_WATCH: 297 type = HW_BREAKPOINT_RW; 298 break; 299 default: 300 return ERR_PTR(-EINVAL); 301 } 302 303 ptrace_breakpoint_init(&attr); 304 305 /* 306 * Initialise fields to sane defaults 307 * (i.e. values that will pass validation). 308 */ 309 attr.bp_addr = 0; 310 attr.bp_len = HW_BREAKPOINT_LEN_4; 311 attr.bp_type = type; 312 attr.disabled = 1; 313 314 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); 315 if (IS_ERR(bp)) 316 return bp; 317 318 err = ptrace_hbp_set_event(note_type, tsk, idx, bp); 319 if (err) 320 return ERR_PTR(err); 321 322 return bp; 323 } 324 325 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, 326 struct arch_hw_breakpoint_ctrl ctrl, 327 struct perf_event_attr *attr) 328 { 329 int err, len, type, offset, disabled = !ctrl.enabled; 330 331 attr->disabled = disabled; 332 if (disabled) 333 return 0; 334 335 err = arch_bp_generic_fields(ctrl, &len, &type, &offset); 336 if (err) 337 return err; 338 339 switch (note_type) { 340 case NT_ARM_HW_BREAK: 341 if ((type & HW_BREAKPOINT_X) != type) 342 return -EINVAL; 343 break; 344 case NT_ARM_HW_WATCH: 345 if ((type & HW_BREAKPOINT_RW) != type) 346 return -EINVAL; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 attr->bp_len = len; 353 attr->bp_type = type; 354 attr->bp_addr += offset; 355 356 return 0; 357 } 358 359 static int ptrace_hbp_get_resource_info(unsigned int note_type, u32 *info) 360 { 361 u8 num; 362 u32 reg = 0; 363 364 switch (note_type) { 365 case NT_ARM_HW_BREAK: 366 num = hw_breakpoint_slots(TYPE_INST); 367 break; 368 case NT_ARM_HW_WATCH: 369 num = hw_breakpoint_slots(TYPE_DATA); 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 reg |= debug_monitors_arch(); 376 reg <<= 8; 377 reg |= num; 378 379 *info = reg; 380 return 0; 381 } 382 383 static int ptrace_hbp_get_ctrl(unsigned int note_type, 384 struct task_struct *tsk, 385 unsigned long idx, 386 u32 *ctrl) 387 { 388 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 389 390 if (IS_ERR(bp)) 391 return PTR_ERR(bp); 392 393 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0; 394 return 0; 395 } 396 397 static int ptrace_hbp_get_addr(unsigned int note_type, 398 struct task_struct *tsk, 399 unsigned long idx, 400 u64 *addr) 401 { 402 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 403 404 if (IS_ERR(bp)) 405 return PTR_ERR(bp); 406 407 *addr = bp ? counter_arch_bp(bp)->address : 0; 408 return 0; 409 } 410 411 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type, 412 struct task_struct *tsk, 413 unsigned long idx) 414 { 415 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 416 417 if (!bp) 418 bp = ptrace_hbp_create(note_type, tsk, idx); 419 420 return bp; 421 } 422 423 static int ptrace_hbp_set_ctrl(unsigned int note_type, 424 struct task_struct *tsk, 425 unsigned long idx, 426 u32 uctrl) 427 { 428 int err; 429 struct perf_event *bp; 430 struct perf_event_attr attr; 431 struct arch_hw_breakpoint_ctrl ctrl; 432 433 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 434 if (IS_ERR(bp)) { 435 err = PTR_ERR(bp); 436 return err; 437 } 438 439 attr = bp->attr; 440 decode_ctrl_reg(uctrl, &ctrl); 441 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr); 442 if (err) 443 return err; 444 445 return modify_user_hw_breakpoint(bp, &attr); 446 } 447 448 static int ptrace_hbp_set_addr(unsigned int note_type, 449 struct task_struct *tsk, 450 unsigned long idx, 451 u64 addr) 452 { 453 int err; 454 struct perf_event *bp; 455 struct perf_event_attr attr; 456 457 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 458 if (IS_ERR(bp)) { 459 err = PTR_ERR(bp); 460 return err; 461 } 462 463 attr = bp->attr; 464 attr.bp_addr = addr; 465 err = modify_user_hw_breakpoint(bp, &attr); 466 return err; 467 } 468 469 #define PTRACE_HBP_ADDR_SZ sizeof(u64) 470 #define PTRACE_HBP_CTRL_SZ sizeof(u32) 471 #define PTRACE_HBP_PAD_SZ sizeof(u32) 472 473 static int hw_break_get(struct task_struct *target, 474 const struct user_regset *regset, 475 struct membuf to) 476 { 477 unsigned int note_type = regset->core_note_type; 478 int ret, idx = 0; 479 u32 info, ctrl; 480 u64 addr; 481 482 /* Resource info */ 483 ret = ptrace_hbp_get_resource_info(note_type, &info); 484 if (ret) 485 return ret; 486 487 membuf_write(&to, &info, sizeof(info)); 488 membuf_zero(&to, sizeof(u32)); 489 /* (address, ctrl) registers */ 490 while (to.left) { 491 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr); 492 if (ret) 493 return ret; 494 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl); 495 if (ret) 496 return ret; 497 membuf_store(&to, addr); 498 membuf_store(&to, ctrl); 499 membuf_zero(&to, sizeof(u32)); 500 idx++; 501 } 502 return 0; 503 } 504 505 static int hw_break_set(struct task_struct *target, 506 const struct user_regset *regset, 507 unsigned int pos, unsigned int count, 508 const void *kbuf, const void __user *ubuf) 509 { 510 unsigned int note_type = regset->core_note_type; 511 int ret, idx = 0, offset, limit; 512 u32 ctrl; 513 u64 addr; 514 515 /* Resource info and pad */ 516 offset = offsetof(struct user_hwdebug_state, dbg_regs); 517 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset); 518 519 /* (address, ctrl) registers */ 520 limit = regset->n * regset->size; 521 while (count && offset < limit) { 522 if (count < PTRACE_HBP_ADDR_SZ) 523 return -EINVAL; 524 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr, 525 offset, offset + PTRACE_HBP_ADDR_SZ); 526 if (ret) 527 return ret; 528 ret = ptrace_hbp_set_addr(note_type, target, idx, addr); 529 if (ret) 530 return ret; 531 offset += PTRACE_HBP_ADDR_SZ; 532 533 if (!count) 534 break; 535 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 536 offset, offset + PTRACE_HBP_CTRL_SZ); 537 if (ret) 538 return ret; 539 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl); 540 if (ret) 541 return ret; 542 offset += PTRACE_HBP_CTRL_SZ; 543 544 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 545 offset, offset + PTRACE_HBP_PAD_SZ); 546 offset += PTRACE_HBP_PAD_SZ; 547 idx++; 548 } 549 550 return 0; 551 } 552 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 553 554 static int gpr_get(struct task_struct *target, 555 const struct user_regset *regset, 556 struct membuf to) 557 { 558 struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs; 559 return membuf_write(&to, uregs, sizeof(*uregs)); 560 } 561 562 static int gpr_set(struct task_struct *target, const struct user_regset *regset, 563 unsigned int pos, unsigned int count, 564 const void *kbuf, const void __user *ubuf) 565 { 566 int ret; 567 struct user_pt_regs newregs = task_pt_regs(target)->user_regs; 568 569 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1); 570 if (ret) 571 return ret; 572 573 if (!valid_user_regs(&newregs, target)) 574 return -EINVAL; 575 576 task_pt_regs(target)->user_regs = newregs; 577 return 0; 578 } 579 580 static int fpr_active(struct task_struct *target, const struct user_regset *regset) 581 { 582 if (!system_supports_fpsimd()) 583 return -ENODEV; 584 return regset->n; 585 } 586 587 /* 588 * TODO: update fp accessors for lazy context switching (sync/flush hwstate) 589 */ 590 static int __fpr_get(struct task_struct *target, 591 const struct user_regset *regset, 592 struct membuf to) 593 { 594 struct user_fpsimd_state *uregs; 595 596 sve_sync_to_fpsimd(target); 597 598 uregs = &target->thread.uw.fpsimd_state; 599 600 return membuf_write(&to, uregs, sizeof(*uregs)); 601 } 602 603 static int fpr_get(struct task_struct *target, const struct user_regset *regset, 604 struct membuf to) 605 { 606 if (!system_supports_fpsimd()) 607 return -EINVAL; 608 609 if (target == current) 610 fpsimd_preserve_current_state(); 611 612 return __fpr_get(target, regset, to); 613 } 614 615 static int __fpr_set(struct task_struct *target, 616 const struct user_regset *regset, 617 unsigned int pos, unsigned int count, 618 const void *kbuf, const void __user *ubuf, 619 unsigned int start_pos) 620 { 621 int ret; 622 struct user_fpsimd_state newstate; 623 624 /* 625 * Ensure target->thread.uw.fpsimd_state is up to date, so that a 626 * short copyin can't resurrect stale data. 627 */ 628 sve_sync_to_fpsimd(target); 629 630 newstate = target->thread.uw.fpsimd_state; 631 632 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 633 start_pos, start_pos + sizeof(newstate)); 634 if (ret) 635 return ret; 636 637 target->thread.uw.fpsimd_state = newstate; 638 639 return ret; 640 } 641 642 static int fpr_set(struct task_struct *target, const struct user_regset *regset, 643 unsigned int pos, unsigned int count, 644 const void *kbuf, const void __user *ubuf) 645 { 646 int ret; 647 648 if (!system_supports_fpsimd()) 649 return -EINVAL; 650 651 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0); 652 if (ret) 653 return ret; 654 655 sve_sync_from_fpsimd_zeropad(target); 656 fpsimd_flush_task_state(target); 657 658 return ret; 659 } 660 661 static int tls_get(struct task_struct *target, const struct user_regset *regset, 662 struct membuf to) 663 { 664 int ret; 665 666 if (target == current) 667 tls_preserve_current_state(); 668 669 ret = membuf_store(&to, target->thread.uw.tp_value); 670 if (system_supports_tpidr2()) 671 ret = membuf_store(&to, target->thread.tpidr2_el0); 672 else 673 ret = membuf_zero(&to, sizeof(u64)); 674 675 return ret; 676 } 677 678 static int tls_set(struct task_struct *target, const struct user_regset *regset, 679 unsigned int pos, unsigned int count, 680 const void *kbuf, const void __user *ubuf) 681 { 682 int ret; 683 unsigned long tls[2]; 684 685 tls[0] = target->thread.uw.tp_value; 686 if (system_supports_tpidr2()) 687 tls[1] = target->thread.tpidr2_el0; 688 689 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, tls, 0, count); 690 if (ret) 691 return ret; 692 693 target->thread.uw.tp_value = tls[0]; 694 if (system_supports_tpidr2()) 695 target->thread.tpidr2_el0 = tls[1]; 696 697 return ret; 698 } 699 700 static int system_call_get(struct task_struct *target, 701 const struct user_regset *regset, 702 struct membuf to) 703 { 704 return membuf_store(&to, task_pt_regs(target)->syscallno); 705 } 706 707 static int system_call_set(struct task_struct *target, 708 const struct user_regset *regset, 709 unsigned int pos, unsigned int count, 710 const void *kbuf, const void __user *ubuf) 711 { 712 int syscallno = task_pt_regs(target)->syscallno; 713 int ret; 714 715 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1); 716 if (ret) 717 return ret; 718 719 task_pt_regs(target)->syscallno = syscallno; 720 return ret; 721 } 722 723 #ifdef CONFIG_ARM64_SVE 724 725 static void sve_init_header_from_task(struct user_sve_header *header, 726 struct task_struct *target, 727 enum vec_type type) 728 { 729 unsigned int vq; 730 bool active; 731 bool fpsimd_only; 732 enum vec_type task_type; 733 734 memset(header, 0, sizeof(*header)); 735 736 /* Check if the requested registers are active for the task */ 737 if (thread_sm_enabled(&target->thread)) 738 task_type = ARM64_VEC_SME; 739 else 740 task_type = ARM64_VEC_SVE; 741 active = (task_type == type); 742 743 switch (type) { 744 case ARM64_VEC_SVE: 745 if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT)) 746 header->flags |= SVE_PT_VL_INHERIT; 747 fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE); 748 break; 749 case ARM64_VEC_SME: 750 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 751 header->flags |= SVE_PT_VL_INHERIT; 752 fpsimd_only = false; 753 break; 754 default: 755 WARN_ON_ONCE(1); 756 return; 757 } 758 759 if (active) { 760 if (fpsimd_only) { 761 header->flags |= SVE_PT_REGS_FPSIMD; 762 } else { 763 header->flags |= SVE_PT_REGS_SVE; 764 } 765 } 766 767 header->vl = task_get_vl(target, type); 768 vq = sve_vq_from_vl(header->vl); 769 770 header->max_vl = vec_max_vl(type); 771 header->size = SVE_PT_SIZE(vq, header->flags); 772 header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl), 773 SVE_PT_REGS_SVE); 774 } 775 776 static unsigned int sve_size_from_header(struct user_sve_header const *header) 777 { 778 return ALIGN(header->size, SVE_VQ_BYTES); 779 } 780 781 static int sve_get_common(struct task_struct *target, 782 const struct user_regset *regset, 783 struct membuf to, 784 enum vec_type type) 785 { 786 struct user_sve_header header; 787 unsigned int vq; 788 unsigned long start, end; 789 790 /* Header */ 791 sve_init_header_from_task(&header, target, type); 792 vq = sve_vq_from_vl(header.vl); 793 794 membuf_write(&to, &header, sizeof(header)); 795 796 if (target == current) 797 fpsimd_preserve_current_state(); 798 799 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 800 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 801 802 switch ((header.flags & SVE_PT_REGS_MASK)) { 803 case SVE_PT_REGS_FPSIMD: 804 return __fpr_get(target, regset, to); 805 806 case SVE_PT_REGS_SVE: 807 start = SVE_PT_SVE_OFFSET; 808 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 809 membuf_write(&to, target->thread.sve_state, end - start); 810 811 start = end; 812 end = SVE_PT_SVE_FPSR_OFFSET(vq); 813 membuf_zero(&to, end - start); 814 815 /* 816 * Copy fpsr, and fpcr which must follow contiguously in 817 * struct fpsimd_state: 818 */ 819 start = end; 820 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 821 membuf_write(&to, &target->thread.uw.fpsimd_state.fpsr, 822 end - start); 823 824 start = end; 825 end = sve_size_from_header(&header); 826 return membuf_zero(&to, end - start); 827 828 default: 829 return 0; 830 } 831 } 832 833 static int sve_get(struct task_struct *target, 834 const struct user_regset *regset, 835 struct membuf to) 836 { 837 if (!system_supports_sve()) 838 return -EINVAL; 839 840 return sve_get_common(target, regset, to, ARM64_VEC_SVE); 841 } 842 843 static int sve_set_common(struct task_struct *target, 844 const struct user_regset *regset, 845 unsigned int pos, unsigned int count, 846 const void *kbuf, const void __user *ubuf, 847 enum vec_type type) 848 { 849 int ret; 850 struct user_sve_header header; 851 unsigned int vq; 852 unsigned long start, end; 853 854 /* Header */ 855 if (count < sizeof(header)) 856 return -EINVAL; 857 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 858 0, sizeof(header)); 859 if (ret) 860 goto out; 861 862 /* 863 * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by 864 * vec_set_vector_length(), which will also validate them for us: 865 */ 866 ret = vec_set_vector_length(target, type, header.vl, 867 ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16); 868 if (ret) 869 goto out; 870 871 /* Actual VL set may be less than the user asked for: */ 872 vq = sve_vq_from_vl(task_get_vl(target, type)); 873 874 /* Enter/exit streaming mode */ 875 if (system_supports_sme()) { 876 u64 old_svcr = target->thread.svcr; 877 878 switch (type) { 879 case ARM64_VEC_SVE: 880 target->thread.svcr &= ~SVCR_SM_MASK; 881 break; 882 case ARM64_VEC_SME: 883 target->thread.svcr |= SVCR_SM_MASK; 884 885 /* 886 * Disable traps and ensure there is SME storage but 887 * preserve any currently set values in ZA/ZT. 888 */ 889 sme_alloc(target, false); 890 set_tsk_thread_flag(target, TIF_SME); 891 break; 892 default: 893 WARN_ON_ONCE(1); 894 ret = -EINVAL; 895 goto out; 896 } 897 898 /* 899 * If we switched then invalidate any existing SVE 900 * state and ensure there's storage. 901 */ 902 if (target->thread.svcr != old_svcr) 903 sve_alloc(target, true); 904 } 905 906 /* Registers: FPSIMD-only case */ 907 908 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 909 if ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) { 910 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 911 SVE_PT_FPSIMD_OFFSET); 912 clear_tsk_thread_flag(target, TIF_SVE); 913 target->thread.fp_type = FP_STATE_FPSIMD; 914 goto out; 915 } 916 917 /* 918 * Otherwise: no registers or full SVE case. For backwards 919 * compatibility reasons we treat empty flags as SVE registers. 920 */ 921 922 /* 923 * If setting a different VL from the requested VL and there is 924 * register data, the data layout will be wrong: don't even 925 * try to set the registers in this case. 926 */ 927 if (count && vq != sve_vq_from_vl(header.vl)) { 928 ret = -EIO; 929 goto out; 930 } 931 932 sve_alloc(target, true); 933 if (!target->thread.sve_state) { 934 ret = -ENOMEM; 935 clear_tsk_thread_flag(target, TIF_SVE); 936 target->thread.fp_type = FP_STATE_FPSIMD; 937 goto out; 938 } 939 940 /* 941 * Ensure target->thread.sve_state is up to date with target's 942 * FPSIMD regs, so that a short copyin leaves trailing 943 * registers unmodified. Only enable SVE if we are 944 * configuring normal SVE, a system with streaming SVE may not 945 * have normal SVE. 946 */ 947 fpsimd_sync_to_sve(target); 948 if (type == ARM64_VEC_SVE) 949 set_tsk_thread_flag(target, TIF_SVE); 950 target->thread.fp_type = FP_STATE_SVE; 951 952 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 953 start = SVE_PT_SVE_OFFSET; 954 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 955 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 956 target->thread.sve_state, 957 start, end); 958 if (ret) 959 goto out; 960 961 start = end; 962 end = SVE_PT_SVE_FPSR_OFFSET(vq); 963 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, start, end); 964 965 /* 966 * Copy fpsr, and fpcr which must follow contiguously in 967 * struct fpsimd_state: 968 */ 969 start = end; 970 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 971 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 972 &target->thread.uw.fpsimd_state.fpsr, 973 start, end); 974 975 out: 976 fpsimd_flush_task_state(target); 977 return ret; 978 } 979 980 static int sve_set(struct task_struct *target, 981 const struct user_regset *regset, 982 unsigned int pos, unsigned int count, 983 const void *kbuf, const void __user *ubuf) 984 { 985 if (!system_supports_sve()) 986 return -EINVAL; 987 988 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 989 ARM64_VEC_SVE); 990 } 991 992 #endif /* CONFIG_ARM64_SVE */ 993 994 #ifdef CONFIG_ARM64_SME 995 996 static int ssve_get(struct task_struct *target, 997 const struct user_regset *regset, 998 struct membuf to) 999 { 1000 if (!system_supports_sme()) 1001 return -EINVAL; 1002 1003 return sve_get_common(target, regset, to, ARM64_VEC_SME); 1004 } 1005 1006 static int ssve_set(struct task_struct *target, 1007 const struct user_regset *regset, 1008 unsigned int pos, unsigned int count, 1009 const void *kbuf, const void __user *ubuf) 1010 { 1011 if (!system_supports_sme()) 1012 return -EINVAL; 1013 1014 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 1015 ARM64_VEC_SME); 1016 } 1017 1018 static int za_get(struct task_struct *target, 1019 const struct user_regset *regset, 1020 struct membuf to) 1021 { 1022 struct user_za_header header; 1023 unsigned int vq; 1024 unsigned long start, end; 1025 1026 if (!system_supports_sme()) 1027 return -EINVAL; 1028 1029 /* Header */ 1030 memset(&header, 0, sizeof(header)); 1031 1032 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 1033 header.flags |= ZA_PT_VL_INHERIT; 1034 1035 header.vl = task_get_sme_vl(target); 1036 vq = sve_vq_from_vl(header.vl); 1037 header.max_vl = sme_max_vl(); 1038 header.max_size = ZA_PT_SIZE(vq); 1039 1040 /* If ZA is not active there is only the header */ 1041 if (thread_za_enabled(&target->thread)) 1042 header.size = ZA_PT_SIZE(vq); 1043 else 1044 header.size = ZA_PT_ZA_OFFSET; 1045 1046 membuf_write(&to, &header, sizeof(header)); 1047 1048 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1049 end = ZA_PT_ZA_OFFSET; 1050 1051 if (target == current) 1052 fpsimd_preserve_current_state(); 1053 1054 /* Any register data to include? */ 1055 if (thread_za_enabled(&target->thread)) { 1056 start = end; 1057 end = ZA_PT_SIZE(vq); 1058 membuf_write(&to, target->thread.sme_state, end - start); 1059 } 1060 1061 /* Zero any trailing padding */ 1062 start = end; 1063 end = ALIGN(header.size, SVE_VQ_BYTES); 1064 return membuf_zero(&to, end - start); 1065 } 1066 1067 static int za_set(struct task_struct *target, 1068 const struct user_regset *regset, 1069 unsigned int pos, unsigned int count, 1070 const void *kbuf, const void __user *ubuf) 1071 { 1072 int ret; 1073 struct user_za_header header; 1074 unsigned int vq; 1075 unsigned long start, end; 1076 1077 if (!system_supports_sme()) 1078 return -EINVAL; 1079 1080 /* Header */ 1081 if (count < sizeof(header)) 1082 return -EINVAL; 1083 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 1084 0, sizeof(header)); 1085 if (ret) 1086 goto out; 1087 1088 /* 1089 * All current ZA_PT_* flags are consumed by 1090 * vec_set_vector_length(), which will also validate them for 1091 * us: 1092 */ 1093 ret = vec_set_vector_length(target, ARM64_VEC_SME, header.vl, 1094 ((unsigned long)header.flags) << 16); 1095 if (ret) 1096 goto out; 1097 1098 /* Actual VL set may be less than the user asked for: */ 1099 vq = sve_vq_from_vl(task_get_sme_vl(target)); 1100 1101 /* Ensure there is some SVE storage for streaming mode */ 1102 if (!target->thread.sve_state) { 1103 sve_alloc(target, false); 1104 if (!target->thread.sve_state) { 1105 ret = -ENOMEM; 1106 goto out; 1107 } 1108 } 1109 1110 /* 1111 * Only flush the storage if PSTATE.ZA was not already set, 1112 * otherwise preserve any existing data. 1113 */ 1114 sme_alloc(target, !thread_za_enabled(&target->thread)); 1115 if (!target->thread.sme_state) 1116 return -ENOMEM; 1117 1118 /* If there is no data then disable ZA */ 1119 if (!count) { 1120 target->thread.svcr &= ~SVCR_ZA_MASK; 1121 goto out; 1122 } 1123 1124 /* 1125 * If setting a different VL from the requested VL and there is 1126 * register data, the data layout will be wrong: don't even 1127 * try to set the registers in this case. 1128 */ 1129 if (vq != sve_vq_from_vl(header.vl)) { 1130 ret = -EIO; 1131 goto out; 1132 } 1133 1134 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1135 start = ZA_PT_ZA_OFFSET; 1136 end = ZA_PT_SIZE(vq); 1137 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1138 target->thread.sme_state, 1139 start, end); 1140 if (ret) 1141 goto out; 1142 1143 /* Mark ZA as active and let userspace use it */ 1144 set_tsk_thread_flag(target, TIF_SME); 1145 target->thread.svcr |= SVCR_ZA_MASK; 1146 1147 out: 1148 fpsimd_flush_task_state(target); 1149 return ret; 1150 } 1151 1152 static int zt_get(struct task_struct *target, 1153 const struct user_regset *regset, 1154 struct membuf to) 1155 { 1156 if (!system_supports_sme2()) 1157 return -EINVAL; 1158 1159 /* 1160 * If PSTATE.ZA is not set then ZT will be zeroed when it is 1161 * enabled so report the current register value as zero. 1162 */ 1163 if (thread_za_enabled(&target->thread)) 1164 membuf_write(&to, thread_zt_state(&target->thread), 1165 ZT_SIG_REG_BYTES); 1166 else 1167 membuf_zero(&to, ZT_SIG_REG_BYTES); 1168 1169 return 0; 1170 } 1171 1172 static int zt_set(struct task_struct *target, 1173 const struct user_regset *regset, 1174 unsigned int pos, unsigned int count, 1175 const void *kbuf, const void __user *ubuf) 1176 { 1177 int ret; 1178 1179 if (!system_supports_sme2()) 1180 return -EINVAL; 1181 1182 /* Ensure SVE storage in case this is first use of SME */ 1183 sve_alloc(target, false); 1184 if (!target->thread.sve_state) 1185 return -ENOMEM; 1186 1187 if (!thread_za_enabled(&target->thread)) { 1188 sme_alloc(target, true); 1189 if (!target->thread.sme_state) 1190 return -ENOMEM; 1191 } 1192 1193 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1194 thread_zt_state(&target->thread), 1195 0, ZT_SIG_REG_BYTES); 1196 if (ret == 0) { 1197 target->thread.svcr |= SVCR_ZA_MASK; 1198 set_tsk_thread_flag(target, TIF_SME); 1199 } 1200 1201 fpsimd_flush_task_state(target); 1202 1203 return ret; 1204 } 1205 1206 #endif /* CONFIG_ARM64_SME */ 1207 1208 #ifdef CONFIG_ARM64_PTR_AUTH 1209 static int pac_mask_get(struct task_struct *target, 1210 const struct user_regset *regset, 1211 struct membuf to) 1212 { 1213 /* 1214 * The PAC bits can differ across data and instruction pointers 1215 * depending on TCR_EL1.TBID*, which we may make use of in future, so 1216 * we expose separate masks. 1217 */ 1218 unsigned long mask = ptrauth_user_pac_mask(); 1219 struct user_pac_mask uregs = { 1220 .data_mask = mask, 1221 .insn_mask = mask, 1222 }; 1223 1224 if (!system_supports_address_auth()) 1225 return -EINVAL; 1226 1227 return membuf_write(&to, &uregs, sizeof(uregs)); 1228 } 1229 1230 static int pac_enabled_keys_get(struct task_struct *target, 1231 const struct user_regset *regset, 1232 struct membuf to) 1233 { 1234 long enabled_keys = ptrauth_get_enabled_keys(target); 1235 1236 if (IS_ERR_VALUE(enabled_keys)) 1237 return enabled_keys; 1238 1239 return membuf_write(&to, &enabled_keys, sizeof(enabled_keys)); 1240 } 1241 1242 static int pac_enabled_keys_set(struct task_struct *target, 1243 const struct user_regset *regset, 1244 unsigned int pos, unsigned int count, 1245 const void *kbuf, const void __user *ubuf) 1246 { 1247 int ret; 1248 long enabled_keys = ptrauth_get_enabled_keys(target); 1249 1250 if (IS_ERR_VALUE(enabled_keys)) 1251 return enabled_keys; 1252 1253 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &enabled_keys, 0, 1254 sizeof(long)); 1255 if (ret) 1256 return ret; 1257 1258 return ptrauth_set_enabled_keys(target, PR_PAC_ENABLED_KEYS_MASK, 1259 enabled_keys); 1260 } 1261 1262 #ifdef CONFIG_CHECKPOINT_RESTORE 1263 static __uint128_t pac_key_to_user(const struct ptrauth_key *key) 1264 { 1265 return (__uint128_t)key->hi << 64 | key->lo; 1266 } 1267 1268 static struct ptrauth_key pac_key_from_user(__uint128_t ukey) 1269 { 1270 struct ptrauth_key key = { 1271 .lo = (unsigned long)ukey, 1272 .hi = (unsigned long)(ukey >> 64), 1273 }; 1274 1275 return key; 1276 } 1277 1278 static void pac_address_keys_to_user(struct user_pac_address_keys *ukeys, 1279 const struct ptrauth_keys_user *keys) 1280 { 1281 ukeys->apiakey = pac_key_to_user(&keys->apia); 1282 ukeys->apibkey = pac_key_to_user(&keys->apib); 1283 ukeys->apdakey = pac_key_to_user(&keys->apda); 1284 ukeys->apdbkey = pac_key_to_user(&keys->apdb); 1285 } 1286 1287 static void pac_address_keys_from_user(struct ptrauth_keys_user *keys, 1288 const struct user_pac_address_keys *ukeys) 1289 { 1290 keys->apia = pac_key_from_user(ukeys->apiakey); 1291 keys->apib = pac_key_from_user(ukeys->apibkey); 1292 keys->apda = pac_key_from_user(ukeys->apdakey); 1293 keys->apdb = pac_key_from_user(ukeys->apdbkey); 1294 } 1295 1296 static int pac_address_keys_get(struct task_struct *target, 1297 const struct user_regset *regset, 1298 struct membuf to) 1299 { 1300 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1301 struct user_pac_address_keys user_keys; 1302 1303 if (!system_supports_address_auth()) 1304 return -EINVAL; 1305 1306 pac_address_keys_to_user(&user_keys, keys); 1307 1308 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1309 } 1310 1311 static int pac_address_keys_set(struct task_struct *target, 1312 const struct user_regset *regset, 1313 unsigned int pos, unsigned int count, 1314 const void *kbuf, const void __user *ubuf) 1315 { 1316 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1317 struct user_pac_address_keys user_keys; 1318 int ret; 1319 1320 if (!system_supports_address_auth()) 1321 return -EINVAL; 1322 1323 pac_address_keys_to_user(&user_keys, keys); 1324 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1325 &user_keys, 0, -1); 1326 if (ret) 1327 return ret; 1328 pac_address_keys_from_user(keys, &user_keys); 1329 1330 return 0; 1331 } 1332 1333 static void pac_generic_keys_to_user(struct user_pac_generic_keys *ukeys, 1334 const struct ptrauth_keys_user *keys) 1335 { 1336 ukeys->apgakey = pac_key_to_user(&keys->apga); 1337 } 1338 1339 static void pac_generic_keys_from_user(struct ptrauth_keys_user *keys, 1340 const struct user_pac_generic_keys *ukeys) 1341 { 1342 keys->apga = pac_key_from_user(ukeys->apgakey); 1343 } 1344 1345 static int pac_generic_keys_get(struct task_struct *target, 1346 const struct user_regset *regset, 1347 struct membuf to) 1348 { 1349 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1350 struct user_pac_generic_keys user_keys; 1351 1352 if (!system_supports_generic_auth()) 1353 return -EINVAL; 1354 1355 pac_generic_keys_to_user(&user_keys, keys); 1356 1357 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1358 } 1359 1360 static int pac_generic_keys_set(struct task_struct *target, 1361 const struct user_regset *regset, 1362 unsigned int pos, unsigned int count, 1363 const void *kbuf, const void __user *ubuf) 1364 { 1365 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1366 struct user_pac_generic_keys user_keys; 1367 int ret; 1368 1369 if (!system_supports_generic_auth()) 1370 return -EINVAL; 1371 1372 pac_generic_keys_to_user(&user_keys, keys); 1373 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1374 &user_keys, 0, -1); 1375 if (ret) 1376 return ret; 1377 pac_generic_keys_from_user(keys, &user_keys); 1378 1379 return 0; 1380 } 1381 #endif /* CONFIG_CHECKPOINT_RESTORE */ 1382 #endif /* CONFIG_ARM64_PTR_AUTH */ 1383 1384 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1385 static int tagged_addr_ctrl_get(struct task_struct *target, 1386 const struct user_regset *regset, 1387 struct membuf to) 1388 { 1389 long ctrl = get_tagged_addr_ctrl(target); 1390 1391 if (IS_ERR_VALUE(ctrl)) 1392 return ctrl; 1393 1394 return membuf_write(&to, &ctrl, sizeof(ctrl)); 1395 } 1396 1397 static int tagged_addr_ctrl_set(struct task_struct *target, const struct 1398 user_regset *regset, unsigned int pos, 1399 unsigned int count, const void *kbuf, const 1400 void __user *ubuf) 1401 { 1402 int ret; 1403 long ctrl; 1404 1405 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); 1406 if (ret) 1407 return ret; 1408 1409 return set_tagged_addr_ctrl(target, ctrl); 1410 } 1411 #endif 1412 1413 enum aarch64_regset { 1414 REGSET_GPR, 1415 REGSET_FPR, 1416 REGSET_TLS, 1417 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1418 REGSET_HW_BREAK, 1419 REGSET_HW_WATCH, 1420 #endif 1421 REGSET_SYSTEM_CALL, 1422 #ifdef CONFIG_ARM64_SVE 1423 REGSET_SVE, 1424 #endif 1425 #ifdef CONFIG_ARM64_SME 1426 REGSET_SSVE, 1427 REGSET_ZA, 1428 REGSET_ZT, 1429 #endif 1430 #ifdef CONFIG_ARM64_PTR_AUTH 1431 REGSET_PAC_MASK, 1432 REGSET_PAC_ENABLED_KEYS, 1433 #ifdef CONFIG_CHECKPOINT_RESTORE 1434 REGSET_PACA_KEYS, 1435 REGSET_PACG_KEYS, 1436 #endif 1437 #endif 1438 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1439 REGSET_TAGGED_ADDR_CTRL, 1440 #endif 1441 }; 1442 1443 static const struct user_regset aarch64_regsets[] = { 1444 [REGSET_GPR] = { 1445 .core_note_type = NT_PRSTATUS, 1446 .n = sizeof(struct user_pt_regs) / sizeof(u64), 1447 .size = sizeof(u64), 1448 .align = sizeof(u64), 1449 .regset_get = gpr_get, 1450 .set = gpr_set 1451 }, 1452 [REGSET_FPR] = { 1453 .core_note_type = NT_PRFPREG, 1454 .n = sizeof(struct user_fpsimd_state) / sizeof(u32), 1455 /* 1456 * We pretend we have 32-bit registers because the fpsr and 1457 * fpcr are 32-bits wide. 1458 */ 1459 .size = sizeof(u32), 1460 .align = sizeof(u32), 1461 .active = fpr_active, 1462 .regset_get = fpr_get, 1463 .set = fpr_set 1464 }, 1465 [REGSET_TLS] = { 1466 .core_note_type = NT_ARM_TLS, 1467 .n = 2, 1468 .size = sizeof(void *), 1469 .align = sizeof(void *), 1470 .regset_get = tls_get, 1471 .set = tls_set, 1472 }, 1473 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1474 [REGSET_HW_BREAK] = { 1475 .core_note_type = NT_ARM_HW_BREAK, 1476 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1477 .size = sizeof(u32), 1478 .align = sizeof(u32), 1479 .regset_get = hw_break_get, 1480 .set = hw_break_set, 1481 }, 1482 [REGSET_HW_WATCH] = { 1483 .core_note_type = NT_ARM_HW_WATCH, 1484 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1485 .size = sizeof(u32), 1486 .align = sizeof(u32), 1487 .regset_get = hw_break_get, 1488 .set = hw_break_set, 1489 }, 1490 #endif 1491 [REGSET_SYSTEM_CALL] = { 1492 .core_note_type = NT_ARM_SYSTEM_CALL, 1493 .n = 1, 1494 .size = sizeof(int), 1495 .align = sizeof(int), 1496 .regset_get = system_call_get, 1497 .set = system_call_set, 1498 }, 1499 #ifdef CONFIG_ARM64_SVE 1500 [REGSET_SVE] = { /* Scalable Vector Extension */ 1501 .core_note_type = NT_ARM_SVE, 1502 .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE), 1503 SVE_VQ_BYTES), 1504 .size = SVE_VQ_BYTES, 1505 .align = SVE_VQ_BYTES, 1506 .regset_get = sve_get, 1507 .set = sve_set, 1508 }, 1509 #endif 1510 #ifdef CONFIG_ARM64_SME 1511 [REGSET_SSVE] = { /* Streaming mode SVE */ 1512 .core_note_type = NT_ARM_SSVE, 1513 .n = DIV_ROUND_UP(SVE_PT_SIZE(SME_VQ_MAX, SVE_PT_REGS_SVE), 1514 SVE_VQ_BYTES), 1515 .size = SVE_VQ_BYTES, 1516 .align = SVE_VQ_BYTES, 1517 .regset_get = ssve_get, 1518 .set = ssve_set, 1519 }, 1520 [REGSET_ZA] = { /* SME ZA */ 1521 .core_note_type = NT_ARM_ZA, 1522 /* 1523 * ZA is a single register but it's variably sized and 1524 * the ptrace core requires that the size of any data 1525 * be an exact multiple of the configured register 1526 * size so report as though we had SVE_VQ_BYTES 1527 * registers. These values aren't exposed to 1528 * userspace. 1529 */ 1530 .n = DIV_ROUND_UP(ZA_PT_SIZE(SME_VQ_MAX), SVE_VQ_BYTES), 1531 .size = SVE_VQ_BYTES, 1532 .align = SVE_VQ_BYTES, 1533 .regset_get = za_get, 1534 .set = za_set, 1535 }, 1536 [REGSET_ZT] = { /* SME ZT */ 1537 .core_note_type = NT_ARM_ZT, 1538 .n = 1, 1539 .size = ZT_SIG_REG_BYTES, 1540 .align = sizeof(u64), 1541 .regset_get = zt_get, 1542 .set = zt_set, 1543 }, 1544 #endif 1545 #ifdef CONFIG_ARM64_PTR_AUTH 1546 [REGSET_PAC_MASK] = { 1547 .core_note_type = NT_ARM_PAC_MASK, 1548 .n = sizeof(struct user_pac_mask) / sizeof(u64), 1549 .size = sizeof(u64), 1550 .align = sizeof(u64), 1551 .regset_get = pac_mask_get, 1552 /* this cannot be set dynamically */ 1553 }, 1554 [REGSET_PAC_ENABLED_KEYS] = { 1555 .core_note_type = NT_ARM_PAC_ENABLED_KEYS, 1556 .n = 1, 1557 .size = sizeof(long), 1558 .align = sizeof(long), 1559 .regset_get = pac_enabled_keys_get, 1560 .set = pac_enabled_keys_set, 1561 }, 1562 #ifdef CONFIG_CHECKPOINT_RESTORE 1563 [REGSET_PACA_KEYS] = { 1564 .core_note_type = NT_ARM_PACA_KEYS, 1565 .n = sizeof(struct user_pac_address_keys) / sizeof(__uint128_t), 1566 .size = sizeof(__uint128_t), 1567 .align = sizeof(__uint128_t), 1568 .regset_get = pac_address_keys_get, 1569 .set = pac_address_keys_set, 1570 }, 1571 [REGSET_PACG_KEYS] = { 1572 .core_note_type = NT_ARM_PACG_KEYS, 1573 .n = sizeof(struct user_pac_generic_keys) / sizeof(__uint128_t), 1574 .size = sizeof(__uint128_t), 1575 .align = sizeof(__uint128_t), 1576 .regset_get = pac_generic_keys_get, 1577 .set = pac_generic_keys_set, 1578 }, 1579 #endif 1580 #endif 1581 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1582 [REGSET_TAGGED_ADDR_CTRL] = { 1583 .core_note_type = NT_ARM_TAGGED_ADDR_CTRL, 1584 .n = 1, 1585 .size = sizeof(long), 1586 .align = sizeof(long), 1587 .regset_get = tagged_addr_ctrl_get, 1588 .set = tagged_addr_ctrl_set, 1589 }, 1590 #endif 1591 }; 1592 1593 static const struct user_regset_view user_aarch64_view = { 1594 .name = "aarch64", .e_machine = EM_AARCH64, 1595 .regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets) 1596 }; 1597 1598 #ifdef CONFIG_COMPAT 1599 enum compat_regset { 1600 REGSET_COMPAT_GPR, 1601 REGSET_COMPAT_VFP, 1602 }; 1603 1604 static inline compat_ulong_t compat_get_user_reg(struct task_struct *task, int idx) 1605 { 1606 struct pt_regs *regs = task_pt_regs(task); 1607 1608 switch (idx) { 1609 case 15: 1610 return regs->pc; 1611 case 16: 1612 return pstate_to_compat_psr(regs->pstate); 1613 case 17: 1614 return regs->orig_x0; 1615 default: 1616 return regs->regs[idx]; 1617 } 1618 } 1619 1620 static int compat_gpr_get(struct task_struct *target, 1621 const struct user_regset *regset, 1622 struct membuf to) 1623 { 1624 int i = 0; 1625 1626 while (to.left) 1627 membuf_store(&to, compat_get_user_reg(target, i++)); 1628 return 0; 1629 } 1630 1631 static int compat_gpr_set(struct task_struct *target, 1632 const struct user_regset *regset, 1633 unsigned int pos, unsigned int count, 1634 const void *kbuf, const void __user *ubuf) 1635 { 1636 struct pt_regs newregs; 1637 int ret = 0; 1638 unsigned int i, start, num_regs; 1639 1640 /* Calculate the number of AArch32 registers contained in count */ 1641 num_regs = count / regset->size; 1642 1643 /* Convert pos into an register number */ 1644 start = pos / regset->size; 1645 1646 if (start + num_regs > regset->n) 1647 return -EIO; 1648 1649 newregs = *task_pt_regs(target); 1650 1651 for (i = 0; i < num_regs; ++i) { 1652 unsigned int idx = start + i; 1653 compat_ulong_t reg; 1654 1655 if (kbuf) { 1656 memcpy(®, kbuf, sizeof(reg)); 1657 kbuf += sizeof(reg); 1658 } else { 1659 ret = copy_from_user(®, ubuf, sizeof(reg)); 1660 if (ret) { 1661 ret = -EFAULT; 1662 break; 1663 } 1664 1665 ubuf += sizeof(reg); 1666 } 1667 1668 switch (idx) { 1669 case 15: 1670 newregs.pc = reg; 1671 break; 1672 case 16: 1673 reg = compat_psr_to_pstate(reg); 1674 newregs.pstate = reg; 1675 break; 1676 case 17: 1677 newregs.orig_x0 = reg; 1678 break; 1679 default: 1680 newregs.regs[idx] = reg; 1681 } 1682 1683 } 1684 1685 if (valid_user_regs(&newregs.user_regs, target)) 1686 *task_pt_regs(target) = newregs; 1687 else 1688 ret = -EINVAL; 1689 1690 return ret; 1691 } 1692 1693 static int compat_vfp_get(struct task_struct *target, 1694 const struct user_regset *regset, 1695 struct membuf to) 1696 { 1697 struct user_fpsimd_state *uregs; 1698 compat_ulong_t fpscr; 1699 1700 if (!system_supports_fpsimd()) 1701 return -EINVAL; 1702 1703 uregs = &target->thread.uw.fpsimd_state; 1704 1705 if (target == current) 1706 fpsimd_preserve_current_state(); 1707 1708 /* 1709 * The VFP registers are packed into the fpsimd_state, so they all sit 1710 * nicely together for us. We just need to create the fpscr separately. 1711 */ 1712 membuf_write(&to, uregs, VFP_STATE_SIZE - sizeof(compat_ulong_t)); 1713 fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) | 1714 (uregs->fpcr & VFP_FPSCR_CTRL_MASK); 1715 return membuf_store(&to, fpscr); 1716 } 1717 1718 static int compat_vfp_set(struct task_struct *target, 1719 const struct user_regset *regset, 1720 unsigned int pos, unsigned int count, 1721 const void *kbuf, const void __user *ubuf) 1722 { 1723 struct user_fpsimd_state *uregs; 1724 compat_ulong_t fpscr; 1725 int ret, vregs_end_pos; 1726 1727 if (!system_supports_fpsimd()) 1728 return -EINVAL; 1729 1730 uregs = &target->thread.uw.fpsimd_state; 1731 1732 vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t); 1733 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 1734 vregs_end_pos); 1735 1736 if (count && !ret) { 1737 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpscr, 1738 vregs_end_pos, VFP_STATE_SIZE); 1739 if (!ret) { 1740 uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK; 1741 uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK; 1742 } 1743 } 1744 1745 fpsimd_flush_task_state(target); 1746 return ret; 1747 } 1748 1749 static int compat_tls_get(struct task_struct *target, 1750 const struct user_regset *regset, 1751 struct membuf to) 1752 { 1753 return membuf_store(&to, (compat_ulong_t)target->thread.uw.tp_value); 1754 } 1755 1756 static int compat_tls_set(struct task_struct *target, 1757 const struct user_regset *regset, unsigned int pos, 1758 unsigned int count, const void *kbuf, 1759 const void __user *ubuf) 1760 { 1761 int ret; 1762 compat_ulong_t tls = target->thread.uw.tp_value; 1763 1764 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1); 1765 if (ret) 1766 return ret; 1767 1768 target->thread.uw.tp_value = tls; 1769 return ret; 1770 } 1771 1772 static const struct user_regset aarch32_regsets[] = { 1773 [REGSET_COMPAT_GPR] = { 1774 .core_note_type = NT_PRSTATUS, 1775 .n = COMPAT_ELF_NGREG, 1776 .size = sizeof(compat_elf_greg_t), 1777 .align = sizeof(compat_elf_greg_t), 1778 .regset_get = compat_gpr_get, 1779 .set = compat_gpr_set 1780 }, 1781 [REGSET_COMPAT_VFP] = { 1782 .core_note_type = NT_ARM_VFP, 1783 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1784 .size = sizeof(compat_ulong_t), 1785 .align = sizeof(compat_ulong_t), 1786 .active = fpr_active, 1787 .regset_get = compat_vfp_get, 1788 .set = compat_vfp_set 1789 }, 1790 }; 1791 1792 static const struct user_regset_view user_aarch32_view = { 1793 .name = "aarch32", .e_machine = EM_ARM, 1794 .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets) 1795 }; 1796 1797 static const struct user_regset aarch32_ptrace_regsets[] = { 1798 [REGSET_GPR] = { 1799 .core_note_type = NT_PRSTATUS, 1800 .n = COMPAT_ELF_NGREG, 1801 .size = sizeof(compat_elf_greg_t), 1802 .align = sizeof(compat_elf_greg_t), 1803 .regset_get = compat_gpr_get, 1804 .set = compat_gpr_set 1805 }, 1806 [REGSET_FPR] = { 1807 .core_note_type = NT_ARM_VFP, 1808 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1809 .size = sizeof(compat_ulong_t), 1810 .align = sizeof(compat_ulong_t), 1811 .regset_get = compat_vfp_get, 1812 .set = compat_vfp_set 1813 }, 1814 [REGSET_TLS] = { 1815 .core_note_type = NT_ARM_TLS, 1816 .n = 1, 1817 .size = sizeof(compat_ulong_t), 1818 .align = sizeof(compat_ulong_t), 1819 .regset_get = compat_tls_get, 1820 .set = compat_tls_set, 1821 }, 1822 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1823 [REGSET_HW_BREAK] = { 1824 .core_note_type = NT_ARM_HW_BREAK, 1825 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1826 .size = sizeof(u32), 1827 .align = sizeof(u32), 1828 .regset_get = hw_break_get, 1829 .set = hw_break_set, 1830 }, 1831 [REGSET_HW_WATCH] = { 1832 .core_note_type = NT_ARM_HW_WATCH, 1833 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1834 .size = sizeof(u32), 1835 .align = sizeof(u32), 1836 .regset_get = hw_break_get, 1837 .set = hw_break_set, 1838 }, 1839 #endif 1840 [REGSET_SYSTEM_CALL] = { 1841 .core_note_type = NT_ARM_SYSTEM_CALL, 1842 .n = 1, 1843 .size = sizeof(int), 1844 .align = sizeof(int), 1845 .regset_get = system_call_get, 1846 .set = system_call_set, 1847 }, 1848 }; 1849 1850 static const struct user_regset_view user_aarch32_ptrace_view = { 1851 .name = "aarch32", .e_machine = EM_ARM, 1852 .regsets = aarch32_ptrace_regsets, .n = ARRAY_SIZE(aarch32_ptrace_regsets) 1853 }; 1854 1855 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off, 1856 compat_ulong_t __user *ret) 1857 { 1858 compat_ulong_t tmp; 1859 1860 if (off & 3) 1861 return -EIO; 1862 1863 if (off == COMPAT_PT_TEXT_ADDR) 1864 tmp = tsk->mm->start_code; 1865 else if (off == COMPAT_PT_DATA_ADDR) 1866 tmp = tsk->mm->start_data; 1867 else if (off == COMPAT_PT_TEXT_END_ADDR) 1868 tmp = tsk->mm->end_code; 1869 else if (off < sizeof(compat_elf_gregset_t)) 1870 tmp = compat_get_user_reg(tsk, off >> 2); 1871 else if (off >= COMPAT_USER_SZ) 1872 return -EIO; 1873 else 1874 tmp = 0; 1875 1876 return put_user(tmp, ret); 1877 } 1878 1879 static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off, 1880 compat_ulong_t val) 1881 { 1882 struct pt_regs newregs = *task_pt_regs(tsk); 1883 unsigned int idx = off / 4; 1884 1885 if (off & 3 || off >= COMPAT_USER_SZ) 1886 return -EIO; 1887 1888 if (off >= sizeof(compat_elf_gregset_t)) 1889 return 0; 1890 1891 switch (idx) { 1892 case 15: 1893 newregs.pc = val; 1894 break; 1895 case 16: 1896 newregs.pstate = compat_psr_to_pstate(val); 1897 break; 1898 case 17: 1899 newregs.orig_x0 = val; 1900 break; 1901 default: 1902 newregs.regs[idx] = val; 1903 } 1904 1905 if (!valid_user_regs(&newregs.user_regs, tsk)) 1906 return -EINVAL; 1907 1908 *task_pt_regs(tsk) = newregs; 1909 return 0; 1910 } 1911 1912 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1913 1914 /* 1915 * Convert a virtual register number into an index for a thread_info 1916 * breakpoint array. Breakpoints are identified using positive numbers 1917 * whilst watchpoints are negative. The registers are laid out as pairs 1918 * of (address, control), each pair mapping to a unique hw_breakpoint struct. 1919 * Register 0 is reserved for describing resource information. 1920 */ 1921 static int compat_ptrace_hbp_num_to_idx(compat_long_t num) 1922 { 1923 return (abs(num) - 1) >> 1; 1924 } 1925 1926 static int compat_ptrace_hbp_get_resource_info(u32 *kdata) 1927 { 1928 u8 num_brps, num_wrps, debug_arch, wp_len; 1929 u32 reg = 0; 1930 1931 num_brps = hw_breakpoint_slots(TYPE_INST); 1932 num_wrps = hw_breakpoint_slots(TYPE_DATA); 1933 1934 debug_arch = debug_monitors_arch(); 1935 wp_len = 8; 1936 reg |= debug_arch; 1937 reg <<= 8; 1938 reg |= wp_len; 1939 reg <<= 8; 1940 reg |= num_wrps; 1941 reg <<= 8; 1942 reg |= num_brps; 1943 1944 *kdata = reg; 1945 return 0; 1946 } 1947 1948 static int compat_ptrace_hbp_get(unsigned int note_type, 1949 struct task_struct *tsk, 1950 compat_long_t num, 1951 u32 *kdata) 1952 { 1953 u64 addr = 0; 1954 u32 ctrl = 0; 1955 1956 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1957 1958 if (num & 1) { 1959 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr); 1960 *kdata = (u32)addr; 1961 } else { 1962 err = ptrace_hbp_get_ctrl(note_type, tsk, idx, &ctrl); 1963 *kdata = ctrl; 1964 } 1965 1966 return err; 1967 } 1968 1969 static int compat_ptrace_hbp_set(unsigned int note_type, 1970 struct task_struct *tsk, 1971 compat_long_t num, 1972 u32 *kdata) 1973 { 1974 u64 addr; 1975 u32 ctrl; 1976 1977 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1978 1979 if (num & 1) { 1980 addr = *kdata; 1981 err = ptrace_hbp_set_addr(note_type, tsk, idx, addr); 1982 } else { 1983 ctrl = *kdata; 1984 err = ptrace_hbp_set_ctrl(note_type, tsk, idx, ctrl); 1985 } 1986 1987 return err; 1988 } 1989 1990 static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num, 1991 compat_ulong_t __user *data) 1992 { 1993 int ret; 1994 u32 kdata; 1995 1996 /* Watchpoint */ 1997 if (num < 0) { 1998 ret = compat_ptrace_hbp_get(NT_ARM_HW_WATCH, tsk, num, &kdata); 1999 /* Resource info */ 2000 } else if (num == 0) { 2001 ret = compat_ptrace_hbp_get_resource_info(&kdata); 2002 /* Breakpoint */ 2003 } else { 2004 ret = compat_ptrace_hbp_get(NT_ARM_HW_BREAK, tsk, num, &kdata); 2005 } 2006 2007 if (!ret) 2008 ret = put_user(kdata, data); 2009 2010 return ret; 2011 } 2012 2013 static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num, 2014 compat_ulong_t __user *data) 2015 { 2016 int ret; 2017 u32 kdata = 0; 2018 2019 if (num == 0) 2020 return 0; 2021 2022 ret = get_user(kdata, data); 2023 if (ret) 2024 return ret; 2025 2026 if (num < 0) 2027 ret = compat_ptrace_hbp_set(NT_ARM_HW_WATCH, tsk, num, &kdata); 2028 else 2029 ret = compat_ptrace_hbp_set(NT_ARM_HW_BREAK, tsk, num, &kdata); 2030 2031 return ret; 2032 } 2033 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 2034 2035 long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 2036 compat_ulong_t caddr, compat_ulong_t cdata) 2037 { 2038 unsigned long addr = caddr; 2039 unsigned long data = cdata; 2040 void __user *datap = compat_ptr(data); 2041 int ret; 2042 2043 switch (request) { 2044 case PTRACE_PEEKUSR: 2045 ret = compat_ptrace_read_user(child, addr, datap); 2046 break; 2047 2048 case PTRACE_POKEUSR: 2049 ret = compat_ptrace_write_user(child, addr, data); 2050 break; 2051 2052 case COMPAT_PTRACE_GETREGS: 2053 ret = copy_regset_to_user(child, 2054 &user_aarch32_view, 2055 REGSET_COMPAT_GPR, 2056 0, sizeof(compat_elf_gregset_t), 2057 datap); 2058 break; 2059 2060 case COMPAT_PTRACE_SETREGS: 2061 ret = copy_regset_from_user(child, 2062 &user_aarch32_view, 2063 REGSET_COMPAT_GPR, 2064 0, sizeof(compat_elf_gregset_t), 2065 datap); 2066 break; 2067 2068 case COMPAT_PTRACE_GET_THREAD_AREA: 2069 ret = put_user((compat_ulong_t)child->thread.uw.tp_value, 2070 (compat_ulong_t __user *)datap); 2071 break; 2072 2073 case COMPAT_PTRACE_SET_SYSCALL: 2074 task_pt_regs(child)->syscallno = data; 2075 ret = 0; 2076 break; 2077 2078 case COMPAT_PTRACE_GETVFPREGS: 2079 ret = copy_regset_to_user(child, 2080 &user_aarch32_view, 2081 REGSET_COMPAT_VFP, 2082 0, VFP_STATE_SIZE, 2083 datap); 2084 break; 2085 2086 case COMPAT_PTRACE_SETVFPREGS: 2087 ret = copy_regset_from_user(child, 2088 &user_aarch32_view, 2089 REGSET_COMPAT_VFP, 2090 0, VFP_STATE_SIZE, 2091 datap); 2092 break; 2093 2094 #ifdef CONFIG_HAVE_HW_BREAKPOINT 2095 case COMPAT_PTRACE_GETHBPREGS: 2096 ret = compat_ptrace_gethbpregs(child, addr, datap); 2097 break; 2098 2099 case COMPAT_PTRACE_SETHBPREGS: 2100 ret = compat_ptrace_sethbpregs(child, addr, datap); 2101 break; 2102 #endif 2103 2104 default: 2105 ret = compat_ptrace_request(child, request, addr, 2106 data); 2107 break; 2108 } 2109 2110 return ret; 2111 } 2112 #endif /* CONFIG_COMPAT */ 2113 2114 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 2115 { 2116 #ifdef CONFIG_COMPAT 2117 /* 2118 * Core dumping of 32-bit tasks or compat ptrace requests must use the 2119 * user_aarch32_view compatible with arm32. Native ptrace requests on 2120 * 32-bit children use an extended user_aarch32_ptrace_view to allow 2121 * access to the TLS register. 2122 */ 2123 if (is_compat_task()) 2124 return &user_aarch32_view; 2125 else if (is_compat_thread(task_thread_info(task))) 2126 return &user_aarch32_ptrace_view; 2127 #endif 2128 return &user_aarch64_view; 2129 } 2130 2131 long arch_ptrace(struct task_struct *child, long request, 2132 unsigned long addr, unsigned long data) 2133 { 2134 switch (request) { 2135 case PTRACE_PEEKMTETAGS: 2136 case PTRACE_POKEMTETAGS: 2137 return mte_ptrace_copy_tags(child, request, addr, data); 2138 } 2139 2140 return ptrace_request(child, request, addr, data); 2141 } 2142 2143 enum ptrace_syscall_dir { 2144 PTRACE_SYSCALL_ENTER = 0, 2145 PTRACE_SYSCALL_EXIT, 2146 }; 2147 2148 static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir) 2149 { 2150 int regno; 2151 unsigned long saved_reg; 2152 2153 /* 2154 * We have some ABI weirdness here in the way that we handle syscall 2155 * exit stops because we indicate whether or not the stop has been 2156 * signalled from syscall entry or syscall exit by clobbering a general 2157 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee 2158 * and restoring its old value after the stop. This means that: 2159 * 2160 * - Any writes by the tracer to this register during the stop are 2161 * ignored/discarded. 2162 * 2163 * - The actual value of the register is not available during the stop, 2164 * so the tracer cannot save it and restore it later. 2165 * 2166 * - Syscall stops behave differently to seccomp and pseudo-step traps 2167 * (the latter do not nobble any registers). 2168 */ 2169 regno = (is_compat_task() ? 12 : 7); 2170 saved_reg = regs->regs[regno]; 2171 regs->regs[regno] = dir; 2172 2173 if (dir == PTRACE_SYSCALL_ENTER) { 2174 if (ptrace_report_syscall_entry(regs)) 2175 forget_syscall(regs); 2176 regs->regs[regno] = saved_reg; 2177 } else if (!test_thread_flag(TIF_SINGLESTEP)) { 2178 ptrace_report_syscall_exit(regs, 0); 2179 regs->regs[regno] = saved_reg; 2180 } else { 2181 regs->regs[regno] = saved_reg; 2182 2183 /* 2184 * Signal a pseudo-step exception since we are stepping but 2185 * tracer modifications to the registers may have rewound the 2186 * state machine. 2187 */ 2188 ptrace_report_syscall_exit(regs, 1); 2189 } 2190 } 2191 2192 int syscall_trace_enter(struct pt_regs *regs) 2193 { 2194 unsigned long flags = read_thread_flags(); 2195 2196 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { 2197 report_syscall(regs, PTRACE_SYSCALL_ENTER); 2198 if (flags & _TIF_SYSCALL_EMU) 2199 return NO_SYSCALL; 2200 } 2201 2202 /* Do the secure computing after ptrace; failures should be fast. */ 2203 if (secure_computing() == -1) 2204 return NO_SYSCALL; 2205 2206 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) 2207 trace_sys_enter(regs, regs->syscallno); 2208 2209 audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1], 2210 regs->regs[2], regs->regs[3]); 2211 2212 return regs->syscallno; 2213 } 2214 2215 void syscall_trace_exit(struct pt_regs *regs) 2216 { 2217 unsigned long flags = read_thread_flags(); 2218 2219 audit_syscall_exit(regs); 2220 2221 if (flags & _TIF_SYSCALL_TRACEPOINT) 2222 trace_sys_exit(regs, syscall_get_return_value(current, regs)); 2223 2224 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) 2225 report_syscall(regs, PTRACE_SYSCALL_EXIT); 2226 2227 rseq_syscall(regs); 2228 } 2229 2230 /* 2231 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. 2232 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is 2233 * not described in ARM DDI 0487D.a. 2234 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may 2235 * be allocated an EL0 meaning in future. 2236 * Userspace cannot use these until they have an architectural meaning. 2237 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format. 2238 * We also reserve IL for the kernel; SS is handled dynamically. 2239 */ 2240 #define SPSR_EL1_AARCH64_RES0_BITS \ 2241 (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \ 2242 GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5)) 2243 #define SPSR_EL1_AARCH32_RES0_BITS \ 2244 (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) 2245 2246 static int valid_compat_regs(struct user_pt_regs *regs) 2247 { 2248 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; 2249 2250 if (!system_supports_mixed_endian_el0()) { 2251 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 2252 regs->pstate |= PSR_AA32_E_BIT; 2253 else 2254 regs->pstate &= ~PSR_AA32_E_BIT; 2255 } 2256 2257 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && 2258 (regs->pstate & PSR_AA32_A_BIT) == 0 && 2259 (regs->pstate & PSR_AA32_I_BIT) == 0 && 2260 (regs->pstate & PSR_AA32_F_BIT) == 0) { 2261 return 1; 2262 } 2263 2264 /* 2265 * Force PSR to a valid 32-bit EL0t, preserving the same bits as 2266 * arch/arm. 2267 */ 2268 regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT | 2269 PSR_AA32_C_BIT | PSR_AA32_V_BIT | 2270 PSR_AA32_Q_BIT | PSR_AA32_IT_MASK | 2271 PSR_AA32_GE_MASK | PSR_AA32_E_BIT | 2272 PSR_AA32_T_BIT; 2273 regs->pstate |= PSR_MODE32_BIT; 2274 2275 return 0; 2276 } 2277 2278 static int valid_native_regs(struct user_pt_regs *regs) 2279 { 2280 regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; 2281 2282 if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) && 2283 (regs->pstate & PSR_D_BIT) == 0 && 2284 (regs->pstate & PSR_A_BIT) == 0 && 2285 (regs->pstate & PSR_I_BIT) == 0 && 2286 (regs->pstate & PSR_F_BIT) == 0) { 2287 return 1; 2288 } 2289 2290 /* Force PSR to a valid 64-bit EL0t */ 2291 regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; 2292 2293 return 0; 2294 } 2295 2296 /* 2297 * Are the current registers suitable for user mode? (used to maintain 2298 * security in signal handlers) 2299 */ 2300 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task) 2301 { 2302 /* https://lore.kernel.org/lkml/20191118131525.GA4180@willie-the-truck */ 2303 user_regs_reset_single_step(regs, task); 2304 2305 if (is_compat_thread(task_thread_info(task))) 2306 return valid_compat_regs(regs); 2307 else 2308 return valid_native_regs(regs); 2309 } 2310