1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/ptrace.c 4 * 5 * By Ross Biro 1/23/92 6 * edited by Linus Torvalds 7 * ARM modifications Copyright (C) 2000 Russell King 8 * Copyright (C) 2012 ARM Ltd. 9 */ 10 11 #include <linux/audit.h> 12 #include <linux/compat.h> 13 #include <linux/kernel.h> 14 #include <linux/sched/signal.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/mm.h> 17 #include <linux/nospec.h> 18 #include <linux/smp.h> 19 #include <linux/ptrace.h> 20 #include <linux/user.h> 21 #include <linux/seccomp.h> 22 #include <linux/security.h> 23 #include <linux/init.h> 24 #include <linux/signal.h> 25 #include <linux/string.h> 26 #include <linux/uaccess.h> 27 #include <linux/perf_event.h> 28 #include <linux/hw_breakpoint.h> 29 #include <linux/regset.h> 30 #include <linux/elf.h> 31 32 #include <asm/compat.h> 33 #include <asm/cpufeature.h> 34 #include <asm/debug-monitors.h> 35 #include <asm/fpsimd.h> 36 #include <asm/mte.h> 37 #include <asm/pointer_auth.h> 38 #include <asm/stacktrace.h> 39 #include <asm/syscall.h> 40 #include <asm/traps.h> 41 #include <asm/system_misc.h> 42 43 #define CREATE_TRACE_POINTS 44 #include <trace/events/syscalls.h> 45 46 struct pt_regs_offset { 47 const char *name; 48 int offset; 49 }; 50 51 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 52 #define REG_OFFSET_END {.name = NULL, .offset = 0} 53 #define GPR_OFFSET_NAME(r) \ 54 {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])} 55 56 static const struct pt_regs_offset regoffset_table[] = { 57 GPR_OFFSET_NAME(0), 58 GPR_OFFSET_NAME(1), 59 GPR_OFFSET_NAME(2), 60 GPR_OFFSET_NAME(3), 61 GPR_OFFSET_NAME(4), 62 GPR_OFFSET_NAME(5), 63 GPR_OFFSET_NAME(6), 64 GPR_OFFSET_NAME(7), 65 GPR_OFFSET_NAME(8), 66 GPR_OFFSET_NAME(9), 67 GPR_OFFSET_NAME(10), 68 GPR_OFFSET_NAME(11), 69 GPR_OFFSET_NAME(12), 70 GPR_OFFSET_NAME(13), 71 GPR_OFFSET_NAME(14), 72 GPR_OFFSET_NAME(15), 73 GPR_OFFSET_NAME(16), 74 GPR_OFFSET_NAME(17), 75 GPR_OFFSET_NAME(18), 76 GPR_OFFSET_NAME(19), 77 GPR_OFFSET_NAME(20), 78 GPR_OFFSET_NAME(21), 79 GPR_OFFSET_NAME(22), 80 GPR_OFFSET_NAME(23), 81 GPR_OFFSET_NAME(24), 82 GPR_OFFSET_NAME(25), 83 GPR_OFFSET_NAME(26), 84 GPR_OFFSET_NAME(27), 85 GPR_OFFSET_NAME(28), 86 GPR_OFFSET_NAME(29), 87 GPR_OFFSET_NAME(30), 88 {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])}, 89 REG_OFFSET_NAME(sp), 90 REG_OFFSET_NAME(pc), 91 REG_OFFSET_NAME(pstate), 92 REG_OFFSET_END, 93 }; 94 95 /** 96 * regs_query_register_offset() - query register offset from its name 97 * @name: the name of a register 98 * 99 * regs_query_register_offset() returns the offset of a register in struct 100 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 101 */ 102 int regs_query_register_offset(const char *name) 103 { 104 const struct pt_regs_offset *roff; 105 106 for (roff = regoffset_table; roff->name != NULL; roff++) 107 if (!strcmp(roff->name, name)) 108 return roff->offset; 109 return -EINVAL; 110 } 111 112 /** 113 * regs_within_kernel_stack() - check the address in the stack 114 * @regs: pt_regs which contains kernel stack pointer. 115 * @addr: address which is checked. 116 * 117 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 118 * If @addr is within the kernel stack, it returns true. If not, returns false. 119 */ 120 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) 121 { 122 return ((addr & ~(THREAD_SIZE - 1)) == 123 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))) || 124 on_irq_stack(addr, sizeof(unsigned long)); 125 } 126 127 /** 128 * regs_get_kernel_stack_nth() - get Nth entry of the stack 129 * @regs: pt_regs which contains kernel stack pointer. 130 * @n: stack entry number. 131 * 132 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 133 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 134 * this returns 0. 135 */ 136 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) 137 { 138 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 139 140 addr += n; 141 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 142 return *addr; 143 else 144 return 0; 145 } 146 147 /* 148 * TODO: does not yet catch signals sent when the child dies. 149 * in exit.c or in signal.c. 150 */ 151 152 /* 153 * Called by kernel/ptrace.c when detaching.. 154 */ 155 void ptrace_disable(struct task_struct *child) 156 { 157 /* 158 * This would be better off in core code, but PTRACE_DETACH has 159 * grown its fair share of arch-specific worts and changing it 160 * is likely to cause regressions on obscure architectures. 161 */ 162 user_disable_single_step(child); 163 } 164 165 #ifdef CONFIG_HAVE_HW_BREAKPOINT 166 /* 167 * Handle hitting a HW-breakpoint. 168 */ 169 static void ptrace_hbptriggered(struct perf_event *bp, 170 struct perf_sample_data *data, 171 struct pt_regs *regs) 172 { 173 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); 174 const char *desc = "Hardware breakpoint trap (ptrace)"; 175 176 #ifdef CONFIG_COMPAT 177 if (is_compat_task()) { 178 int si_errno = 0; 179 int i; 180 181 for (i = 0; i < ARM_MAX_BRP; ++i) { 182 if (current->thread.debug.hbp_break[i] == bp) { 183 si_errno = (i << 1) + 1; 184 break; 185 } 186 } 187 188 for (i = 0; i < ARM_MAX_WRP; ++i) { 189 if (current->thread.debug.hbp_watch[i] == bp) { 190 si_errno = -((i << 1) + 1); 191 break; 192 } 193 } 194 arm64_force_sig_ptrace_errno_trap(si_errno, bkpt->trigger, 195 desc); 196 return; 197 } 198 #endif 199 arm64_force_sig_fault(SIGTRAP, TRAP_HWBKPT, bkpt->trigger, desc); 200 } 201 202 /* 203 * Unregister breakpoints from this task and reset the pointers in 204 * the thread_struct. 205 */ 206 void flush_ptrace_hw_breakpoint(struct task_struct *tsk) 207 { 208 int i; 209 struct thread_struct *t = &tsk->thread; 210 211 for (i = 0; i < ARM_MAX_BRP; i++) { 212 if (t->debug.hbp_break[i]) { 213 unregister_hw_breakpoint(t->debug.hbp_break[i]); 214 t->debug.hbp_break[i] = NULL; 215 } 216 } 217 218 for (i = 0; i < ARM_MAX_WRP; i++) { 219 if (t->debug.hbp_watch[i]) { 220 unregister_hw_breakpoint(t->debug.hbp_watch[i]); 221 t->debug.hbp_watch[i] = NULL; 222 } 223 } 224 } 225 226 void ptrace_hw_copy_thread(struct task_struct *tsk) 227 { 228 memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); 229 } 230 231 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type, 232 struct task_struct *tsk, 233 unsigned long idx) 234 { 235 struct perf_event *bp = ERR_PTR(-EINVAL); 236 237 switch (note_type) { 238 case NT_ARM_HW_BREAK: 239 if (idx >= ARM_MAX_BRP) 240 goto out; 241 idx = array_index_nospec(idx, ARM_MAX_BRP); 242 bp = tsk->thread.debug.hbp_break[idx]; 243 break; 244 case NT_ARM_HW_WATCH: 245 if (idx >= ARM_MAX_WRP) 246 goto out; 247 idx = array_index_nospec(idx, ARM_MAX_WRP); 248 bp = tsk->thread.debug.hbp_watch[idx]; 249 break; 250 } 251 252 out: 253 return bp; 254 } 255 256 static int ptrace_hbp_set_event(unsigned int note_type, 257 struct task_struct *tsk, 258 unsigned long idx, 259 struct perf_event *bp) 260 { 261 int err = -EINVAL; 262 263 switch (note_type) { 264 case NT_ARM_HW_BREAK: 265 if (idx >= ARM_MAX_BRP) 266 goto out; 267 idx = array_index_nospec(idx, ARM_MAX_BRP); 268 tsk->thread.debug.hbp_break[idx] = bp; 269 err = 0; 270 break; 271 case NT_ARM_HW_WATCH: 272 if (idx >= ARM_MAX_WRP) 273 goto out; 274 idx = array_index_nospec(idx, ARM_MAX_WRP); 275 tsk->thread.debug.hbp_watch[idx] = bp; 276 err = 0; 277 break; 278 } 279 280 out: 281 return err; 282 } 283 284 static struct perf_event *ptrace_hbp_create(unsigned int note_type, 285 struct task_struct *tsk, 286 unsigned long idx) 287 { 288 struct perf_event *bp; 289 struct perf_event_attr attr; 290 int err, type; 291 292 switch (note_type) { 293 case NT_ARM_HW_BREAK: 294 type = HW_BREAKPOINT_X; 295 break; 296 case NT_ARM_HW_WATCH: 297 type = HW_BREAKPOINT_RW; 298 break; 299 default: 300 return ERR_PTR(-EINVAL); 301 } 302 303 ptrace_breakpoint_init(&attr); 304 305 /* 306 * Initialise fields to sane defaults 307 * (i.e. values that will pass validation). 308 */ 309 attr.bp_addr = 0; 310 attr.bp_len = HW_BREAKPOINT_LEN_4; 311 attr.bp_type = type; 312 attr.disabled = 1; 313 314 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); 315 if (IS_ERR(bp)) 316 return bp; 317 318 err = ptrace_hbp_set_event(note_type, tsk, idx, bp); 319 if (err) 320 return ERR_PTR(err); 321 322 return bp; 323 } 324 325 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, 326 struct arch_hw_breakpoint_ctrl ctrl, 327 struct perf_event_attr *attr) 328 { 329 int err, len, type, offset, disabled = !ctrl.enabled; 330 331 attr->disabled = disabled; 332 if (disabled) 333 return 0; 334 335 err = arch_bp_generic_fields(ctrl, &len, &type, &offset); 336 if (err) 337 return err; 338 339 switch (note_type) { 340 case NT_ARM_HW_BREAK: 341 if ((type & HW_BREAKPOINT_X) != type) 342 return -EINVAL; 343 break; 344 case NT_ARM_HW_WATCH: 345 if ((type & HW_BREAKPOINT_RW) != type) 346 return -EINVAL; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 attr->bp_len = len; 353 attr->bp_type = type; 354 attr->bp_addr += offset; 355 356 return 0; 357 } 358 359 static int ptrace_hbp_get_resource_info(unsigned int note_type, u32 *info) 360 { 361 u8 num; 362 u32 reg = 0; 363 364 switch (note_type) { 365 case NT_ARM_HW_BREAK: 366 num = hw_breakpoint_slots(TYPE_INST); 367 break; 368 case NT_ARM_HW_WATCH: 369 num = hw_breakpoint_slots(TYPE_DATA); 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 reg |= debug_monitors_arch(); 376 reg <<= 8; 377 reg |= num; 378 379 *info = reg; 380 return 0; 381 } 382 383 static int ptrace_hbp_get_ctrl(unsigned int note_type, 384 struct task_struct *tsk, 385 unsigned long idx, 386 u32 *ctrl) 387 { 388 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 389 390 if (IS_ERR(bp)) 391 return PTR_ERR(bp); 392 393 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0; 394 return 0; 395 } 396 397 static int ptrace_hbp_get_addr(unsigned int note_type, 398 struct task_struct *tsk, 399 unsigned long idx, 400 u64 *addr) 401 { 402 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 403 404 if (IS_ERR(bp)) 405 return PTR_ERR(bp); 406 407 *addr = bp ? counter_arch_bp(bp)->address : 0; 408 return 0; 409 } 410 411 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type, 412 struct task_struct *tsk, 413 unsigned long idx) 414 { 415 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 416 417 if (!bp) 418 bp = ptrace_hbp_create(note_type, tsk, idx); 419 420 return bp; 421 } 422 423 static int ptrace_hbp_set_ctrl(unsigned int note_type, 424 struct task_struct *tsk, 425 unsigned long idx, 426 u32 uctrl) 427 { 428 int err; 429 struct perf_event *bp; 430 struct perf_event_attr attr; 431 struct arch_hw_breakpoint_ctrl ctrl; 432 433 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 434 if (IS_ERR(bp)) { 435 err = PTR_ERR(bp); 436 return err; 437 } 438 439 attr = bp->attr; 440 decode_ctrl_reg(uctrl, &ctrl); 441 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr); 442 if (err) 443 return err; 444 445 return modify_user_hw_breakpoint(bp, &attr); 446 } 447 448 static int ptrace_hbp_set_addr(unsigned int note_type, 449 struct task_struct *tsk, 450 unsigned long idx, 451 u64 addr) 452 { 453 int err; 454 struct perf_event *bp; 455 struct perf_event_attr attr; 456 457 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 458 if (IS_ERR(bp)) { 459 err = PTR_ERR(bp); 460 return err; 461 } 462 463 attr = bp->attr; 464 attr.bp_addr = addr; 465 err = modify_user_hw_breakpoint(bp, &attr); 466 return err; 467 } 468 469 #define PTRACE_HBP_ADDR_SZ sizeof(u64) 470 #define PTRACE_HBP_CTRL_SZ sizeof(u32) 471 #define PTRACE_HBP_PAD_SZ sizeof(u32) 472 473 static int hw_break_get(struct task_struct *target, 474 const struct user_regset *regset, 475 struct membuf to) 476 { 477 unsigned int note_type = regset->core_note_type; 478 int ret, idx = 0; 479 u32 info, ctrl; 480 u64 addr; 481 482 /* Resource info */ 483 ret = ptrace_hbp_get_resource_info(note_type, &info); 484 if (ret) 485 return ret; 486 487 membuf_write(&to, &info, sizeof(info)); 488 membuf_zero(&to, sizeof(u32)); 489 /* (address, ctrl) registers */ 490 while (to.left) { 491 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr); 492 if (ret) 493 return ret; 494 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl); 495 if (ret) 496 return ret; 497 membuf_store(&to, addr); 498 membuf_store(&to, ctrl); 499 membuf_zero(&to, sizeof(u32)); 500 idx++; 501 } 502 return 0; 503 } 504 505 static int hw_break_set(struct task_struct *target, 506 const struct user_regset *regset, 507 unsigned int pos, unsigned int count, 508 const void *kbuf, const void __user *ubuf) 509 { 510 unsigned int note_type = regset->core_note_type; 511 int ret, idx = 0, offset, limit; 512 u32 ctrl; 513 u64 addr; 514 515 /* Resource info and pad */ 516 offset = offsetof(struct user_hwdebug_state, dbg_regs); 517 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset); 518 519 /* (address, ctrl) registers */ 520 limit = regset->n * regset->size; 521 while (count && offset < limit) { 522 if (count < PTRACE_HBP_ADDR_SZ) 523 return -EINVAL; 524 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr, 525 offset, offset + PTRACE_HBP_ADDR_SZ); 526 if (ret) 527 return ret; 528 ret = ptrace_hbp_set_addr(note_type, target, idx, addr); 529 if (ret) 530 return ret; 531 offset += PTRACE_HBP_ADDR_SZ; 532 533 if (!count) 534 break; 535 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 536 offset, offset + PTRACE_HBP_CTRL_SZ); 537 if (ret) 538 return ret; 539 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl); 540 if (ret) 541 return ret; 542 offset += PTRACE_HBP_CTRL_SZ; 543 544 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 545 offset, offset + PTRACE_HBP_PAD_SZ); 546 offset += PTRACE_HBP_PAD_SZ; 547 idx++; 548 } 549 550 return 0; 551 } 552 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 553 554 static int gpr_get(struct task_struct *target, 555 const struct user_regset *regset, 556 struct membuf to) 557 { 558 struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs; 559 return membuf_write(&to, uregs, sizeof(*uregs)); 560 } 561 562 static int gpr_set(struct task_struct *target, const struct user_regset *regset, 563 unsigned int pos, unsigned int count, 564 const void *kbuf, const void __user *ubuf) 565 { 566 int ret; 567 struct user_pt_regs newregs = task_pt_regs(target)->user_regs; 568 569 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1); 570 if (ret) 571 return ret; 572 573 if (!valid_user_regs(&newregs, target)) 574 return -EINVAL; 575 576 task_pt_regs(target)->user_regs = newregs; 577 return 0; 578 } 579 580 static int fpr_active(struct task_struct *target, const struct user_regset *regset) 581 { 582 if (!system_supports_fpsimd()) 583 return -ENODEV; 584 return regset->n; 585 } 586 587 /* 588 * TODO: update fp accessors for lazy context switching (sync/flush hwstate) 589 */ 590 static int __fpr_get(struct task_struct *target, 591 const struct user_regset *regset, 592 struct membuf to) 593 { 594 struct user_fpsimd_state *uregs; 595 596 sve_sync_to_fpsimd(target); 597 598 uregs = &target->thread.uw.fpsimd_state; 599 600 return membuf_write(&to, uregs, sizeof(*uregs)); 601 } 602 603 static int fpr_get(struct task_struct *target, const struct user_regset *regset, 604 struct membuf to) 605 { 606 if (!system_supports_fpsimd()) 607 return -EINVAL; 608 609 if (target == current) 610 fpsimd_preserve_current_state(); 611 612 return __fpr_get(target, regset, to); 613 } 614 615 static int __fpr_set(struct task_struct *target, 616 const struct user_regset *regset, 617 unsigned int pos, unsigned int count, 618 const void *kbuf, const void __user *ubuf, 619 unsigned int start_pos) 620 { 621 int ret; 622 struct user_fpsimd_state newstate; 623 624 /* 625 * Ensure target->thread.uw.fpsimd_state is up to date, so that a 626 * short copyin can't resurrect stale data. 627 */ 628 sve_sync_to_fpsimd(target); 629 630 newstate = target->thread.uw.fpsimd_state; 631 632 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 633 start_pos, start_pos + sizeof(newstate)); 634 if (ret) 635 return ret; 636 637 target->thread.uw.fpsimd_state = newstate; 638 639 return ret; 640 } 641 642 static int fpr_set(struct task_struct *target, const struct user_regset *regset, 643 unsigned int pos, unsigned int count, 644 const void *kbuf, const void __user *ubuf) 645 { 646 int ret; 647 648 if (!system_supports_fpsimd()) 649 return -EINVAL; 650 651 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0); 652 if (ret) 653 return ret; 654 655 sve_sync_from_fpsimd_zeropad(target); 656 fpsimd_flush_task_state(target); 657 658 return ret; 659 } 660 661 static int tls_get(struct task_struct *target, const struct user_regset *regset, 662 struct membuf to) 663 { 664 int ret; 665 666 if (target == current) 667 tls_preserve_current_state(); 668 669 ret = membuf_store(&to, target->thread.uw.tp_value); 670 if (system_supports_tpidr2()) 671 ret = membuf_store(&to, target->thread.tpidr2_el0); 672 else 673 ret = membuf_zero(&to, sizeof(u64)); 674 675 return ret; 676 } 677 678 static int tls_set(struct task_struct *target, const struct user_regset *regset, 679 unsigned int pos, unsigned int count, 680 const void *kbuf, const void __user *ubuf) 681 { 682 int ret; 683 unsigned long tls[2]; 684 685 tls[0] = target->thread.uw.tp_value; 686 if (system_supports_tpidr2()) 687 tls[1] = target->thread.tpidr2_el0; 688 689 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, tls, 0, count); 690 if (ret) 691 return ret; 692 693 target->thread.uw.tp_value = tls[0]; 694 if (system_supports_tpidr2()) 695 target->thread.tpidr2_el0 = tls[1]; 696 697 return ret; 698 } 699 700 static int system_call_get(struct task_struct *target, 701 const struct user_regset *regset, 702 struct membuf to) 703 { 704 return membuf_store(&to, task_pt_regs(target)->syscallno); 705 } 706 707 static int system_call_set(struct task_struct *target, 708 const struct user_regset *regset, 709 unsigned int pos, unsigned int count, 710 const void *kbuf, const void __user *ubuf) 711 { 712 int syscallno = task_pt_regs(target)->syscallno; 713 int ret; 714 715 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1); 716 if (ret) 717 return ret; 718 719 task_pt_regs(target)->syscallno = syscallno; 720 return ret; 721 } 722 723 #ifdef CONFIG_ARM64_SVE 724 725 static void sve_init_header_from_task(struct user_sve_header *header, 726 struct task_struct *target, 727 enum vec_type type) 728 { 729 unsigned int vq; 730 bool active; 731 bool fpsimd_only; 732 enum vec_type task_type; 733 734 memset(header, 0, sizeof(*header)); 735 736 /* Check if the requested registers are active for the task */ 737 if (thread_sm_enabled(&target->thread)) 738 task_type = ARM64_VEC_SME; 739 else 740 task_type = ARM64_VEC_SVE; 741 active = (task_type == type); 742 743 switch (type) { 744 case ARM64_VEC_SVE: 745 if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT)) 746 header->flags |= SVE_PT_VL_INHERIT; 747 fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE); 748 break; 749 case ARM64_VEC_SME: 750 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 751 header->flags |= SVE_PT_VL_INHERIT; 752 fpsimd_only = false; 753 break; 754 default: 755 WARN_ON_ONCE(1); 756 return; 757 } 758 759 if (active) { 760 if (fpsimd_only) { 761 header->flags |= SVE_PT_REGS_FPSIMD; 762 } else { 763 header->flags |= SVE_PT_REGS_SVE; 764 } 765 } 766 767 header->vl = task_get_vl(target, type); 768 vq = sve_vq_from_vl(header->vl); 769 770 header->max_vl = vec_max_vl(type); 771 header->size = SVE_PT_SIZE(vq, header->flags); 772 header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl), 773 SVE_PT_REGS_SVE); 774 } 775 776 static unsigned int sve_size_from_header(struct user_sve_header const *header) 777 { 778 return ALIGN(header->size, SVE_VQ_BYTES); 779 } 780 781 static int sve_get_common(struct task_struct *target, 782 const struct user_regset *regset, 783 struct membuf to, 784 enum vec_type type) 785 { 786 struct user_sve_header header; 787 unsigned int vq; 788 unsigned long start, end; 789 790 /* Header */ 791 sve_init_header_from_task(&header, target, type); 792 vq = sve_vq_from_vl(header.vl); 793 794 membuf_write(&to, &header, sizeof(header)); 795 796 if (target == current) 797 fpsimd_preserve_current_state(); 798 799 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 800 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 801 802 switch ((header.flags & SVE_PT_REGS_MASK)) { 803 case SVE_PT_REGS_FPSIMD: 804 return __fpr_get(target, regset, to); 805 806 case SVE_PT_REGS_SVE: 807 start = SVE_PT_SVE_OFFSET; 808 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 809 membuf_write(&to, target->thread.sve_state, end - start); 810 811 start = end; 812 end = SVE_PT_SVE_FPSR_OFFSET(vq); 813 membuf_zero(&to, end - start); 814 815 /* 816 * Copy fpsr, and fpcr which must follow contiguously in 817 * struct fpsimd_state: 818 */ 819 start = end; 820 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 821 membuf_write(&to, &target->thread.uw.fpsimd_state.fpsr, 822 end - start); 823 824 start = end; 825 end = sve_size_from_header(&header); 826 return membuf_zero(&to, end - start); 827 828 default: 829 return 0; 830 } 831 } 832 833 static int sve_get(struct task_struct *target, 834 const struct user_regset *regset, 835 struct membuf to) 836 { 837 if (!system_supports_sve()) 838 return -EINVAL; 839 840 return sve_get_common(target, regset, to, ARM64_VEC_SVE); 841 } 842 843 static int sve_set_common(struct task_struct *target, 844 const struct user_regset *regset, 845 unsigned int pos, unsigned int count, 846 const void *kbuf, const void __user *ubuf, 847 enum vec_type type) 848 { 849 int ret; 850 struct user_sve_header header; 851 unsigned int vq; 852 unsigned long start, end; 853 854 /* Header */ 855 if (count < sizeof(header)) 856 return -EINVAL; 857 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 858 0, sizeof(header)); 859 if (ret) 860 goto out; 861 862 /* 863 * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by 864 * vec_set_vector_length(), which will also validate them for us: 865 */ 866 ret = vec_set_vector_length(target, type, header.vl, 867 ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16); 868 if (ret) 869 goto out; 870 871 /* Actual VL set may be less than the user asked for: */ 872 vq = sve_vq_from_vl(task_get_vl(target, type)); 873 874 /* Enter/exit streaming mode */ 875 if (system_supports_sme()) { 876 u64 old_svcr = target->thread.svcr; 877 878 switch (type) { 879 case ARM64_VEC_SVE: 880 target->thread.svcr &= ~SVCR_SM_MASK; 881 break; 882 case ARM64_VEC_SME: 883 target->thread.svcr |= SVCR_SM_MASK; 884 break; 885 default: 886 WARN_ON_ONCE(1); 887 return -EINVAL; 888 } 889 890 /* 891 * If we switched then invalidate any existing SVE 892 * state and ensure there's storage. 893 */ 894 if (target->thread.svcr != old_svcr) 895 sve_alloc(target, true); 896 } 897 898 /* Registers: FPSIMD-only case */ 899 900 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 901 if ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) { 902 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 903 SVE_PT_FPSIMD_OFFSET); 904 clear_tsk_thread_flag(target, TIF_SVE); 905 target->thread.fp_type = FP_STATE_FPSIMD; 906 goto out; 907 } 908 909 /* 910 * Otherwise: no registers or full SVE case. For backwards 911 * compatibility reasons we treat empty flags as SVE registers. 912 */ 913 914 /* 915 * If setting a different VL from the requested VL and there is 916 * register data, the data layout will be wrong: don't even 917 * try to set the registers in this case. 918 */ 919 if (count && vq != sve_vq_from_vl(header.vl)) { 920 ret = -EIO; 921 goto out; 922 } 923 924 sve_alloc(target, true); 925 if (!target->thread.sve_state) { 926 ret = -ENOMEM; 927 clear_tsk_thread_flag(target, TIF_SVE); 928 target->thread.fp_type = FP_STATE_FPSIMD; 929 goto out; 930 } 931 932 /* 933 * Ensure target->thread.sve_state is up to date with target's 934 * FPSIMD regs, so that a short copyin leaves trailing 935 * registers unmodified. Only enable SVE if we are 936 * configuring normal SVE, a system with streaming SVE may not 937 * have normal SVE. 938 */ 939 fpsimd_sync_to_sve(target); 940 if (type == ARM64_VEC_SVE) 941 set_tsk_thread_flag(target, TIF_SVE); 942 target->thread.fp_type = FP_STATE_SVE; 943 944 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 945 start = SVE_PT_SVE_OFFSET; 946 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 947 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 948 target->thread.sve_state, 949 start, end); 950 if (ret) 951 goto out; 952 953 start = end; 954 end = SVE_PT_SVE_FPSR_OFFSET(vq); 955 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, start, end); 956 957 /* 958 * Copy fpsr, and fpcr which must follow contiguously in 959 * struct fpsimd_state: 960 */ 961 start = end; 962 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 963 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 964 &target->thread.uw.fpsimd_state.fpsr, 965 start, end); 966 967 out: 968 fpsimd_flush_task_state(target); 969 return ret; 970 } 971 972 static int sve_set(struct task_struct *target, 973 const struct user_regset *regset, 974 unsigned int pos, unsigned int count, 975 const void *kbuf, const void __user *ubuf) 976 { 977 if (!system_supports_sve()) 978 return -EINVAL; 979 980 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 981 ARM64_VEC_SVE); 982 } 983 984 #endif /* CONFIG_ARM64_SVE */ 985 986 #ifdef CONFIG_ARM64_SME 987 988 static int ssve_get(struct task_struct *target, 989 const struct user_regset *regset, 990 struct membuf to) 991 { 992 if (!system_supports_sme()) 993 return -EINVAL; 994 995 return sve_get_common(target, regset, to, ARM64_VEC_SME); 996 } 997 998 static int ssve_set(struct task_struct *target, 999 const struct user_regset *regset, 1000 unsigned int pos, unsigned int count, 1001 const void *kbuf, const void __user *ubuf) 1002 { 1003 if (!system_supports_sme()) 1004 return -EINVAL; 1005 1006 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 1007 ARM64_VEC_SME); 1008 } 1009 1010 static int za_get(struct task_struct *target, 1011 const struct user_regset *regset, 1012 struct membuf to) 1013 { 1014 struct user_za_header header; 1015 unsigned int vq; 1016 unsigned long start, end; 1017 1018 if (!system_supports_sme()) 1019 return -EINVAL; 1020 1021 /* Header */ 1022 memset(&header, 0, sizeof(header)); 1023 1024 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 1025 header.flags |= ZA_PT_VL_INHERIT; 1026 1027 header.vl = task_get_sme_vl(target); 1028 vq = sve_vq_from_vl(header.vl); 1029 header.max_vl = sme_max_vl(); 1030 header.max_size = ZA_PT_SIZE(vq); 1031 1032 /* If ZA is not active there is only the header */ 1033 if (thread_za_enabled(&target->thread)) 1034 header.size = ZA_PT_SIZE(vq); 1035 else 1036 header.size = ZA_PT_ZA_OFFSET; 1037 1038 membuf_write(&to, &header, sizeof(header)); 1039 1040 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1041 end = ZA_PT_ZA_OFFSET; 1042 1043 if (target == current) 1044 fpsimd_preserve_current_state(); 1045 1046 /* Any register data to include? */ 1047 if (thread_za_enabled(&target->thread)) { 1048 start = end; 1049 end = ZA_PT_SIZE(vq); 1050 membuf_write(&to, target->thread.sme_state, end - start); 1051 } 1052 1053 /* Zero any trailing padding */ 1054 start = end; 1055 end = ALIGN(header.size, SVE_VQ_BYTES); 1056 return membuf_zero(&to, end - start); 1057 } 1058 1059 static int za_set(struct task_struct *target, 1060 const struct user_regset *regset, 1061 unsigned int pos, unsigned int count, 1062 const void *kbuf, const void __user *ubuf) 1063 { 1064 int ret; 1065 struct user_za_header header; 1066 unsigned int vq; 1067 unsigned long start, end; 1068 1069 if (!system_supports_sme()) 1070 return -EINVAL; 1071 1072 /* Header */ 1073 if (count < sizeof(header)) 1074 return -EINVAL; 1075 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 1076 0, sizeof(header)); 1077 if (ret) 1078 goto out; 1079 1080 /* 1081 * All current ZA_PT_* flags are consumed by 1082 * vec_set_vector_length(), which will also validate them for 1083 * us: 1084 */ 1085 ret = vec_set_vector_length(target, ARM64_VEC_SME, header.vl, 1086 ((unsigned long)header.flags) << 16); 1087 if (ret) 1088 goto out; 1089 1090 /* Actual VL set may be less than the user asked for: */ 1091 vq = sve_vq_from_vl(task_get_sme_vl(target)); 1092 1093 /* Ensure there is some SVE storage for streaming mode */ 1094 if (!target->thread.sve_state) { 1095 sve_alloc(target, false); 1096 if (!target->thread.sve_state) { 1097 ret = -ENOMEM; 1098 goto out; 1099 } 1100 } 1101 1102 /* Allocate/reinit ZA storage */ 1103 sme_alloc(target); 1104 if (!target->thread.sme_state) { 1105 ret = -ENOMEM; 1106 goto out; 1107 } 1108 1109 /* If there is no data then disable ZA */ 1110 if (!count) { 1111 target->thread.svcr &= ~SVCR_ZA_MASK; 1112 goto out; 1113 } 1114 1115 /* 1116 * If setting a different VL from the requested VL and there is 1117 * register data, the data layout will be wrong: don't even 1118 * try to set the registers in this case. 1119 */ 1120 if (vq != sve_vq_from_vl(header.vl)) { 1121 ret = -EIO; 1122 goto out; 1123 } 1124 1125 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1126 start = ZA_PT_ZA_OFFSET; 1127 end = ZA_PT_SIZE(vq); 1128 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1129 target->thread.sme_state, 1130 start, end); 1131 if (ret) 1132 goto out; 1133 1134 /* Mark ZA as active and let userspace use it */ 1135 set_tsk_thread_flag(target, TIF_SME); 1136 target->thread.svcr |= SVCR_ZA_MASK; 1137 1138 out: 1139 fpsimd_flush_task_state(target); 1140 return ret; 1141 } 1142 1143 static int zt_get(struct task_struct *target, 1144 const struct user_regset *regset, 1145 struct membuf to) 1146 { 1147 if (!system_supports_sme2()) 1148 return -EINVAL; 1149 1150 /* 1151 * If PSTATE.ZA is not set then ZT will be zeroed when it is 1152 * enabled so report the current register value as zero. 1153 */ 1154 if (thread_za_enabled(&target->thread)) 1155 membuf_write(&to, thread_zt_state(&target->thread), 1156 ZT_SIG_REG_BYTES); 1157 else 1158 membuf_zero(&to, ZT_SIG_REG_BYTES); 1159 1160 return 0; 1161 } 1162 1163 static int zt_set(struct task_struct *target, 1164 const struct user_regset *regset, 1165 unsigned int pos, unsigned int count, 1166 const void *kbuf, const void __user *ubuf) 1167 { 1168 int ret; 1169 1170 if (!system_supports_sme2()) 1171 return -EINVAL; 1172 1173 if (!thread_za_enabled(&target->thread)) { 1174 sme_alloc(target); 1175 if (!target->thread.sme_state) 1176 return -ENOMEM; 1177 } 1178 1179 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1180 thread_zt_state(&target->thread), 1181 0, ZT_SIG_REG_BYTES); 1182 if (ret == 0) 1183 target->thread.svcr |= SVCR_ZA_MASK; 1184 1185 fpsimd_flush_task_state(target); 1186 1187 return ret; 1188 } 1189 1190 #endif /* CONFIG_ARM64_SME */ 1191 1192 #ifdef CONFIG_ARM64_PTR_AUTH 1193 static int pac_mask_get(struct task_struct *target, 1194 const struct user_regset *regset, 1195 struct membuf to) 1196 { 1197 /* 1198 * The PAC bits can differ across data and instruction pointers 1199 * depending on TCR_EL1.TBID*, which we may make use of in future, so 1200 * we expose separate masks. 1201 */ 1202 unsigned long mask = ptrauth_user_pac_mask(); 1203 struct user_pac_mask uregs = { 1204 .data_mask = mask, 1205 .insn_mask = mask, 1206 }; 1207 1208 if (!system_supports_address_auth()) 1209 return -EINVAL; 1210 1211 return membuf_write(&to, &uregs, sizeof(uregs)); 1212 } 1213 1214 static int pac_enabled_keys_get(struct task_struct *target, 1215 const struct user_regset *regset, 1216 struct membuf to) 1217 { 1218 long enabled_keys = ptrauth_get_enabled_keys(target); 1219 1220 if (IS_ERR_VALUE(enabled_keys)) 1221 return enabled_keys; 1222 1223 return membuf_write(&to, &enabled_keys, sizeof(enabled_keys)); 1224 } 1225 1226 static int pac_enabled_keys_set(struct task_struct *target, 1227 const struct user_regset *regset, 1228 unsigned int pos, unsigned int count, 1229 const void *kbuf, const void __user *ubuf) 1230 { 1231 int ret; 1232 long enabled_keys = ptrauth_get_enabled_keys(target); 1233 1234 if (IS_ERR_VALUE(enabled_keys)) 1235 return enabled_keys; 1236 1237 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &enabled_keys, 0, 1238 sizeof(long)); 1239 if (ret) 1240 return ret; 1241 1242 return ptrauth_set_enabled_keys(target, PR_PAC_ENABLED_KEYS_MASK, 1243 enabled_keys); 1244 } 1245 1246 #ifdef CONFIG_CHECKPOINT_RESTORE 1247 static __uint128_t pac_key_to_user(const struct ptrauth_key *key) 1248 { 1249 return (__uint128_t)key->hi << 64 | key->lo; 1250 } 1251 1252 static struct ptrauth_key pac_key_from_user(__uint128_t ukey) 1253 { 1254 struct ptrauth_key key = { 1255 .lo = (unsigned long)ukey, 1256 .hi = (unsigned long)(ukey >> 64), 1257 }; 1258 1259 return key; 1260 } 1261 1262 static void pac_address_keys_to_user(struct user_pac_address_keys *ukeys, 1263 const struct ptrauth_keys_user *keys) 1264 { 1265 ukeys->apiakey = pac_key_to_user(&keys->apia); 1266 ukeys->apibkey = pac_key_to_user(&keys->apib); 1267 ukeys->apdakey = pac_key_to_user(&keys->apda); 1268 ukeys->apdbkey = pac_key_to_user(&keys->apdb); 1269 } 1270 1271 static void pac_address_keys_from_user(struct ptrauth_keys_user *keys, 1272 const struct user_pac_address_keys *ukeys) 1273 { 1274 keys->apia = pac_key_from_user(ukeys->apiakey); 1275 keys->apib = pac_key_from_user(ukeys->apibkey); 1276 keys->apda = pac_key_from_user(ukeys->apdakey); 1277 keys->apdb = pac_key_from_user(ukeys->apdbkey); 1278 } 1279 1280 static int pac_address_keys_get(struct task_struct *target, 1281 const struct user_regset *regset, 1282 struct membuf to) 1283 { 1284 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1285 struct user_pac_address_keys user_keys; 1286 1287 if (!system_supports_address_auth()) 1288 return -EINVAL; 1289 1290 pac_address_keys_to_user(&user_keys, keys); 1291 1292 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1293 } 1294 1295 static int pac_address_keys_set(struct task_struct *target, 1296 const struct user_regset *regset, 1297 unsigned int pos, unsigned int count, 1298 const void *kbuf, const void __user *ubuf) 1299 { 1300 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1301 struct user_pac_address_keys user_keys; 1302 int ret; 1303 1304 if (!system_supports_address_auth()) 1305 return -EINVAL; 1306 1307 pac_address_keys_to_user(&user_keys, keys); 1308 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1309 &user_keys, 0, -1); 1310 if (ret) 1311 return ret; 1312 pac_address_keys_from_user(keys, &user_keys); 1313 1314 return 0; 1315 } 1316 1317 static void pac_generic_keys_to_user(struct user_pac_generic_keys *ukeys, 1318 const struct ptrauth_keys_user *keys) 1319 { 1320 ukeys->apgakey = pac_key_to_user(&keys->apga); 1321 } 1322 1323 static void pac_generic_keys_from_user(struct ptrauth_keys_user *keys, 1324 const struct user_pac_generic_keys *ukeys) 1325 { 1326 keys->apga = pac_key_from_user(ukeys->apgakey); 1327 } 1328 1329 static int pac_generic_keys_get(struct task_struct *target, 1330 const struct user_regset *regset, 1331 struct membuf to) 1332 { 1333 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1334 struct user_pac_generic_keys user_keys; 1335 1336 if (!system_supports_generic_auth()) 1337 return -EINVAL; 1338 1339 pac_generic_keys_to_user(&user_keys, keys); 1340 1341 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1342 } 1343 1344 static int pac_generic_keys_set(struct task_struct *target, 1345 const struct user_regset *regset, 1346 unsigned int pos, unsigned int count, 1347 const void *kbuf, const void __user *ubuf) 1348 { 1349 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1350 struct user_pac_generic_keys user_keys; 1351 int ret; 1352 1353 if (!system_supports_generic_auth()) 1354 return -EINVAL; 1355 1356 pac_generic_keys_to_user(&user_keys, keys); 1357 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1358 &user_keys, 0, -1); 1359 if (ret) 1360 return ret; 1361 pac_generic_keys_from_user(keys, &user_keys); 1362 1363 return 0; 1364 } 1365 #endif /* CONFIG_CHECKPOINT_RESTORE */ 1366 #endif /* CONFIG_ARM64_PTR_AUTH */ 1367 1368 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1369 static int tagged_addr_ctrl_get(struct task_struct *target, 1370 const struct user_regset *regset, 1371 struct membuf to) 1372 { 1373 long ctrl = get_tagged_addr_ctrl(target); 1374 1375 if (IS_ERR_VALUE(ctrl)) 1376 return ctrl; 1377 1378 return membuf_write(&to, &ctrl, sizeof(ctrl)); 1379 } 1380 1381 static int tagged_addr_ctrl_set(struct task_struct *target, const struct 1382 user_regset *regset, unsigned int pos, 1383 unsigned int count, const void *kbuf, const 1384 void __user *ubuf) 1385 { 1386 int ret; 1387 long ctrl; 1388 1389 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); 1390 if (ret) 1391 return ret; 1392 1393 return set_tagged_addr_ctrl(target, ctrl); 1394 } 1395 #endif 1396 1397 enum aarch64_regset { 1398 REGSET_GPR, 1399 REGSET_FPR, 1400 REGSET_TLS, 1401 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1402 REGSET_HW_BREAK, 1403 REGSET_HW_WATCH, 1404 #endif 1405 REGSET_SYSTEM_CALL, 1406 #ifdef CONFIG_ARM64_SVE 1407 REGSET_SVE, 1408 #endif 1409 #ifdef CONFIG_ARM64_SME 1410 REGSET_SSVE, 1411 REGSET_ZA, 1412 REGSET_ZT, 1413 #endif 1414 #ifdef CONFIG_ARM64_PTR_AUTH 1415 REGSET_PAC_MASK, 1416 REGSET_PAC_ENABLED_KEYS, 1417 #ifdef CONFIG_CHECKPOINT_RESTORE 1418 REGSET_PACA_KEYS, 1419 REGSET_PACG_KEYS, 1420 #endif 1421 #endif 1422 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1423 REGSET_TAGGED_ADDR_CTRL, 1424 #endif 1425 }; 1426 1427 static const struct user_regset aarch64_regsets[] = { 1428 [REGSET_GPR] = { 1429 .core_note_type = NT_PRSTATUS, 1430 .n = sizeof(struct user_pt_regs) / sizeof(u64), 1431 .size = sizeof(u64), 1432 .align = sizeof(u64), 1433 .regset_get = gpr_get, 1434 .set = gpr_set 1435 }, 1436 [REGSET_FPR] = { 1437 .core_note_type = NT_PRFPREG, 1438 .n = sizeof(struct user_fpsimd_state) / sizeof(u32), 1439 /* 1440 * We pretend we have 32-bit registers because the fpsr and 1441 * fpcr are 32-bits wide. 1442 */ 1443 .size = sizeof(u32), 1444 .align = sizeof(u32), 1445 .active = fpr_active, 1446 .regset_get = fpr_get, 1447 .set = fpr_set 1448 }, 1449 [REGSET_TLS] = { 1450 .core_note_type = NT_ARM_TLS, 1451 .n = 2, 1452 .size = sizeof(void *), 1453 .align = sizeof(void *), 1454 .regset_get = tls_get, 1455 .set = tls_set, 1456 }, 1457 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1458 [REGSET_HW_BREAK] = { 1459 .core_note_type = NT_ARM_HW_BREAK, 1460 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1461 .size = sizeof(u32), 1462 .align = sizeof(u32), 1463 .regset_get = hw_break_get, 1464 .set = hw_break_set, 1465 }, 1466 [REGSET_HW_WATCH] = { 1467 .core_note_type = NT_ARM_HW_WATCH, 1468 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1469 .size = sizeof(u32), 1470 .align = sizeof(u32), 1471 .regset_get = hw_break_get, 1472 .set = hw_break_set, 1473 }, 1474 #endif 1475 [REGSET_SYSTEM_CALL] = { 1476 .core_note_type = NT_ARM_SYSTEM_CALL, 1477 .n = 1, 1478 .size = sizeof(int), 1479 .align = sizeof(int), 1480 .regset_get = system_call_get, 1481 .set = system_call_set, 1482 }, 1483 #ifdef CONFIG_ARM64_SVE 1484 [REGSET_SVE] = { /* Scalable Vector Extension */ 1485 .core_note_type = NT_ARM_SVE, 1486 .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE), 1487 SVE_VQ_BYTES), 1488 .size = SVE_VQ_BYTES, 1489 .align = SVE_VQ_BYTES, 1490 .regset_get = sve_get, 1491 .set = sve_set, 1492 }, 1493 #endif 1494 #ifdef CONFIG_ARM64_SME 1495 [REGSET_SSVE] = { /* Streaming mode SVE */ 1496 .core_note_type = NT_ARM_SSVE, 1497 .n = DIV_ROUND_UP(SVE_PT_SIZE(SME_VQ_MAX, SVE_PT_REGS_SVE), 1498 SVE_VQ_BYTES), 1499 .size = SVE_VQ_BYTES, 1500 .align = SVE_VQ_BYTES, 1501 .regset_get = ssve_get, 1502 .set = ssve_set, 1503 }, 1504 [REGSET_ZA] = { /* SME ZA */ 1505 .core_note_type = NT_ARM_ZA, 1506 /* 1507 * ZA is a single register but it's variably sized and 1508 * the ptrace core requires that the size of any data 1509 * be an exact multiple of the configured register 1510 * size so report as though we had SVE_VQ_BYTES 1511 * registers. These values aren't exposed to 1512 * userspace. 1513 */ 1514 .n = DIV_ROUND_UP(ZA_PT_SIZE(SME_VQ_MAX), SVE_VQ_BYTES), 1515 .size = SVE_VQ_BYTES, 1516 .align = SVE_VQ_BYTES, 1517 .regset_get = za_get, 1518 .set = za_set, 1519 }, 1520 [REGSET_ZT] = { /* SME ZT */ 1521 .core_note_type = NT_ARM_ZT, 1522 .n = 1, 1523 .size = ZT_SIG_REG_BYTES, 1524 .align = sizeof(u64), 1525 .regset_get = zt_get, 1526 .set = zt_set, 1527 }, 1528 #endif 1529 #ifdef CONFIG_ARM64_PTR_AUTH 1530 [REGSET_PAC_MASK] = { 1531 .core_note_type = NT_ARM_PAC_MASK, 1532 .n = sizeof(struct user_pac_mask) / sizeof(u64), 1533 .size = sizeof(u64), 1534 .align = sizeof(u64), 1535 .regset_get = pac_mask_get, 1536 /* this cannot be set dynamically */ 1537 }, 1538 [REGSET_PAC_ENABLED_KEYS] = { 1539 .core_note_type = NT_ARM_PAC_ENABLED_KEYS, 1540 .n = 1, 1541 .size = sizeof(long), 1542 .align = sizeof(long), 1543 .regset_get = pac_enabled_keys_get, 1544 .set = pac_enabled_keys_set, 1545 }, 1546 #ifdef CONFIG_CHECKPOINT_RESTORE 1547 [REGSET_PACA_KEYS] = { 1548 .core_note_type = NT_ARM_PACA_KEYS, 1549 .n = sizeof(struct user_pac_address_keys) / sizeof(__uint128_t), 1550 .size = sizeof(__uint128_t), 1551 .align = sizeof(__uint128_t), 1552 .regset_get = pac_address_keys_get, 1553 .set = pac_address_keys_set, 1554 }, 1555 [REGSET_PACG_KEYS] = { 1556 .core_note_type = NT_ARM_PACG_KEYS, 1557 .n = sizeof(struct user_pac_generic_keys) / sizeof(__uint128_t), 1558 .size = sizeof(__uint128_t), 1559 .align = sizeof(__uint128_t), 1560 .regset_get = pac_generic_keys_get, 1561 .set = pac_generic_keys_set, 1562 }, 1563 #endif 1564 #endif 1565 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1566 [REGSET_TAGGED_ADDR_CTRL] = { 1567 .core_note_type = NT_ARM_TAGGED_ADDR_CTRL, 1568 .n = 1, 1569 .size = sizeof(long), 1570 .align = sizeof(long), 1571 .regset_get = tagged_addr_ctrl_get, 1572 .set = tagged_addr_ctrl_set, 1573 }, 1574 #endif 1575 }; 1576 1577 static const struct user_regset_view user_aarch64_view = { 1578 .name = "aarch64", .e_machine = EM_AARCH64, 1579 .regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets) 1580 }; 1581 1582 #ifdef CONFIG_COMPAT 1583 enum compat_regset { 1584 REGSET_COMPAT_GPR, 1585 REGSET_COMPAT_VFP, 1586 }; 1587 1588 static inline compat_ulong_t compat_get_user_reg(struct task_struct *task, int idx) 1589 { 1590 struct pt_regs *regs = task_pt_regs(task); 1591 1592 switch (idx) { 1593 case 15: 1594 return regs->pc; 1595 case 16: 1596 return pstate_to_compat_psr(regs->pstate); 1597 case 17: 1598 return regs->orig_x0; 1599 default: 1600 return regs->regs[idx]; 1601 } 1602 } 1603 1604 static int compat_gpr_get(struct task_struct *target, 1605 const struct user_regset *regset, 1606 struct membuf to) 1607 { 1608 int i = 0; 1609 1610 while (to.left) 1611 membuf_store(&to, compat_get_user_reg(target, i++)); 1612 return 0; 1613 } 1614 1615 static int compat_gpr_set(struct task_struct *target, 1616 const struct user_regset *regset, 1617 unsigned int pos, unsigned int count, 1618 const void *kbuf, const void __user *ubuf) 1619 { 1620 struct pt_regs newregs; 1621 int ret = 0; 1622 unsigned int i, start, num_regs; 1623 1624 /* Calculate the number of AArch32 registers contained in count */ 1625 num_regs = count / regset->size; 1626 1627 /* Convert pos into an register number */ 1628 start = pos / regset->size; 1629 1630 if (start + num_regs > regset->n) 1631 return -EIO; 1632 1633 newregs = *task_pt_regs(target); 1634 1635 for (i = 0; i < num_regs; ++i) { 1636 unsigned int idx = start + i; 1637 compat_ulong_t reg; 1638 1639 if (kbuf) { 1640 memcpy(®, kbuf, sizeof(reg)); 1641 kbuf += sizeof(reg); 1642 } else { 1643 ret = copy_from_user(®, ubuf, sizeof(reg)); 1644 if (ret) { 1645 ret = -EFAULT; 1646 break; 1647 } 1648 1649 ubuf += sizeof(reg); 1650 } 1651 1652 switch (idx) { 1653 case 15: 1654 newregs.pc = reg; 1655 break; 1656 case 16: 1657 reg = compat_psr_to_pstate(reg); 1658 newregs.pstate = reg; 1659 break; 1660 case 17: 1661 newregs.orig_x0 = reg; 1662 break; 1663 default: 1664 newregs.regs[idx] = reg; 1665 } 1666 1667 } 1668 1669 if (valid_user_regs(&newregs.user_regs, target)) 1670 *task_pt_regs(target) = newregs; 1671 else 1672 ret = -EINVAL; 1673 1674 return ret; 1675 } 1676 1677 static int compat_vfp_get(struct task_struct *target, 1678 const struct user_regset *regset, 1679 struct membuf to) 1680 { 1681 struct user_fpsimd_state *uregs; 1682 compat_ulong_t fpscr; 1683 1684 if (!system_supports_fpsimd()) 1685 return -EINVAL; 1686 1687 uregs = &target->thread.uw.fpsimd_state; 1688 1689 if (target == current) 1690 fpsimd_preserve_current_state(); 1691 1692 /* 1693 * The VFP registers are packed into the fpsimd_state, so they all sit 1694 * nicely together for us. We just need to create the fpscr separately. 1695 */ 1696 membuf_write(&to, uregs, VFP_STATE_SIZE - sizeof(compat_ulong_t)); 1697 fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) | 1698 (uregs->fpcr & VFP_FPSCR_CTRL_MASK); 1699 return membuf_store(&to, fpscr); 1700 } 1701 1702 static int compat_vfp_set(struct task_struct *target, 1703 const struct user_regset *regset, 1704 unsigned int pos, unsigned int count, 1705 const void *kbuf, const void __user *ubuf) 1706 { 1707 struct user_fpsimd_state *uregs; 1708 compat_ulong_t fpscr; 1709 int ret, vregs_end_pos; 1710 1711 if (!system_supports_fpsimd()) 1712 return -EINVAL; 1713 1714 uregs = &target->thread.uw.fpsimd_state; 1715 1716 vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t); 1717 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 1718 vregs_end_pos); 1719 1720 if (count && !ret) { 1721 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpscr, 1722 vregs_end_pos, VFP_STATE_SIZE); 1723 if (!ret) { 1724 uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK; 1725 uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK; 1726 } 1727 } 1728 1729 fpsimd_flush_task_state(target); 1730 return ret; 1731 } 1732 1733 static int compat_tls_get(struct task_struct *target, 1734 const struct user_regset *regset, 1735 struct membuf to) 1736 { 1737 return membuf_store(&to, (compat_ulong_t)target->thread.uw.tp_value); 1738 } 1739 1740 static int compat_tls_set(struct task_struct *target, 1741 const struct user_regset *regset, unsigned int pos, 1742 unsigned int count, const void *kbuf, 1743 const void __user *ubuf) 1744 { 1745 int ret; 1746 compat_ulong_t tls = target->thread.uw.tp_value; 1747 1748 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1); 1749 if (ret) 1750 return ret; 1751 1752 target->thread.uw.tp_value = tls; 1753 return ret; 1754 } 1755 1756 static const struct user_regset aarch32_regsets[] = { 1757 [REGSET_COMPAT_GPR] = { 1758 .core_note_type = NT_PRSTATUS, 1759 .n = COMPAT_ELF_NGREG, 1760 .size = sizeof(compat_elf_greg_t), 1761 .align = sizeof(compat_elf_greg_t), 1762 .regset_get = compat_gpr_get, 1763 .set = compat_gpr_set 1764 }, 1765 [REGSET_COMPAT_VFP] = { 1766 .core_note_type = NT_ARM_VFP, 1767 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1768 .size = sizeof(compat_ulong_t), 1769 .align = sizeof(compat_ulong_t), 1770 .active = fpr_active, 1771 .regset_get = compat_vfp_get, 1772 .set = compat_vfp_set 1773 }, 1774 }; 1775 1776 static const struct user_regset_view user_aarch32_view = { 1777 .name = "aarch32", .e_machine = EM_ARM, 1778 .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets) 1779 }; 1780 1781 static const struct user_regset aarch32_ptrace_regsets[] = { 1782 [REGSET_GPR] = { 1783 .core_note_type = NT_PRSTATUS, 1784 .n = COMPAT_ELF_NGREG, 1785 .size = sizeof(compat_elf_greg_t), 1786 .align = sizeof(compat_elf_greg_t), 1787 .regset_get = compat_gpr_get, 1788 .set = compat_gpr_set 1789 }, 1790 [REGSET_FPR] = { 1791 .core_note_type = NT_ARM_VFP, 1792 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1793 .size = sizeof(compat_ulong_t), 1794 .align = sizeof(compat_ulong_t), 1795 .regset_get = compat_vfp_get, 1796 .set = compat_vfp_set 1797 }, 1798 [REGSET_TLS] = { 1799 .core_note_type = NT_ARM_TLS, 1800 .n = 1, 1801 .size = sizeof(compat_ulong_t), 1802 .align = sizeof(compat_ulong_t), 1803 .regset_get = compat_tls_get, 1804 .set = compat_tls_set, 1805 }, 1806 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1807 [REGSET_HW_BREAK] = { 1808 .core_note_type = NT_ARM_HW_BREAK, 1809 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1810 .size = sizeof(u32), 1811 .align = sizeof(u32), 1812 .regset_get = hw_break_get, 1813 .set = hw_break_set, 1814 }, 1815 [REGSET_HW_WATCH] = { 1816 .core_note_type = NT_ARM_HW_WATCH, 1817 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1818 .size = sizeof(u32), 1819 .align = sizeof(u32), 1820 .regset_get = hw_break_get, 1821 .set = hw_break_set, 1822 }, 1823 #endif 1824 [REGSET_SYSTEM_CALL] = { 1825 .core_note_type = NT_ARM_SYSTEM_CALL, 1826 .n = 1, 1827 .size = sizeof(int), 1828 .align = sizeof(int), 1829 .regset_get = system_call_get, 1830 .set = system_call_set, 1831 }, 1832 }; 1833 1834 static const struct user_regset_view user_aarch32_ptrace_view = { 1835 .name = "aarch32", .e_machine = EM_ARM, 1836 .regsets = aarch32_ptrace_regsets, .n = ARRAY_SIZE(aarch32_ptrace_regsets) 1837 }; 1838 1839 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off, 1840 compat_ulong_t __user *ret) 1841 { 1842 compat_ulong_t tmp; 1843 1844 if (off & 3) 1845 return -EIO; 1846 1847 if (off == COMPAT_PT_TEXT_ADDR) 1848 tmp = tsk->mm->start_code; 1849 else if (off == COMPAT_PT_DATA_ADDR) 1850 tmp = tsk->mm->start_data; 1851 else if (off == COMPAT_PT_TEXT_END_ADDR) 1852 tmp = tsk->mm->end_code; 1853 else if (off < sizeof(compat_elf_gregset_t)) 1854 tmp = compat_get_user_reg(tsk, off >> 2); 1855 else if (off >= COMPAT_USER_SZ) 1856 return -EIO; 1857 else 1858 tmp = 0; 1859 1860 return put_user(tmp, ret); 1861 } 1862 1863 static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off, 1864 compat_ulong_t val) 1865 { 1866 struct pt_regs newregs = *task_pt_regs(tsk); 1867 unsigned int idx = off / 4; 1868 1869 if (off & 3 || off >= COMPAT_USER_SZ) 1870 return -EIO; 1871 1872 if (off >= sizeof(compat_elf_gregset_t)) 1873 return 0; 1874 1875 switch (idx) { 1876 case 15: 1877 newregs.pc = val; 1878 break; 1879 case 16: 1880 newregs.pstate = compat_psr_to_pstate(val); 1881 break; 1882 case 17: 1883 newregs.orig_x0 = val; 1884 break; 1885 default: 1886 newregs.regs[idx] = val; 1887 } 1888 1889 if (!valid_user_regs(&newregs.user_regs, tsk)) 1890 return -EINVAL; 1891 1892 *task_pt_regs(tsk) = newregs; 1893 return 0; 1894 } 1895 1896 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1897 1898 /* 1899 * Convert a virtual register number into an index for a thread_info 1900 * breakpoint array. Breakpoints are identified using positive numbers 1901 * whilst watchpoints are negative. The registers are laid out as pairs 1902 * of (address, control), each pair mapping to a unique hw_breakpoint struct. 1903 * Register 0 is reserved for describing resource information. 1904 */ 1905 static int compat_ptrace_hbp_num_to_idx(compat_long_t num) 1906 { 1907 return (abs(num) - 1) >> 1; 1908 } 1909 1910 static int compat_ptrace_hbp_get_resource_info(u32 *kdata) 1911 { 1912 u8 num_brps, num_wrps, debug_arch, wp_len; 1913 u32 reg = 0; 1914 1915 num_brps = hw_breakpoint_slots(TYPE_INST); 1916 num_wrps = hw_breakpoint_slots(TYPE_DATA); 1917 1918 debug_arch = debug_monitors_arch(); 1919 wp_len = 8; 1920 reg |= debug_arch; 1921 reg <<= 8; 1922 reg |= wp_len; 1923 reg <<= 8; 1924 reg |= num_wrps; 1925 reg <<= 8; 1926 reg |= num_brps; 1927 1928 *kdata = reg; 1929 return 0; 1930 } 1931 1932 static int compat_ptrace_hbp_get(unsigned int note_type, 1933 struct task_struct *tsk, 1934 compat_long_t num, 1935 u32 *kdata) 1936 { 1937 u64 addr = 0; 1938 u32 ctrl = 0; 1939 1940 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1941 1942 if (num & 1) { 1943 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr); 1944 *kdata = (u32)addr; 1945 } else { 1946 err = ptrace_hbp_get_ctrl(note_type, tsk, idx, &ctrl); 1947 *kdata = ctrl; 1948 } 1949 1950 return err; 1951 } 1952 1953 static int compat_ptrace_hbp_set(unsigned int note_type, 1954 struct task_struct *tsk, 1955 compat_long_t num, 1956 u32 *kdata) 1957 { 1958 u64 addr; 1959 u32 ctrl; 1960 1961 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1962 1963 if (num & 1) { 1964 addr = *kdata; 1965 err = ptrace_hbp_set_addr(note_type, tsk, idx, addr); 1966 } else { 1967 ctrl = *kdata; 1968 err = ptrace_hbp_set_ctrl(note_type, tsk, idx, ctrl); 1969 } 1970 1971 return err; 1972 } 1973 1974 static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num, 1975 compat_ulong_t __user *data) 1976 { 1977 int ret; 1978 u32 kdata; 1979 1980 /* Watchpoint */ 1981 if (num < 0) { 1982 ret = compat_ptrace_hbp_get(NT_ARM_HW_WATCH, tsk, num, &kdata); 1983 /* Resource info */ 1984 } else if (num == 0) { 1985 ret = compat_ptrace_hbp_get_resource_info(&kdata); 1986 /* Breakpoint */ 1987 } else { 1988 ret = compat_ptrace_hbp_get(NT_ARM_HW_BREAK, tsk, num, &kdata); 1989 } 1990 1991 if (!ret) 1992 ret = put_user(kdata, data); 1993 1994 return ret; 1995 } 1996 1997 static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num, 1998 compat_ulong_t __user *data) 1999 { 2000 int ret; 2001 u32 kdata = 0; 2002 2003 if (num == 0) 2004 return 0; 2005 2006 ret = get_user(kdata, data); 2007 if (ret) 2008 return ret; 2009 2010 if (num < 0) 2011 ret = compat_ptrace_hbp_set(NT_ARM_HW_WATCH, tsk, num, &kdata); 2012 else 2013 ret = compat_ptrace_hbp_set(NT_ARM_HW_BREAK, tsk, num, &kdata); 2014 2015 return ret; 2016 } 2017 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 2018 2019 long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 2020 compat_ulong_t caddr, compat_ulong_t cdata) 2021 { 2022 unsigned long addr = caddr; 2023 unsigned long data = cdata; 2024 void __user *datap = compat_ptr(data); 2025 int ret; 2026 2027 switch (request) { 2028 case PTRACE_PEEKUSR: 2029 ret = compat_ptrace_read_user(child, addr, datap); 2030 break; 2031 2032 case PTRACE_POKEUSR: 2033 ret = compat_ptrace_write_user(child, addr, data); 2034 break; 2035 2036 case COMPAT_PTRACE_GETREGS: 2037 ret = copy_regset_to_user(child, 2038 &user_aarch32_view, 2039 REGSET_COMPAT_GPR, 2040 0, sizeof(compat_elf_gregset_t), 2041 datap); 2042 break; 2043 2044 case COMPAT_PTRACE_SETREGS: 2045 ret = copy_regset_from_user(child, 2046 &user_aarch32_view, 2047 REGSET_COMPAT_GPR, 2048 0, sizeof(compat_elf_gregset_t), 2049 datap); 2050 break; 2051 2052 case COMPAT_PTRACE_GET_THREAD_AREA: 2053 ret = put_user((compat_ulong_t)child->thread.uw.tp_value, 2054 (compat_ulong_t __user *)datap); 2055 break; 2056 2057 case COMPAT_PTRACE_SET_SYSCALL: 2058 task_pt_regs(child)->syscallno = data; 2059 ret = 0; 2060 break; 2061 2062 case COMPAT_PTRACE_GETVFPREGS: 2063 ret = copy_regset_to_user(child, 2064 &user_aarch32_view, 2065 REGSET_COMPAT_VFP, 2066 0, VFP_STATE_SIZE, 2067 datap); 2068 break; 2069 2070 case COMPAT_PTRACE_SETVFPREGS: 2071 ret = copy_regset_from_user(child, 2072 &user_aarch32_view, 2073 REGSET_COMPAT_VFP, 2074 0, VFP_STATE_SIZE, 2075 datap); 2076 break; 2077 2078 #ifdef CONFIG_HAVE_HW_BREAKPOINT 2079 case COMPAT_PTRACE_GETHBPREGS: 2080 ret = compat_ptrace_gethbpregs(child, addr, datap); 2081 break; 2082 2083 case COMPAT_PTRACE_SETHBPREGS: 2084 ret = compat_ptrace_sethbpregs(child, addr, datap); 2085 break; 2086 #endif 2087 2088 default: 2089 ret = compat_ptrace_request(child, request, addr, 2090 data); 2091 break; 2092 } 2093 2094 return ret; 2095 } 2096 #endif /* CONFIG_COMPAT */ 2097 2098 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 2099 { 2100 #ifdef CONFIG_COMPAT 2101 /* 2102 * Core dumping of 32-bit tasks or compat ptrace requests must use the 2103 * user_aarch32_view compatible with arm32. Native ptrace requests on 2104 * 32-bit children use an extended user_aarch32_ptrace_view to allow 2105 * access to the TLS register. 2106 */ 2107 if (is_compat_task()) 2108 return &user_aarch32_view; 2109 else if (is_compat_thread(task_thread_info(task))) 2110 return &user_aarch32_ptrace_view; 2111 #endif 2112 return &user_aarch64_view; 2113 } 2114 2115 long arch_ptrace(struct task_struct *child, long request, 2116 unsigned long addr, unsigned long data) 2117 { 2118 switch (request) { 2119 case PTRACE_PEEKMTETAGS: 2120 case PTRACE_POKEMTETAGS: 2121 return mte_ptrace_copy_tags(child, request, addr, data); 2122 } 2123 2124 return ptrace_request(child, request, addr, data); 2125 } 2126 2127 enum ptrace_syscall_dir { 2128 PTRACE_SYSCALL_ENTER = 0, 2129 PTRACE_SYSCALL_EXIT, 2130 }; 2131 2132 static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir) 2133 { 2134 int regno; 2135 unsigned long saved_reg; 2136 2137 /* 2138 * We have some ABI weirdness here in the way that we handle syscall 2139 * exit stops because we indicate whether or not the stop has been 2140 * signalled from syscall entry or syscall exit by clobbering a general 2141 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee 2142 * and restoring its old value after the stop. This means that: 2143 * 2144 * - Any writes by the tracer to this register during the stop are 2145 * ignored/discarded. 2146 * 2147 * - The actual value of the register is not available during the stop, 2148 * so the tracer cannot save it and restore it later. 2149 * 2150 * - Syscall stops behave differently to seccomp and pseudo-step traps 2151 * (the latter do not nobble any registers). 2152 */ 2153 regno = (is_compat_task() ? 12 : 7); 2154 saved_reg = regs->regs[regno]; 2155 regs->regs[regno] = dir; 2156 2157 if (dir == PTRACE_SYSCALL_ENTER) { 2158 if (ptrace_report_syscall_entry(regs)) 2159 forget_syscall(regs); 2160 regs->regs[regno] = saved_reg; 2161 } else if (!test_thread_flag(TIF_SINGLESTEP)) { 2162 ptrace_report_syscall_exit(regs, 0); 2163 regs->regs[regno] = saved_reg; 2164 } else { 2165 regs->regs[regno] = saved_reg; 2166 2167 /* 2168 * Signal a pseudo-step exception since we are stepping but 2169 * tracer modifications to the registers may have rewound the 2170 * state machine. 2171 */ 2172 ptrace_report_syscall_exit(regs, 1); 2173 } 2174 } 2175 2176 int syscall_trace_enter(struct pt_regs *regs) 2177 { 2178 unsigned long flags = read_thread_flags(); 2179 2180 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { 2181 report_syscall(regs, PTRACE_SYSCALL_ENTER); 2182 if (flags & _TIF_SYSCALL_EMU) 2183 return NO_SYSCALL; 2184 } 2185 2186 /* Do the secure computing after ptrace; failures should be fast. */ 2187 if (secure_computing() == -1) 2188 return NO_SYSCALL; 2189 2190 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) 2191 trace_sys_enter(regs, regs->syscallno); 2192 2193 audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1], 2194 regs->regs[2], regs->regs[3]); 2195 2196 return regs->syscallno; 2197 } 2198 2199 void syscall_trace_exit(struct pt_regs *regs) 2200 { 2201 unsigned long flags = read_thread_flags(); 2202 2203 audit_syscall_exit(regs); 2204 2205 if (flags & _TIF_SYSCALL_TRACEPOINT) 2206 trace_sys_exit(regs, syscall_get_return_value(current, regs)); 2207 2208 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) 2209 report_syscall(regs, PTRACE_SYSCALL_EXIT); 2210 2211 rseq_syscall(regs); 2212 } 2213 2214 /* 2215 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. 2216 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is 2217 * not described in ARM DDI 0487D.a. 2218 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may 2219 * be allocated an EL0 meaning in future. 2220 * Userspace cannot use these until they have an architectural meaning. 2221 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format. 2222 * We also reserve IL for the kernel; SS is handled dynamically. 2223 */ 2224 #define SPSR_EL1_AARCH64_RES0_BITS \ 2225 (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \ 2226 GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5)) 2227 #define SPSR_EL1_AARCH32_RES0_BITS \ 2228 (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) 2229 2230 static int valid_compat_regs(struct user_pt_regs *regs) 2231 { 2232 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; 2233 2234 if (!system_supports_mixed_endian_el0()) { 2235 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 2236 regs->pstate |= PSR_AA32_E_BIT; 2237 else 2238 regs->pstate &= ~PSR_AA32_E_BIT; 2239 } 2240 2241 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && 2242 (regs->pstate & PSR_AA32_A_BIT) == 0 && 2243 (regs->pstate & PSR_AA32_I_BIT) == 0 && 2244 (regs->pstate & PSR_AA32_F_BIT) == 0) { 2245 return 1; 2246 } 2247 2248 /* 2249 * Force PSR to a valid 32-bit EL0t, preserving the same bits as 2250 * arch/arm. 2251 */ 2252 regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT | 2253 PSR_AA32_C_BIT | PSR_AA32_V_BIT | 2254 PSR_AA32_Q_BIT | PSR_AA32_IT_MASK | 2255 PSR_AA32_GE_MASK | PSR_AA32_E_BIT | 2256 PSR_AA32_T_BIT; 2257 regs->pstate |= PSR_MODE32_BIT; 2258 2259 return 0; 2260 } 2261 2262 static int valid_native_regs(struct user_pt_regs *regs) 2263 { 2264 regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; 2265 2266 if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) && 2267 (regs->pstate & PSR_D_BIT) == 0 && 2268 (regs->pstate & PSR_A_BIT) == 0 && 2269 (regs->pstate & PSR_I_BIT) == 0 && 2270 (regs->pstate & PSR_F_BIT) == 0) { 2271 return 1; 2272 } 2273 2274 /* Force PSR to a valid 64-bit EL0t */ 2275 regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; 2276 2277 return 0; 2278 } 2279 2280 /* 2281 * Are the current registers suitable for user mode? (used to maintain 2282 * security in signal handlers) 2283 */ 2284 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task) 2285 { 2286 /* https://lore.kernel.org/lkml/20191118131525.GA4180@willie-the-truck */ 2287 user_regs_reset_single_step(regs, task); 2288 2289 if (is_compat_thread(task_thread_info(task))) 2290 return valid_compat_regs(regs); 2291 else 2292 return valid_native_regs(regs); 2293 } 2294