1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/ptrace.c 4 * 5 * By Ross Biro 1/23/92 6 * edited by Linus Torvalds 7 * ARM modifications Copyright (C) 2000 Russell King 8 * Copyright (C) 2012 ARM Ltd. 9 */ 10 11 #include <linux/audit.h> 12 #include <linux/compat.h> 13 #include <linux/kernel.h> 14 #include <linux/sched/signal.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/mm.h> 17 #include <linux/nospec.h> 18 #include <linux/smp.h> 19 #include <linux/ptrace.h> 20 #include <linux/user.h> 21 #include <linux/seccomp.h> 22 #include <linux/security.h> 23 #include <linux/init.h> 24 #include <linux/signal.h> 25 #include <linux/string.h> 26 #include <linux/uaccess.h> 27 #include <linux/perf_event.h> 28 #include <linux/hw_breakpoint.h> 29 #include <linux/regset.h> 30 #include <linux/elf.h> 31 32 #include <asm/compat.h> 33 #include <asm/cpufeature.h> 34 #include <asm/debug-monitors.h> 35 #include <asm/fpsimd.h> 36 #include <asm/mte.h> 37 #include <asm/pointer_auth.h> 38 #include <asm/stacktrace.h> 39 #include <asm/syscall.h> 40 #include <asm/traps.h> 41 #include <asm/system_misc.h> 42 43 #define CREATE_TRACE_POINTS 44 #include <trace/events/syscalls.h> 45 46 struct pt_regs_offset { 47 const char *name; 48 int offset; 49 }; 50 51 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 52 #define REG_OFFSET_END {.name = NULL, .offset = 0} 53 #define GPR_OFFSET_NAME(r) \ 54 {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])} 55 56 static const struct pt_regs_offset regoffset_table[] = { 57 GPR_OFFSET_NAME(0), 58 GPR_OFFSET_NAME(1), 59 GPR_OFFSET_NAME(2), 60 GPR_OFFSET_NAME(3), 61 GPR_OFFSET_NAME(4), 62 GPR_OFFSET_NAME(5), 63 GPR_OFFSET_NAME(6), 64 GPR_OFFSET_NAME(7), 65 GPR_OFFSET_NAME(8), 66 GPR_OFFSET_NAME(9), 67 GPR_OFFSET_NAME(10), 68 GPR_OFFSET_NAME(11), 69 GPR_OFFSET_NAME(12), 70 GPR_OFFSET_NAME(13), 71 GPR_OFFSET_NAME(14), 72 GPR_OFFSET_NAME(15), 73 GPR_OFFSET_NAME(16), 74 GPR_OFFSET_NAME(17), 75 GPR_OFFSET_NAME(18), 76 GPR_OFFSET_NAME(19), 77 GPR_OFFSET_NAME(20), 78 GPR_OFFSET_NAME(21), 79 GPR_OFFSET_NAME(22), 80 GPR_OFFSET_NAME(23), 81 GPR_OFFSET_NAME(24), 82 GPR_OFFSET_NAME(25), 83 GPR_OFFSET_NAME(26), 84 GPR_OFFSET_NAME(27), 85 GPR_OFFSET_NAME(28), 86 GPR_OFFSET_NAME(29), 87 GPR_OFFSET_NAME(30), 88 {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])}, 89 REG_OFFSET_NAME(sp), 90 REG_OFFSET_NAME(pc), 91 REG_OFFSET_NAME(pstate), 92 REG_OFFSET_END, 93 }; 94 95 /** 96 * regs_query_register_offset() - query register offset from its name 97 * @name: the name of a register 98 * 99 * regs_query_register_offset() returns the offset of a register in struct 100 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 101 */ 102 int regs_query_register_offset(const char *name) 103 { 104 const struct pt_regs_offset *roff; 105 106 for (roff = regoffset_table; roff->name != NULL; roff++) 107 if (!strcmp(roff->name, name)) 108 return roff->offset; 109 return -EINVAL; 110 } 111 112 /** 113 * regs_within_kernel_stack() - check the address in the stack 114 * @regs: pt_regs which contains kernel stack pointer. 115 * @addr: address which is checked. 116 * 117 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 118 * If @addr is within the kernel stack, it returns true. If not, returns false. 119 */ 120 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) 121 { 122 return ((addr & ~(THREAD_SIZE - 1)) == 123 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))) || 124 on_irq_stack(addr, sizeof(unsigned long)); 125 } 126 127 /** 128 * regs_get_kernel_stack_nth() - get Nth entry of the stack 129 * @regs: pt_regs which contains kernel stack pointer. 130 * @n: stack entry number. 131 * 132 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 133 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 134 * this returns 0. 135 */ 136 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) 137 { 138 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 139 140 addr += n; 141 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 142 return *addr; 143 else 144 return 0; 145 } 146 147 /* 148 * TODO: does not yet catch signals sent when the child dies. 149 * in exit.c or in signal.c. 150 */ 151 152 /* 153 * Called by kernel/ptrace.c when detaching.. 154 */ 155 void ptrace_disable(struct task_struct *child) 156 { 157 /* 158 * This would be better off in core code, but PTRACE_DETACH has 159 * grown its fair share of arch-specific worts and changing it 160 * is likely to cause regressions on obscure architectures. 161 */ 162 user_disable_single_step(child); 163 } 164 165 #ifdef CONFIG_HAVE_HW_BREAKPOINT 166 /* 167 * Handle hitting a HW-breakpoint. 168 */ 169 static void ptrace_hbptriggered(struct perf_event *bp, 170 struct perf_sample_data *data, 171 struct pt_regs *regs) 172 { 173 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); 174 const char *desc = "Hardware breakpoint trap (ptrace)"; 175 176 #ifdef CONFIG_COMPAT 177 if (is_compat_task()) { 178 int si_errno = 0; 179 int i; 180 181 for (i = 0; i < ARM_MAX_BRP; ++i) { 182 if (current->thread.debug.hbp_break[i] == bp) { 183 si_errno = (i << 1) + 1; 184 break; 185 } 186 } 187 188 for (i = 0; i < ARM_MAX_WRP; ++i) { 189 if (current->thread.debug.hbp_watch[i] == bp) { 190 si_errno = -((i << 1) + 1); 191 break; 192 } 193 } 194 arm64_force_sig_ptrace_errno_trap(si_errno, bkpt->trigger, 195 desc); 196 return; 197 } 198 #endif 199 arm64_force_sig_fault(SIGTRAP, TRAP_HWBKPT, bkpt->trigger, desc); 200 } 201 202 /* 203 * Unregister breakpoints from this task and reset the pointers in 204 * the thread_struct. 205 */ 206 void flush_ptrace_hw_breakpoint(struct task_struct *tsk) 207 { 208 int i; 209 struct thread_struct *t = &tsk->thread; 210 211 for (i = 0; i < ARM_MAX_BRP; i++) { 212 if (t->debug.hbp_break[i]) { 213 unregister_hw_breakpoint(t->debug.hbp_break[i]); 214 t->debug.hbp_break[i] = NULL; 215 } 216 } 217 218 for (i = 0; i < ARM_MAX_WRP; i++) { 219 if (t->debug.hbp_watch[i]) { 220 unregister_hw_breakpoint(t->debug.hbp_watch[i]); 221 t->debug.hbp_watch[i] = NULL; 222 } 223 } 224 } 225 226 void ptrace_hw_copy_thread(struct task_struct *tsk) 227 { 228 memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); 229 } 230 231 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type, 232 struct task_struct *tsk, 233 unsigned long idx) 234 { 235 struct perf_event *bp = ERR_PTR(-EINVAL); 236 237 switch (note_type) { 238 case NT_ARM_HW_BREAK: 239 if (idx >= ARM_MAX_BRP) 240 goto out; 241 idx = array_index_nospec(idx, ARM_MAX_BRP); 242 bp = tsk->thread.debug.hbp_break[idx]; 243 break; 244 case NT_ARM_HW_WATCH: 245 if (idx >= ARM_MAX_WRP) 246 goto out; 247 idx = array_index_nospec(idx, ARM_MAX_WRP); 248 bp = tsk->thread.debug.hbp_watch[idx]; 249 break; 250 } 251 252 out: 253 return bp; 254 } 255 256 static int ptrace_hbp_set_event(unsigned int note_type, 257 struct task_struct *tsk, 258 unsigned long idx, 259 struct perf_event *bp) 260 { 261 int err = -EINVAL; 262 263 switch (note_type) { 264 case NT_ARM_HW_BREAK: 265 if (idx >= ARM_MAX_BRP) 266 goto out; 267 idx = array_index_nospec(idx, ARM_MAX_BRP); 268 tsk->thread.debug.hbp_break[idx] = bp; 269 err = 0; 270 break; 271 case NT_ARM_HW_WATCH: 272 if (idx >= ARM_MAX_WRP) 273 goto out; 274 idx = array_index_nospec(idx, ARM_MAX_WRP); 275 tsk->thread.debug.hbp_watch[idx] = bp; 276 err = 0; 277 break; 278 } 279 280 out: 281 return err; 282 } 283 284 static struct perf_event *ptrace_hbp_create(unsigned int note_type, 285 struct task_struct *tsk, 286 unsigned long idx) 287 { 288 struct perf_event *bp; 289 struct perf_event_attr attr; 290 int err, type; 291 292 switch (note_type) { 293 case NT_ARM_HW_BREAK: 294 type = HW_BREAKPOINT_X; 295 break; 296 case NT_ARM_HW_WATCH: 297 type = HW_BREAKPOINT_RW; 298 break; 299 default: 300 return ERR_PTR(-EINVAL); 301 } 302 303 ptrace_breakpoint_init(&attr); 304 305 /* 306 * Initialise fields to sane defaults 307 * (i.e. values that will pass validation). 308 */ 309 attr.bp_addr = 0; 310 attr.bp_len = HW_BREAKPOINT_LEN_4; 311 attr.bp_type = type; 312 attr.disabled = 1; 313 314 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); 315 if (IS_ERR(bp)) 316 return bp; 317 318 err = ptrace_hbp_set_event(note_type, tsk, idx, bp); 319 if (err) 320 return ERR_PTR(err); 321 322 return bp; 323 } 324 325 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, 326 struct arch_hw_breakpoint_ctrl ctrl, 327 struct perf_event_attr *attr) 328 { 329 int err, len, type, offset, disabled = !ctrl.enabled; 330 331 attr->disabled = disabled; 332 if (disabled) 333 return 0; 334 335 err = arch_bp_generic_fields(ctrl, &len, &type, &offset); 336 if (err) 337 return err; 338 339 switch (note_type) { 340 case NT_ARM_HW_BREAK: 341 if ((type & HW_BREAKPOINT_X) != type) 342 return -EINVAL; 343 break; 344 case NT_ARM_HW_WATCH: 345 if ((type & HW_BREAKPOINT_RW) != type) 346 return -EINVAL; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 attr->bp_len = len; 353 attr->bp_type = type; 354 attr->bp_addr += offset; 355 356 return 0; 357 } 358 359 static int ptrace_hbp_get_resource_info(unsigned int note_type, u32 *info) 360 { 361 u8 num; 362 u32 reg = 0; 363 364 switch (note_type) { 365 case NT_ARM_HW_BREAK: 366 num = hw_breakpoint_slots(TYPE_INST); 367 break; 368 case NT_ARM_HW_WATCH: 369 num = hw_breakpoint_slots(TYPE_DATA); 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 reg |= debug_monitors_arch(); 376 reg <<= 8; 377 reg |= num; 378 379 *info = reg; 380 return 0; 381 } 382 383 static int ptrace_hbp_get_ctrl(unsigned int note_type, 384 struct task_struct *tsk, 385 unsigned long idx, 386 u32 *ctrl) 387 { 388 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 389 390 if (IS_ERR(bp)) 391 return PTR_ERR(bp); 392 393 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0; 394 return 0; 395 } 396 397 static int ptrace_hbp_get_addr(unsigned int note_type, 398 struct task_struct *tsk, 399 unsigned long idx, 400 u64 *addr) 401 { 402 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 403 404 if (IS_ERR(bp)) 405 return PTR_ERR(bp); 406 407 *addr = bp ? counter_arch_bp(bp)->address : 0; 408 return 0; 409 } 410 411 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type, 412 struct task_struct *tsk, 413 unsigned long idx) 414 { 415 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 416 417 if (!bp) 418 bp = ptrace_hbp_create(note_type, tsk, idx); 419 420 return bp; 421 } 422 423 static int ptrace_hbp_set_ctrl(unsigned int note_type, 424 struct task_struct *tsk, 425 unsigned long idx, 426 u32 uctrl) 427 { 428 int err; 429 struct perf_event *bp; 430 struct perf_event_attr attr; 431 struct arch_hw_breakpoint_ctrl ctrl; 432 433 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 434 if (IS_ERR(bp)) { 435 err = PTR_ERR(bp); 436 return err; 437 } 438 439 attr = bp->attr; 440 decode_ctrl_reg(uctrl, &ctrl); 441 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr); 442 if (err) 443 return err; 444 445 return modify_user_hw_breakpoint(bp, &attr); 446 } 447 448 static int ptrace_hbp_set_addr(unsigned int note_type, 449 struct task_struct *tsk, 450 unsigned long idx, 451 u64 addr) 452 { 453 int err; 454 struct perf_event *bp; 455 struct perf_event_attr attr; 456 457 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 458 if (IS_ERR(bp)) { 459 err = PTR_ERR(bp); 460 return err; 461 } 462 463 attr = bp->attr; 464 attr.bp_addr = addr; 465 err = modify_user_hw_breakpoint(bp, &attr); 466 return err; 467 } 468 469 #define PTRACE_HBP_ADDR_SZ sizeof(u64) 470 #define PTRACE_HBP_CTRL_SZ sizeof(u32) 471 #define PTRACE_HBP_PAD_SZ sizeof(u32) 472 473 static int hw_break_get(struct task_struct *target, 474 const struct user_regset *regset, 475 struct membuf to) 476 { 477 unsigned int note_type = regset->core_note_type; 478 int ret, idx = 0; 479 u32 info, ctrl; 480 u64 addr; 481 482 /* Resource info */ 483 ret = ptrace_hbp_get_resource_info(note_type, &info); 484 if (ret) 485 return ret; 486 487 membuf_write(&to, &info, sizeof(info)); 488 membuf_zero(&to, sizeof(u32)); 489 /* (address, ctrl) registers */ 490 while (to.left) { 491 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr); 492 if (ret) 493 return ret; 494 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl); 495 if (ret) 496 return ret; 497 membuf_store(&to, addr); 498 membuf_store(&to, ctrl); 499 membuf_zero(&to, sizeof(u32)); 500 idx++; 501 } 502 return 0; 503 } 504 505 static int hw_break_set(struct task_struct *target, 506 const struct user_regset *regset, 507 unsigned int pos, unsigned int count, 508 const void *kbuf, const void __user *ubuf) 509 { 510 unsigned int note_type = regset->core_note_type; 511 int ret, idx = 0, offset, limit; 512 u32 ctrl; 513 u64 addr; 514 515 /* Resource info and pad */ 516 offset = offsetof(struct user_hwdebug_state, dbg_regs); 517 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset); 518 if (ret) 519 return ret; 520 521 /* (address, ctrl) registers */ 522 limit = regset->n * regset->size; 523 while (count && offset < limit) { 524 if (count < PTRACE_HBP_ADDR_SZ) 525 return -EINVAL; 526 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr, 527 offset, offset + PTRACE_HBP_ADDR_SZ); 528 if (ret) 529 return ret; 530 ret = ptrace_hbp_set_addr(note_type, target, idx, addr); 531 if (ret) 532 return ret; 533 offset += PTRACE_HBP_ADDR_SZ; 534 535 if (!count) 536 break; 537 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 538 offset, offset + PTRACE_HBP_CTRL_SZ); 539 if (ret) 540 return ret; 541 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl); 542 if (ret) 543 return ret; 544 offset += PTRACE_HBP_CTRL_SZ; 545 546 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 547 offset, 548 offset + PTRACE_HBP_PAD_SZ); 549 if (ret) 550 return ret; 551 offset += PTRACE_HBP_PAD_SZ; 552 idx++; 553 } 554 555 return 0; 556 } 557 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 558 559 static int gpr_get(struct task_struct *target, 560 const struct user_regset *regset, 561 struct membuf to) 562 { 563 struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs; 564 return membuf_write(&to, uregs, sizeof(*uregs)); 565 } 566 567 static int gpr_set(struct task_struct *target, const struct user_regset *regset, 568 unsigned int pos, unsigned int count, 569 const void *kbuf, const void __user *ubuf) 570 { 571 int ret; 572 struct user_pt_regs newregs = task_pt_regs(target)->user_regs; 573 574 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1); 575 if (ret) 576 return ret; 577 578 if (!valid_user_regs(&newregs, target)) 579 return -EINVAL; 580 581 task_pt_regs(target)->user_regs = newregs; 582 return 0; 583 } 584 585 static int fpr_active(struct task_struct *target, const struct user_regset *regset) 586 { 587 if (!system_supports_fpsimd()) 588 return -ENODEV; 589 return regset->n; 590 } 591 592 /* 593 * TODO: update fp accessors for lazy context switching (sync/flush hwstate) 594 */ 595 static int __fpr_get(struct task_struct *target, 596 const struct user_regset *regset, 597 struct membuf to) 598 { 599 struct user_fpsimd_state *uregs; 600 601 sve_sync_to_fpsimd(target); 602 603 uregs = &target->thread.uw.fpsimd_state; 604 605 return membuf_write(&to, uregs, sizeof(*uregs)); 606 } 607 608 static int fpr_get(struct task_struct *target, const struct user_regset *regset, 609 struct membuf to) 610 { 611 if (!system_supports_fpsimd()) 612 return -EINVAL; 613 614 if (target == current) 615 fpsimd_preserve_current_state(); 616 617 return __fpr_get(target, regset, to); 618 } 619 620 static int __fpr_set(struct task_struct *target, 621 const struct user_regset *regset, 622 unsigned int pos, unsigned int count, 623 const void *kbuf, const void __user *ubuf, 624 unsigned int start_pos) 625 { 626 int ret; 627 struct user_fpsimd_state newstate; 628 629 /* 630 * Ensure target->thread.uw.fpsimd_state is up to date, so that a 631 * short copyin can't resurrect stale data. 632 */ 633 sve_sync_to_fpsimd(target); 634 635 newstate = target->thread.uw.fpsimd_state; 636 637 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 638 start_pos, start_pos + sizeof(newstate)); 639 if (ret) 640 return ret; 641 642 target->thread.uw.fpsimd_state = newstate; 643 644 return ret; 645 } 646 647 static int fpr_set(struct task_struct *target, const struct user_regset *regset, 648 unsigned int pos, unsigned int count, 649 const void *kbuf, const void __user *ubuf) 650 { 651 int ret; 652 653 if (!system_supports_fpsimd()) 654 return -EINVAL; 655 656 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0); 657 if (ret) 658 return ret; 659 660 sve_sync_from_fpsimd_zeropad(target); 661 fpsimd_flush_task_state(target); 662 663 return ret; 664 } 665 666 static int tls_get(struct task_struct *target, const struct user_regset *regset, 667 struct membuf to) 668 { 669 int ret; 670 671 if (target == current) 672 tls_preserve_current_state(); 673 674 ret = membuf_store(&to, target->thread.uw.tp_value); 675 if (system_supports_tpidr2()) 676 ret = membuf_store(&to, target->thread.tpidr2_el0); 677 else 678 ret = membuf_zero(&to, sizeof(u64)); 679 680 return ret; 681 } 682 683 static int tls_set(struct task_struct *target, const struct user_regset *regset, 684 unsigned int pos, unsigned int count, 685 const void *kbuf, const void __user *ubuf) 686 { 687 int ret; 688 unsigned long tls[2]; 689 690 tls[0] = target->thread.uw.tp_value; 691 if (system_supports_sme()) 692 tls[1] = target->thread.tpidr2_el0; 693 694 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, tls, 0, count); 695 if (ret) 696 return ret; 697 698 target->thread.uw.tp_value = tls[0]; 699 if (system_supports_sme()) 700 target->thread.tpidr2_el0 = tls[1]; 701 702 return ret; 703 } 704 705 static int system_call_get(struct task_struct *target, 706 const struct user_regset *regset, 707 struct membuf to) 708 { 709 return membuf_store(&to, task_pt_regs(target)->syscallno); 710 } 711 712 static int system_call_set(struct task_struct *target, 713 const struct user_regset *regset, 714 unsigned int pos, unsigned int count, 715 const void *kbuf, const void __user *ubuf) 716 { 717 int syscallno = task_pt_regs(target)->syscallno; 718 int ret; 719 720 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1); 721 if (ret) 722 return ret; 723 724 task_pt_regs(target)->syscallno = syscallno; 725 return ret; 726 } 727 728 #ifdef CONFIG_ARM64_SVE 729 730 static void sve_init_header_from_task(struct user_sve_header *header, 731 struct task_struct *target, 732 enum vec_type type) 733 { 734 unsigned int vq; 735 bool active; 736 bool fpsimd_only; 737 enum vec_type task_type; 738 739 memset(header, 0, sizeof(*header)); 740 741 /* Check if the requested registers are active for the task */ 742 if (thread_sm_enabled(&target->thread)) 743 task_type = ARM64_VEC_SME; 744 else 745 task_type = ARM64_VEC_SVE; 746 active = (task_type == type); 747 748 switch (type) { 749 case ARM64_VEC_SVE: 750 if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT)) 751 header->flags |= SVE_PT_VL_INHERIT; 752 fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE); 753 break; 754 case ARM64_VEC_SME: 755 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 756 header->flags |= SVE_PT_VL_INHERIT; 757 fpsimd_only = false; 758 break; 759 default: 760 WARN_ON_ONCE(1); 761 return; 762 } 763 764 if (active) { 765 if (fpsimd_only) { 766 header->flags |= SVE_PT_REGS_FPSIMD; 767 } else { 768 header->flags |= SVE_PT_REGS_SVE; 769 } 770 } 771 772 header->vl = task_get_vl(target, type); 773 vq = sve_vq_from_vl(header->vl); 774 775 header->max_vl = vec_max_vl(type); 776 header->size = SVE_PT_SIZE(vq, header->flags); 777 header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl), 778 SVE_PT_REGS_SVE); 779 } 780 781 static unsigned int sve_size_from_header(struct user_sve_header const *header) 782 { 783 return ALIGN(header->size, SVE_VQ_BYTES); 784 } 785 786 static int sve_get_common(struct task_struct *target, 787 const struct user_regset *regset, 788 struct membuf to, 789 enum vec_type type) 790 { 791 struct user_sve_header header; 792 unsigned int vq; 793 unsigned long start, end; 794 795 /* Header */ 796 sve_init_header_from_task(&header, target, type); 797 vq = sve_vq_from_vl(header.vl); 798 799 membuf_write(&to, &header, sizeof(header)); 800 801 if (target == current) 802 fpsimd_preserve_current_state(); 803 804 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 805 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 806 807 switch ((header.flags & SVE_PT_REGS_MASK)) { 808 case SVE_PT_REGS_FPSIMD: 809 return __fpr_get(target, regset, to); 810 811 case SVE_PT_REGS_SVE: 812 start = SVE_PT_SVE_OFFSET; 813 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 814 membuf_write(&to, target->thread.sve_state, end - start); 815 816 start = end; 817 end = SVE_PT_SVE_FPSR_OFFSET(vq); 818 membuf_zero(&to, end - start); 819 820 /* 821 * Copy fpsr, and fpcr which must follow contiguously in 822 * struct fpsimd_state: 823 */ 824 start = end; 825 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 826 membuf_write(&to, &target->thread.uw.fpsimd_state.fpsr, 827 end - start); 828 829 start = end; 830 end = sve_size_from_header(&header); 831 return membuf_zero(&to, end - start); 832 833 default: 834 return 0; 835 } 836 } 837 838 static int sve_get(struct task_struct *target, 839 const struct user_regset *regset, 840 struct membuf to) 841 { 842 if (!system_supports_sve()) 843 return -EINVAL; 844 845 return sve_get_common(target, regset, to, ARM64_VEC_SVE); 846 } 847 848 static int sve_set_common(struct task_struct *target, 849 const struct user_regset *regset, 850 unsigned int pos, unsigned int count, 851 const void *kbuf, const void __user *ubuf, 852 enum vec_type type) 853 { 854 int ret; 855 struct user_sve_header header; 856 unsigned int vq; 857 unsigned long start, end; 858 859 /* Header */ 860 if (count < sizeof(header)) 861 return -EINVAL; 862 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 863 0, sizeof(header)); 864 if (ret) 865 goto out; 866 867 /* 868 * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by 869 * vec_set_vector_length(), which will also validate them for us: 870 */ 871 ret = vec_set_vector_length(target, type, header.vl, 872 ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16); 873 if (ret) 874 goto out; 875 876 /* Actual VL set may be less than the user asked for: */ 877 vq = sve_vq_from_vl(task_get_vl(target, type)); 878 879 /* Enter/exit streaming mode */ 880 if (system_supports_sme()) { 881 u64 old_svcr = target->thread.svcr; 882 883 switch (type) { 884 case ARM64_VEC_SVE: 885 target->thread.svcr &= ~SVCR_SM_MASK; 886 break; 887 case ARM64_VEC_SME: 888 target->thread.svcr |= SVCR_SM_MASK; 889 break; 890 default: 891 WARN_ON_ONCE(1); 892 return -EINVAL; 893 } 894 895 /* 896 * If we switched then invalidate any existing SVE 897 * state and ensure there's storage. 898 */ 899 if (target->thread.svcr != old_svcr) 900 sve_alloc(target, true); 901 } 902 903 /* Registers: FPSIMD-only case */ 904 905 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 906 if ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) { 907 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 908 SVE_PT_FPSIMD_OFFSET); 909 clear_tsk_thread_flag(target, TIF_SVE); 910 target->thread.fp_type = FP_STATE_FPSIMD; 911 goto out; 912 } 913 914 /* 915 * Otherwise: no registers or full SVE case. For backwards 916 * compatibility reasons we treat empty flags as SVE registers. 917 */ 918 919 /* 920 * If setting a different VL from the requested VL and there is 921 * register data, the data layout will be wrong: don't even 922 * try to set the registers in this case. 923 */ 924 if (count && vq != sve_vq_from_vl(header.vl)) { 925 ret = -EIO; 926 goto out; 927 } 928 929 sve_alloc(target, true); 930 if (!target->thread.sve_state) { 931 ret = -ENOMEM; 932 clear_tsk_thread_flag(target, TIF_SVE); 933 target->thread.fp_type = FP_STATE_FPSIMD; 934 goto out; 935 } 936 937 /* 938 * Ensure target->thread.sve_state is up to date with target's 939 * FPSIMD regs, so that a short copyin leaves trailing 940 * registers unmodified. Always enable SVE even if going into 941 * streaming mode. 942 */ 943 fpsimd_sync_to_sve(target); 944 set_tsk_thread_flag(target, TIF_SVE); 945 target->thread.fp_type = FP_STATE_SVE; 946 947 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 948 start = SVE_PT_SVE_OFFSET; 949 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 950 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 951 target->thread.sve_state, 952 start, end); 953 if (ret) 954 goto out; 955 956 start = end; 957 end = SVE_PT_SVE_FPSR_OFFSET(vq); 958 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 959 start, end); 960 if (ret) 961 goto out; 962 963 /* 964 * Copy fpsr, and fpcr which must follow contiguously in 965 * struct fpsimd_state: 966 */ 967 start = end; 968 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 969 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 970 &target->thread.uw.fpsimd_state.fpsr, 971 start, end); 972 973 out: 974 fpsimd_flush_task_state(target); 975 return ret; 976 } 977 978 static int sve_set(struct task_struct *target, 979 const struct user_regset *regset, 980 unsigned int pos, unsigned int count, 981 const void *kbuf, const void __user *ubuf) 982 { 983 if (!system_supports_sve()) 984 return -EINVAL; 985 986 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 987 ARM64_VEC_SVE); 988 } 989 990 #endif /* CONFIG_ARM64_SVE */ 991 992 #ifdef CONFIG_ARM64_SME 993 994 static int ssve_get(struct task_struct *target, 995 const struct user_regset *regset, 996 struct membuf to) 997 { 998 if (!system_supports_sme()) 999 return -EINVAL; 1000 1001 return sve_get_common(target, regset, to, ARM64_VEC_SME); 1002 } 1003 1004 static int ssve_set(struct task_struct *target, 1005 const struct user_regset *regset, 1006 unsigned int pos, unsigned int count, 1007 const void *kbuf, const void __user *ubuf) 1008 { 1009 if (!system_supports_sme()) 1010 return -EINVAL; 1011 1012 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 1013 ARM64_VEC_SME); 1014 } 1015 1016 static int za_get(struct task_struct *target, 1017 const struct user_regset *regset, 1018 struct membuf to) 1019 { 1020 struct user_za_header header; 1021 unsigned int vq; 1022 unsigned long start, end; 1023 1024 if (!system_supports_sme()) 1025 return -EINVAL; 1026 1027 /* Header */ 1028 memset(&header, 0, sizeof(header)); 1029 1030 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 1031 header.flags |= ZA_PT_VL_INHERIT; 1032 1033 header.vl = task_get_sme_vl(target); 1034 vq = sve_vq_from_vl(header.vl); 1035 header.max_vl = sme_max_vl(); 1036 header.max_size = ZA_PT_SIZE(vq); 1037 1038 /* If ZA is not active there is only the header */ 1039 if (thread_za_enabled(&target->thread)) 1040 header.size = ZA_PT_SIZE(vq); 1041 else 1042 header.size = ZA_PT_ZA_OFFSET; 1043 1044 membuf_write(&to, &header, sizeof(header)); 1045 1046 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1047 end = ZA_PT_ZA_OFFSET; 1048 1049 if (target == current) 1050 fpsimd_preserve_current_state(); 1051 1052 /* Any register data to include? */ 1053 if (thread_za_enabled(&target->thread)) { 1054 start = end; 1055 end = ZA_PT_SIZE(vq); 1056 membuf_write(&to, target->thread.za_state, end - start); 1057 } 1058 1059 /* Zero any trailing padding */ 1060 start = end; 1061 end = ALIGN(header.size, SVE_VQ_BYTES); 1062 return membuf_zero(&to, end - start); 1063 } 1064 1065 static int za_set(struct task_struct *target, 1066 const struct user_regset *regset, 1067 unsigned int pos, unsigned int count, 1068 const void *kbuf, const void __user *ubuf) 1069 { 1070 int ret; 1071 struct user_za_header header; 1072 unsigned int vq; 1073 unsigned long start, end; 1074 1075 if (!system_supports_sme()) 1076 return -EINVAL; 1077 1078 /* Header */ 1079 if (count < sizeof(header)) 1080 return -EINVAL; 1081 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 1082 0, sizeof(header)); 1083 if (ret) 1084 goto out; 1085 1086 /* 1087 * All current ZA_PT_* flags are consumed by 1088 * vec_set_vector_length(), which will also validate them for 1089 * us: 1090 */ 1091 ret = vec_set_vector_length(target, ARM64_VEC_SME, header.vl, 1092 ((unsigned long)header.flags) << 16); 1093 if (ret) 1094 goto out; 1095 1096 /* Actual VL set may be less than the user asked for: */ 1097 vq = sve_vq_from_vl(task_get_sme_vl(target)); 1098 1099 /* Ensure there is some SVE storage for streaming mode */ 1100 if (!target->thread.sve_state) { 1101 sve_alloc(target, false); 1102 if (!target->thread.sve_state) { 1103 ret = -ENOMEM; 1104 goto out; 1105 } 1106 } 1107 1108 /* Allocate/reinit ZA storage */ 1109 sme_alloc(target); 1110 if (!target->thread.za_state) { 1111 ret = -ENOMEM; 1112 goto out; 1113 } 1114 1115 /* If there is no data then disable ZA */ 1116 if (!count) { 1117 target->thread.svcr &= ~SVCR_ZA_MASK; 1118 goto out; 1119 } 1120 1121 /* 1122 * If setting a different VL from the requested VL and there is 1123 * register data, the data layout will be wrong: don't even 1124 * try to set the registers in this case. 1125 */ 1126 if (vq != sve_vq_from_vl(header.vl)) { 1127 ret = -EIO; 1128 goto out; 1129 } 1130 1131 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1132 start = ZA_PT_ZA_OFFSET; 1133 end = ZA_PT_SIZE(vq); 1134 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1135 target->thread.za_state, 1136 start, end); 1137 if (ret) 1138 goto out; 1139 1140 /* Mark ZA as active and let userspace use it */ 1141 set_tsk_thread_flag(target, TIF_SME); 1142 target->thread.svcr |= SVCR_ZA_MASK; 1143 1144 out: 1145 fpsimd_flush_task_state(target); 1146 return ret; 1147 } 1148 1149 #endif /* CONFIG_ARM64_SME */ 1150 1151 #ifdef CONFIG_ARM64_PTR_AUTH 1152 static int pac_mask_get(struct task_struct *target, 1153 const struct user_regset *regset, 1154 struct membuf to) 1155 { 1156 /* 1157 * The PAC bits can differ across data and instruction pointers 1158 * depending on TCR_EL1.TBID*, which we may make use of in future, so 1159 * we expose separate masks. 1160 */ 1161 unsigned long mask = ptrauth_user_pac_mask(); 1162 struct user_pac_mask uregs = { 1163 .data_mask = mask, 1164 .insn_mask = mask, 1165 }; 1166 1167 if (!system_supports_address_auth()) 1168 return -EINVAL; 1169 1170 return membuf_write(&to, &uregs, sizeof(uregs)); 1171 } 1172 1173 static int pac_enabled_keys_get(struct task_struct *target, 1174 const struct user_regset *regset, 1175 struct membuf to) 1176 { 1177 long enabled_keys = ptrauth_get_enabled_keys(target); 1178 1179 if (IS_ERR_VALUE(enabled_keys)) 1180 return enabled_keys; 1181 1182 return membuf_write(&to, &enabled_keys, sizeof(enabled_keys)); 1183 } 1184 1185 static int pac_enabled_keys_set(struct task_struct *target, 1186 const struct user_regset *regset, 1187 unsigned int pos, unsigned int count, 1188 const void *kbuf, const void __user *ubuf) 1189 { 1190 int ret; 1191 long enabled_keys = ptrauth_get_enabled_keys(target); 1192 1193 if (IS_ERR_VALUE(enabled_keys)) 1194 return enabled_keys; 1195 1196 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &enabled_keys, 0, 1197 sizeof(long)); 1198 if (ret) 1199 return ret; 1200 1201 return ptrauth_set_enabled_keys(target, PR_PAC_ENABLED_KEYS_MASK, 1202 enabled_keys); 1203 } 1204 1205 #ifdef CONFIG_CHECKPOINT_RESTORE 1206 static __uint128_t pac_key_to_user(const struct ptrauth_key *key) 1207 { 1208 return (__uint128_t)key->hi << 64 | key->lo; 1209 } 1210 1211 static struct ptrauth_key pac_key_from_user(__uint128_t ukey) 1212 { 1213 struct ptrauth_key key = { 1214 .lo = (unsigned long)ukey, 1215 .hi = (unsigned long)(ukey >> 64), 1216 }; 1217 1218 return key; 1219 } 1220 1221 static void pac_address_keys_to_user(struct user_pac_address_keys *ukeys, 1222 const struct ptrauth_keys_user *keys) 1223 { 1224 ukeys->apiakey = pac_key_to_user(&keys->apia); 1225 ukeys->apibkey = pac_key_to_user(&keys->apib); 1226 ukeys->apdakey = pac_key_to_user(&keys->apda); 1227 ukeys->apdbkey = pac_key_to_user(&keys->apdb); 1228 } 1229 1230 static void pac_address_keys_from_user(struct ptrauth_keys_user *keys, 1231 const struct user_pac_address_keys *ukeys) 1232 { 1233 keys->apia = pac_key_from_user(ukeys->apiakey); 1234 keys->apib = pac_key_from_user(ukeys->apibkey); 1235 keys->apda = pac_key_from_user(ukeys->apdakey); 1236 keys->apdb = pac_key_from_user(ukeys->apdbkey); 1237 } 1238 1239 static int pac_address_keys_get(struct task_struct *target, 1240 const struct user_regset *regset, 1241 struct membuf to) 1242 { 1243 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1244 struct user_pac_address_keys user_keys; 1245 1246 if (!system_supports_address_auth()) 1247 return -EINVAL; 1248 1249 pac_address_keys_to_user(&user_keys, keys); 1250 1251 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1252 } 1253 1254 static int pac_address_keys_set(struct task_struct *target, 1255 const struct user_regset *regset, 1256 unsigned int pos, unsigned int count, 1257 const void *kbuf, const void __user *ubuf) 1258 { 1259 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1260 struct user_pac_address_keys user_keys; 1261 int ret; 1262 1263 if (!system_supports_address_auth()) 1264 return -EINVAL; 1265 1266 pac_address_keys_to_user(&user_keys, keys); 1267 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1268 &user_keys, 0, -1); 1269 if (ret) 1270 return ret; 1271 pac_address_keys_from_user(keys, &user_keys); 1272 1273 return 0; 1274 } 1275 1276 static void pac_generic_keys_to_user(struct user_pac_generic_keys *ukeys, 1277 const struct ptrauth_keys_user *keys) 1278 { 1279 ukeys->apgakey = pac_key_to_user(&keys->apga); 1280 } 1281 1282 static void pac_generic_keys_from_user(struct ptrauth_keys_user *keys, 1283 const struct user_pac_generic_keys *ukeys) 1284 { 1285 keys->apga = pac_key_from_user(ukeys->apgakey); 1286 } 1287 1288 static int pac_generic_keys_get(struct task_struct *target, 1289 const struct user_regset *regset, 1290 struct membuf to) 1291 { 1292 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1293 struct user_pac_generic_keys user_keys; 1294 1295 if (!system_supports_generic_auth()) 1296 return -EINVAL; 1297 1298 pac_generic_keys_to_user(&user_keys, keys); 1299 1300 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1301 } 1302 1303 static int pac_generic_keys_set(struct task_struct *target, 1304 const struct user_regset *regset, 1305 unsigned int pos, unsigned int count, 1306 const void *kbuf, const void __user *ubuf) 1307 { 1308 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1309 struct user_pac_generic_keys user_keys; 1310 int ret; 1311 1312 if (!system_supports_generic_auth()) 1313 return -EINVAL; 1314 1315 pac_generic_keys_to_user(&user_keys, keys); 1316 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1317 &user_keys, 0, -1); 1318 if (ret) 1319 return ret; 1320 pac_generic_keys_from_user(keys, &user_keys); 1321 1322 return 0; 1323 } 1324 #endif /* CONFIG_CHECKPOINT_RESTORE */ 1325 #endif /* CONFIG_ARM64_PTR_AUTH */ 1326 1327 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1328 static int tagged_addr_ctrl_get(struct task_struct *target, 1329 const struct user_regset *regset, 1330 struct membuf to) 1331 { 1332 long ctrl = get_tagged_addr_ctrl(target); 1333 1334 if (IS_ERR_VALUE(ctrl)) 1335 return ctrl; 1336 1337 return membuf_write(&to, &ctrl, sizeof(ctrl)); 1338 } 1339 1340 static int tagged_addr_ctrl_set(struct task_struct *target, const struct 1341 user_regset *regset, unsigned int pos, 1342 unsigned int count, const void *kbuf, const 1343 void __user *ubuf) 1344 { 1345 int ret; 1346 long ctrl; 1347 1348 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); 1349 if (ret) 1350 return ret; 1351 1352 return set_tagged_addr_ctrl(target, ctrl); 1353 } 1354 #endif 1355 1356 enum aarch64_regset { 1357 REGSET_GPR, 1358 REGSET_FPR, 1359 REGSET_TLS, 1360 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1361 REGSET_HW_BREAK, 1362 REGSET_HW_WATCH, 1363 #endif 1364 REGSET_SYSTEM_CALL, 1365 #ifdef CONFIG_ARM64_SVE 1366 REGSET_SVE, 1367 #endif 1368 #ifdef CONFIG_ARM64_SVE 1369 REGSET_SSVE, 1370 REGSET_ZA, 1371 #endif 1372 #ifdef CONFIG_ARM64_PTR_AUTH 1373 REGSET_PAC_MASK, 1374 REGSET_PAC_ENABLED_KEYS, 1375 #ifdef CONFIG_CHECKPOINT_RESTORE 1376 REGSET_PACA_KEYS, 1377 REGSET_PACG_KEYS, 1378 #endif 1379 #endif 1380 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1381 REGSET_TAGGED_ADDR_CTRL, 1382 #endif 1383 }; 1384 1385 static const struct user_regset aarch64_regsets[] = { 1386 [REGSET_GPR] = { 1387 .core_note_type = NT_PRSTATUS, 1388 .n = sizeof(struct user_pt_regs) / sizeof(u64), 1389 .size = sizeof(u64), 1390 .align = sizeof(u64), 1391 .regset_get = gpr_get, 1392 .set = gpr_set 1393 }, 1394 [REGSET_FPR] = { 1395 .core_note_type = NT_PRFPREG, 1396 .n = sizeof(struct user_fpsimd_state) / sizeof(u32), 1397 /* 1398 * We pretend we have 32-bit registers because the fpsr and 1399 * fpcr are 32-bits wide. 1400 */ 1401 .size = sizeof(u32), 1402 .align = sizeof(u32), 1403 .active = fpr_active, 1404 .regset_get = fpr_get, 1405 .set = fpr_set 1406 }, 1407 [REGSET_TLS] = { 1408 .core_note_type = NT_ARM_TLS, 1409 .n = 2, 1410 .size = sizeof(void *), 1411 .align = sizeof(void *), 1412 .regset_get = tls_get, 1413 .set = tls_set, 1414 }, 1415 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1416 [REGSET_HW_BREAK] = { 1417 .core_note_type = NT_ARM_HW_BREAK, 1418 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1419 .size = sizeof(u32), 1420 .align = sizeof(u32), 1421 .regset_get = hw_break_get, 1422 .set = hw_break_set, 1423 }, 1424 [REGSET_HW_WATCH] = { 1425 .core_note_type = NT_ARM_HW_WATCH, 1426 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1427 .size = sizeof(u32), 1428 .align = sizeof(u32), 1429 .regset_get = hw_break_get, 1430 .set = hw_break_set, 1431 }, 1432 #endif 1433 [REGSET_SYSTEM_CALL] = { 1434 .core_note_type = NT_ARM_SYSTEM_CALL, 1435 .n = 1, 1436 .size = sizeof(int), 1437 .align = sizeof(int), 1438 .regset_get = system_call_get, 1439 .set = system_call_set, 1440 }, 1441 #ifdef CONFIG_ARM64_SVE 1442 [REGSET_SVE] = { /* Scalable Vector Extension */ 1443 .core_note_type = NT_ARM_SVE, 1444 .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE), 1445 SVE_VQ_BYTES), 1446 .size = SVE_VQ_BYTES, 1447 .align = SVE_VQ_BYTES, 1448 .regset_get = sve_get, 1449 .set = sve_set, 1450 }, 1451 #endif 1452 #ifdef CONFIG_ARM64_SME 1453 [REGSET_SSVE] = { /* Streaming mode SVE */ 1454 .core_note_type = NT_ARM_SSVE, 1455 .n = DIV_ROUND_UP(SVE_PT_SIZE(SME_VQ_MAX, SVE_PT_REGS_SVE), 1456 SVE_VQ_BYTES), 1457 .size = SVE_VQ_BYTES, 1458 .align = SVE_VQ_BYTES, 1459 .regset_get = ssve_get, 1460 .set = ssve_set, 1461 }, 1462 [REGSET_ZA] = { /* SME ZA */ 1463 .core_note_type = NT_ARM_ZA, 1464 /* 1465 * ZA is a single register but it's variably sized and 1466 * the ptrace core requires that the size of any data 1467 * be an exact multiple of the configured register 1468 * size so report as though we had SVE_VQ_BYTES 1469 * registers. These values aren't exposed to 1470 * userspace. 1471 */ 1472 .n = DIV_ROUND_UP(ZA_PT_SIZE(SME_VQ_MAX), SVE_VQ_BYTES), 1473 .size = SVE_VQ_BYTES, 1474 .align = SVE_VQ_BYTES, 1475 .regset_get = za_get, 1476 .set = za_set, 1477 }, 1478 #endif 1479 #ifdef CONFIG_ARM64_PTR_AUTH 1480 [REGSET_PAC_MASK] = { 1481 .core_note_type = NT_ARM_PAC_MASK, 1482 .n = sizeof(struct user_pac_mask) / sizeof(u64), 1483 .size = sizeof(u64), 1484 .align = sizeof(u64), 1485 .regset_get = pac_mask_get, 1486 /* this cannot be set dynamically */ 1487 }, 1488 [REGSET_PAC_ENABLED_KEYS] = { 1489 .core_note_type = NT_ARM_PAC_ENABLED_KEYS, 1490 .n = 1, 1491 .size = sizeof(long), 1492 .align = sizeof(long), 1493 .regset_get = pac_enabled_keys_get, 1494 .set = pac_enabled_keys_set, 1495 }, 1496 #ifdef CONFIG_CHECKPOINT_RESTORE 1497 [REGSET_PACA_KEYS] = { 1498 .core_note_type = NT_ARM_PACA_KEYS, 1499 .n = sizeof(struct user_pac_address_keys) / sizeof(__uint128_t), 1500 .size = sizeof(__uint128_t), 1501 .align = sizeof(__uint128_t), 1502 .regset_get = pac_address_keys_get, 1503 .set = pac_address_keys_set, 1504 }, 1505 [REGSET_PACG_KEYS] = { 1506 .core_note_type = NT_ARM_PACG_KEYS, 1507 .n = sizeof(struct user_pac_generic_keys) / sizeof(__uint128_t), 1508 .size = sizeof(__uint128_t), 1509 .align = sizeof(__uint128_t), 1510 .regset_get = pac_generic_keys_get, 1511 .set = pac_generic_keys_set, 1512 }, 1513 #endif 1514 #endif 1515 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1516 [REGSET_TAGGED_ADDR_CTRL] = { 1517 .core_note_type = NT_ARM_TAGGED_ADDR_CTRL, 1518 .n = 1, 1519 .size = sizeof(long), 1520 .align = sizeof(long), 1521 .regset_get = tagged_addr_ctrl_get, 1522 .set = tagged_addr_ctrl_set, 1523 }, 1524 #endif 1525 }; 1526 1527 static const struct user_regset_view user_aarch64_view = { 1528 .name = "aarch64", .e_machine = EM_AARCH64, 1529 .regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets) 1530 }; 1531 1532 #ifdef CONFIG_COMPAT 1533 enum compat_regset { 1534 REGSET_COMPAT_GPR, 1535 REGSET_COMPAT_VFP, 1536 }; 1537 1538 static inline compat_ulong_t compat_get_user_reg(struct task_struct *task, int idx) 1539 { 1540 struct pt_regs *regs = task_pt_regs(task); 1541 1542 switch (idx) { 1543 case 15: 1544 return regs->pc; 1545 case 16: 1546 return pstate_to_compat_psr(regs->pstate); 1547 case 17: 1548 return regs->orig_x0; 1549 default: 1550 return regs->regs[idx]; 1551 } 1552 } 1553 1554 static int compat_gpr_get(struct task_struct *target, 1555 const struct user_regset *regset, 1556 struct membuf to) 1557 { 1558 int i = 0; 1559 1560 while (to.left) 1561 membuf_store(&to, compat_get_user_reg(target, i++)); 1562 return 0; 1563 } 1564 1565 static int compat_gpr_set(struct task_struct *target, 1566 const struct user_regset *regset, 1567 unsigned int pos, unsigned int count, 1568 const void *kbuf, const void __user *ubuf) 1569 { 1570 struct pt_regs newregs; 1571 int ret = 0; 1572 unsigned int i, start, num_regs; 1573 1574 /* Calculate the number of AArch32 registers contained in count */ 1575 num_regs = count / regset->size; 1576 1577 /* Convert pos into an register number */ 1578 start = pos / regset->size; 1579 1580 if (start + num_regs > regset->n) 1581 return -EIO; 1582 1583 newregs = *task_pt_regs(target); 1584 1585 for (i = 0; i < num_regs; ++i) { 1586 unsigned int idx = start + i; 1587 compat_ulong_t reg; 1588 1589 if (kbuf) { 1590 memcpy(®, kbuf, sizeof(reg)); 1591 kbuf += sizeof(reg); 1592 } else { 1593 ret = copy_from_user(®, ubuf, sizeof(reg)); 1594 if (ret) { 1595 ret = -EFAULT; 1596 break; 1597 } 1598 1599 ubuf += sizeof(reg); 1600 } 1601 1602 switch (idx) { 1603 case 15: 1604 newregs.pc = reg; 1605 break; 1606 case 16: 1607 reg = compat_psr_to_pstate(reg); 1608 newregs.pstate = reg; 1609 break; 1610 case 17: 1611 newregs.orig_x0 = reg; 1612 break; 1613 default: 1614 newregs.regs[idx] = reg; 1615 } 1616 1617 } 1618 1619 if (valid_user_regs(&newregs.user_regs, target)) 1620 *task_pt_regs(target) = newregs; 1621 else 1622 ret = -EINVAL; 1623 1624 return ret; 1625 } 1626 1627 static int compat_vfp_get(struct task_struct *target, 1628 const struct user_regset *regset, 1629 struct membuf to) 1630 { 1631 struct user_fpsimd_state *uregs; 1632 compat_ulong_t fpscr; 1633 1634 if (!system_supports_fpsimd()) 1635 return -EINVAL; 1636 1637 uregs = &target->thread.uw.fpsimd_state; 1638 1639 if (target == current) 1640 fpsimd_preserve_current_state(); 1641 1642 /* 1643 * The VFP registers are packed into the fpsimd_state, so they all sit 1644 * nicely together for us. We just need to create the fpscr separately. 1645 */ 1646 membuf_write(&to, uregs, VFP_STATE_SIZE - sizeof(compat_ulong_t)); 1647 fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) | 1648 (uregs->fpcr & VFP_FPSCR_CTRL_MASK); 1649 return membuf_store(&to, fpscr); 1650 } 1651 1652 static int compat_vfp_set(struct task_struct *target, 1653 const struct user_regset *regset, 1654 unsigned int pos, unsigned int count, 1655 const void *kbuf, const void __user *ubuf) 1656 { 1657 struct user_fpsimd_state *uregs; 1658 compat_ulong_t fpscr; 1659 int ret, vregs_end_pos; 1660 1661 if (!system_supports_fpsimd()) 1662 return -EINVAL; 1663 1664 uregs = &target->thread.uw.fpsimd_state; 1665 1666 vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t); 1667 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 1668 vregs_end_pos); 1669 1670 if (count && !ret) { 1671 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpscr, 1672 vregs_end_pos, VFP_STATE_SIZE); 1673 if (!ret) { 1674 uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK; 1675 uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK; 1676 } 1677 } 1678 1679 fpsimd_flush_task_state(target); 1680 return ret; 1681 } 1682 1683 static int compat_tls_get(struct task_struct *target, 1684 const struct user_regset *regset, 1685 struct membuf to) 1686 { 1687 return membuf_store(&to, (compat_ulong_t)target->thread.uw.tp_value); 1688 } 1689 1690 static int compat_tls_set(struct task_struct *target, 1691 const struct user_regset *regset, unsigned int pos, 1692 unsigned int count, const void *kbuf, 1693 const void __user *ubuf) 1694 { 1695 int ret; 1696 compat_ulong_t tls = target->thread.uw.tp_value; 1697 1698 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1); 1699 if (ret) 1700 return ret; 1701 1702 target->thread.uw.tp_value = tls; 1703 return ret; 1704 } 1705 1706 static const struct user_regset aarch32_regsets[] = { 1707 [REGSET_COMPAT_GPR] = { 1708 .core_note_type = NT_PRSTATUS, 1709 .n = COMPAT_ELF_NGREG, 1710 .size = sizeof(compat_elf_greg_t), 1711 .align = sizeof(compat_elf_greg_t), 1712 .regset_get = compat_gpr_get, 1713 .set = compat_gpr_set 1714 }, 1715 [REGSET_COMPAT_VFP] = { 1716 .core_note_type = NT_ARM_VFP, 1717 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1718 .size = sizeof(compat_ulong_t), 1719 .align = sizeof(compat_ulong_t), 1720 .active = fpr_active, 1721 .regset_get = compat_vfp_get, 1722 .set = compat_vfp_set 1723 }, 1724 }; 1725 1726 static const struct user_regset_view user_aarch32_view = { 1727 .name = "aarch32", .e_machine = EM_ARM, 1728 .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets) 1729 }; 1730 1731 static const struct user_regset aarch32_ptrace_regsets[] = { 1732 [REGSET_GPR] = { 1733 .core_note_type = NT_PRSTATUS, 1734 .n = COMPAT_ELF_NGREG, 1735 .size = sizeof(compat_elf_greg_t), 1736 .align = sizeof(compat_elf_greg_t), 1737 .regset_get = compat_gpr_get, 1738 .set = compat_gpr_set 1739 }, 1740 [REGSET_FPR] = { 1741 .core_note_type = NT_ARM_VFP, 1742 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1743 .size = sizeof(compat_ulong_t), 1744 .align = sizeof(compat_ulong_t), 1745 .regset_get = compat_vfp_get, 1746 .set = compat_vfp_set 1747 }, 1748 [REGSET_TLS] = { 1749 .core_note_type = NT_ARM_TLS, 1750 .n = 1, 1751 .size = sizeof(compat_ulong_t), 1752 .align = sizeof(compat_ulong_t), 1753 .regset_get = compat_tls_get, 1754 .set = compat_tls_set, 1755 }, 1756 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1757 [REGSET_HW_BREAK] = { 1758 .core_note_type = NT_ARM_HW_BREAK, 1759 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1760 .size = sizeof(u32), 1761 .align = sizeof(u32), 1762 .regset_get = hw_break_get, 1763 .set = hw_break_set, 1764 }, 1765 [REGSET_HW_WATCH] = { 1766 .core_note_type = NT_ARM_HW_WATCH, 1767 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1768 .size = sizeof(u32), 1769 .align = sizeof(u32), 1770 .regset_get = hw_break_get, 1771 .set = hw_break_set, 1772 }, 1773 #endif 1774 [REGSET_SYSTEM_CALL] = { 1775 .core_note_type = NT_ARM_SYSTEM_CALL, 1776 .n = 1, 1777 .size = sizeof(int), 1778 .align = sizeof(int), 1779 .regset_get = system_call_get, 1780 .set = system_call_set, 1781 }, 1782 }; 1783 1784 static const struct user_regset_view user_aarch32_ptrace_view = { 1785 .name = "aarch32", .e_machine = EM_ARM, 1786 .regsets = aarch32_ptrace_regsets, .n = ARRAY_SIZE(aarch32_ptrace_regsets) 1787 }; 1788 1789 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off, 1790 compat_ulong_t __user *ret) 1791 { 1792 compat_ulong_t tmp; 1793 1794 if (off & 3) 1795 return -EIO; 1796 1797 if (off == COMPAT_PT_TEXT_ADDR) 1798 tmp = tsk->mm->start_code; 1799 else if (off == COMPAT_PT_DATA_ADDR) 1800 tmp = tsk->mm->start_data; 1801 else if (off == COMPAT_PT_TEXT_END_ADDR) 1802 tmp = tsk->mm->end_code; 1803 else if (off < sizeof(compat_elf_gregset_t)) 1804 tmp = compat_get_user_reg(tsk, off >> 2); 1805 else if (off >= COMPAT_USER_SZ) 1806 return -EIO; 1807 else 1808 tmp = 0; 1809 1810 return put_user(tmp, ret); 1811 } 1812 1813 static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off, 1814 compat_ulong_t val) 1815 { 1816 struct pt_regs newregs = *task_pt_regs(tsk); 1817 unsigned int idx = off / 4; 1818 1819 if (off & 3 || off >= COMPAT_USER_SZ) 1820 return -EIO; 1821 1822 if (off >= sizeof(compat_elf_gregset_t)) 1823 return 0; 1824 1825 switch (idx) { 1826 case 15: 1827 newregs.pc = val; 1828 break; 1829 case 16: 1830 newregs.pstate = compat_psr_to_pstate(val); 1831 break; 1832 case 17: 1833 newregs.orig_x0 = val; 1834 break; 1835 default: 1836 newregs.regs[idx] = val; 1837 } 1838 1839 if (!valid_user_regs(&newregs.user_regs, tsk)) 1840 return -EINVAL; 1841 1842 *task_pt_regs(tsk) = newregs; 1843 return 0; 1844 } 1845 1846 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1847 1848 /* 1849 * Convert a virtual register number into an index for a thread_info 1850 * breakpoint array. Breakpoints are identified using positive numbers 1851 * whilst watchpoints are negative. The registers are laid out as pairs 1852 * of (address, control), each pair mapping to a unique hw_breakpoint struct. 1853 * Register 0 is reserved for describing resource information. 1854 */ 1855 static int compat_ptrace_hbp_num_to_idx(compat_long_t num) 1856 { 1857 return (abs(num) - 1) >> 1; 1858 } 1859 1860 static int compat_ptrace_hbp_get_resource_info(u32 *kdata) 1861 { 1862 u8 num_brps, num_wrps, debug_arch, wp_len; 1863 u32 reg = 0; 1864 1865 num_brps = hw_breakpoint_slots(TYPE_INST); 1866 num_wrps = hw_breakpoint_slots(TYPE_DATA); 1867 1868 debug_arch = debug_monitors_arch(); 1869 wp_len = 8; 1870 reg |= debug_arch; 1871 reg <<= 8; 1872 reg |= wp_len; 1873 reg <<= 8; 1874 reg |= num_wrps; 1875 reg <<= 8; 1876 reg |= num_brps; 1877 1878 *kdata = reg; 1879 return 0; 1880 } 1881 1882 static int compat_ptrace_hbp_get(unsigned int note_type, 1883 struct task_struct *tsk, 1884 compat_long_t num, 1885 u32 *kdata) 1886 { 1887 u64 addr = 0; 1888 u32 ctrl = 0; 1889 1890 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1891 1892 if (num & 1) { 1893 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr); 1894 *kdata = (u32)addr; 1895 } else { 1896 err = ptrace_hbp_get_ctrl(note_type, tsk, idx, &ctrl); 1897 *kdata = ctrl; 1898 } 1899 1900 return err; 1901 } 1902 1903 static int compat_ptrace_hbp_set(unsigned int note_type, 1904 struct task_struct *tsk, 1905 compat_long_t num, 1906 u32 *kdata) 1907 { 1908 u64 addr; 1909 u32 ctrl; 1910 1911 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1912 1913 if (num & 1) { 1914 addr = *kdata; 1915 err = ptrace_hbp_set_addr(note_type, tsk, idx, addr); 1916 } else { 1917 ctrl = *kdata; 1918 err = ptrace_hbp_set_ctrl(note_type, tsk, idx, ctrl); 1919 } 1920 1921 return err; 1922 } 1923 1924 static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num, 1925 compat_ulong_t __user *data) 1926 { 1927 int ret; 1928 u32 kdata; 1929 1930 /* Watchpoint */ 1931 if (num < 0) { 1932 ret = compat_ptrace_hbp_get(NT_ARM_HW_WATCH, tsk, num, &kdata); 1933 /* Resource info */ 1934 } else if (num == 0) { 1935 ret = compat_ptrace_hbp_get_resource_info(&kdata); 1936 /* Breakpoint */ 1937 } else { 1938 ret = compat_ptrace_hbp_get(NT_ARM_HW_BREAK, tsk, num, &kdata); 1939 } 1940 1941 if (!ret) 1942 ret = put_user(kdata, data); 1943 1944 return ret; 1945 } 1946 1947 static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num, 1948 compat_ulong_t __user *data) 1949 { 1950 int ret; 1951 u32 kdata = 0; 1952 1953 if (num == 0) 1954 return 0; 1955 1956 ret = get_user(kdata, data); 1957 if (ret) 1958 return ret; 1959 1960 if (num < 0) 1961 ret = compat_ptrace_hbp_set(NT_ARM_HW_WATCH, tsk, num, &kdata); 1962 else 1963 ret = compat_ptrace_hbp_set(NT_ARM_HW_BREAK, tsk, num, &kdata); 1964 1965 return ret; 1966 } 1967 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1968 1969 long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 1970 compat_ulong_t caddr, compat_ulong_t cdata) 1971 { 1972 unsigned long addr = caddr; 1973 unsigned long data = cdata; 1974 void __user *datap = compat_ptr(data); 1975 int ret; 1976 1977 switch (request) { 1978 case PTRACE_PEEKUSR: 1979 ret = compat_ptrace_read_user(child, addr, datap); 1980 break; 1981 1982 case PTRACE_POKEUSR: 1983 ret = compat_ptrace_write_user(child, addr, data); 1984 break; 1985 1986 case COMPAT_PTRACE_GETREGS: 1987 ret = copy_regset_to_user(child, 1988 &user_aarch32_view, 1989 REGSET_COMPAT_GPR, 1990 0, sizeof(compat_elf_gregset_t), 1991 datap); 1992 break; 1993 1994 case COMPAT_PTRACE_SETREGS: 1995 ret = copy_regset_from_user(child, 1996 &user_aarch32_view, 1997 REGSET_COMPAT_GPR, 1998 0, sizeof(compat_elf_gregset_t), 1999 datap); 2000 break; 2001 2002 case COMPAT_PTRACE_GET_THREAD_AREA: 2003 ret = put_user((compat_ulong_t)child->thread.uw.tp_value, 2004 (compat_ulong_t __user *)datap); 2005 break; 2006 2007 case COMPAT_PTRACE_SET_SYSCALL: 2008 task_pt_regs(child)->syscallno = data; 2009 ret = 0; 2010 break; 2011 2012 case COMPAT_PTRACE_GETVFPREGS: 2013 ret = copy_regset_to_user(child, 2014 &user_aarch32_view, 2015 REGSET_COMPAT_VFP, 2016 0, VFP_STATE_SIZE, 2017 datap); 2018 break; 2019 2020 case COMPAT_PTRACE_SETVFPREGS: 2021 ret = copy_regset_from_user(child, 2022 &user_aarch32_view, 2023 REGSET_COMPAT_VFP, 2024 0, VFP_STATE_SIZE, 2025 datap); 2026 break; 2027 2028 #ifdef CONFIG_HAVE_HW_BREAKPOINT 2029 case COMPAT_PTRACE_GETHBPREGS: 2030 ret = compat_ptrace_gethbpregs(child, addr, datap); 2031 break; 2032 2033 case COMPAT_PTRACE_SETHBPREGS: 2034 ret = compat_ptrace_sethbpregs(child, addr, datap); 2035 break; 2036 #endif 2037 2038 default: 2039 ret = compat_ptrace_request(child, request, addr, 2040 data); 2041 break; 2042 } 2043 2044 return ret; 2045 } 2046 #endif /* CONFIG_COMPAT */ 2047 2048 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 2049 { 2050 #ifdef CONFIG_COMPAT 2051 /* 2052 * Core dumping of 32-bit tasks or compat ptrace requests must use the 2053 * user_aarch32_view compatible with arm32. Native ptrace requests on 2054 * 32-bit children use an extended user_aarch32_ptrace_view to allow 2055 * access to the TLS register. 2056 */ 2057 if (is_compat_task()) 2058 return &user_aarch32_view; 2059 else if (is_compat_thread(task_thread_info(task))) 2060 return &user_aarch32_ptrace_view; 2061 #endif 2062 return &user_aarch64_view; 2063 } 2064 2065 long arch_ptrace(struct task_struct *child, long request, 2066 unsigned long addr, unsigned long data) 2067 { 2068 switch (request) { 2069 case PTRACE_PEEKMTETAGS: 2070 case PTRACE_POKEMTETAGS: 2071 return mte_ptrace_copy_tags(child, request, addr, data); 2072 } 2073 2074 return ptrace_request(child, request, addr, data); 2075 } 2076 2077 enum ptrace_syscall_dir { 2078 PTRACE_SYSCALL_ENTER = 0, 2079 PTRACE_SYSCALL_EXIT, 2080 }; 2081 2082 static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir) 2083 { 2084 int regno; 2085 unsigned long saved_reg; 2086 2087 /* 2088 * We have some ABI weirdness here in the way that we handle syscall 2089 * exit stops because we indicate whether or not the stop has been 2090 * signalled from syscall entry or syscall exit by clobbering a general 2091 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee 2092 * and restoring its old value after the stop. This means that: 2093 * 2094 * - Any writes by the tracer to this register during the stop are 2095 * ignored/discarded. 2096 * 2097 * - The actual value of the register is not available during the stop, 2098 * so the tracer cannot save it and restore it later. 2099 * 2100 * - Syscall stops behave differently to seccomp and pseudo-step traps 2101 * (the latter do not nobble any registers). 2102 */ 2103 regno = (is_compat_task() ? 12 : 7); 2104 saved_reg = regs->regs[regno]; 2105 regs->regs[regno] = dir; 2106 2107 if (dir == PTRACE_SYSCALL_ENTER) { 2108 if (ptrace_report_syscall_entry(regs)) 2109 forget_syscall(regs); 2110 regs->regs[regno] = saved_reg; 2111 } else if (!test_thread_flag(TIF_SINGLESTEP)) { 2112 ptrace_report_syscall_exit(regs, 0); 2113 regs->regs[regno] = saved_reg; 2114 } else { 2115 regs->regs[regno] = saved_reg; 2116 2117 /* 2118 * Signal a pseudo-step exception since we are stepping but 2119 * tracer modifications to the registers may have rewound the 2120 * state machine. 2121 */ 2122 ptrace_report_syscall_exit(regs, 1); 2123 } 2124 } 2125 2126 int syscall_trace_enter(struct pt_regs *regs) 2127 { 2128 unsigned long flags = read_thread_flags(); 2129 2130 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { 2131 report_syscall(regs, PTRACE_SYSCALL_ENTER); 2132 if (flags & _TIF_SYSCALL_EMU) 2133 return NO_SYSCALL; 2134 } 2135 2136 /* Do the secure computing after ptrace; failures should be fast. */ 2137 if (secure_computing() == -1) 2138 return NO_SYSCALL; 2139 2140 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) 2141 trace_sys_enter(regs, regs->syscallno); 2142 2143 audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1], 2144 regs->regs[2], regs->regs[3]); 2145 2146 return regs->syscallno; 2147 } 2148 2149 void syscall_trace_exit(struct pt_regs *regs) 2150 { 2151 unsigned long flags = read_thread_flags(); 2152 2153 audit_syscall_exit(regs); 2154 2155 if (flags & _TIF_SYSCALL_TRACEPOINT) 2156 trace_sys_exit(regs, syscall_get_return_value(current, regs)); 2157 2158 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) 2159 report_syscall(regs, PTRACE_SYSCALL_EXIT); 2160 2161 rseq_syscall(regs); 2162 } 2163 2164 /* 2165 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. 2166 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is 2167 * not described in ARM DDI 0487D.a. 2168 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may 2169 * be allocated an EL0 meaning in future. 2170 * Userspace cannot use these until they have an architectural meaning. 2171 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format. 2172 * We also reserve IL for the kernel; SS is handled dynamically. 2173 */ 2174 #define SPSR_EL1_AARCH64_RES0_BITS \ 2175 (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \ 2176 GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5)) 2177 #define SPSR_EL1_AARCH32_RES0_BITS \ 2178 (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) 2179 2180 static int valid_compat_regs(struct user_pt_regs *regs) 2181 { 2182 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; 2183 2184 if (!system_supports_mixed_endian_el0()) { 2185 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 2186 regs->pstate |= PSR_AA32_E_BIT; 2187 else 2188 regs->pstate &= ~PSR_AA32_E_BIT; 2189 } 2190 2191 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && 2192 (regs->pstate & PSR_AA32_A_BIT) == 0 && 2193 (regs->pstate & PSR_AA32_I_BIT) == 0 && 2194 (regs->pstate & PSR_AA32_F_BIT) == 0) { 2195 return 1; 2196 } 2197 2198 /* 2199 * Force PSR to a valid 32-bit EL0t, preserving the same bits as 2200 * arch/arm. 2201 */ 2202 regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT | 2203 PSR_AA32_C_BIT | PSR_AA32_V_BIT | 2204 PSR_AA32_Q_BIT | PSR_AA32_IT_MASK | 2205 PSR_AA32_GE_MASK | PSR_AA32_E_BIT | 2206 PSR_AA32_T_BIT; 2207 regs->pstate |= PSR_MODE32_BIT; 2208 2209 return 0; 2210 } 2211 2212 static int valid_native_regs(struct user_pt_regs *regs) 2213 { 2214 regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; 2215 2216 if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) && 2217 (regs->pstate & PSR_D_BIT) == 0 && 2218 (regs->pstate & PSR_A_BIT) == 0 && 2219 (regs->pstate & PSR_I_BIT) == 0 && 2220 (regs->pstate & PSR_F_BIT) == 0) { 2221 return 1; 2222 } 2223 2224 /* Force PSR to a valid 64-bit EL0t */ 2225 regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; 2226 2227 return 0; 2228 } 2229 2230 /* 2231 * Are the current registers suitable for user mode? (used to maintain 2232 * security in signal handlers) 2233 */ 2234 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task) 2235 { 2236 /* https://lore.kernel.org/lkml/20191118131525.GA4180@willie-the-truck */ 2237 user_regs_reset_single_step(regs, task); 2238 2239 if (is_compat_thread(task_thread_info(task))) 2240 return valid_compat_regs(regs); 2241 else 2242 return valid_native_regs(regs); 2243 } 2244