1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/kernel/ptrace.c 4 * 5 * By Ross Biro 1/23/92 6 * edited by Linus Torvalds 7 * ARM modifications Copyright (C) 2000 Russell King 8 * Copyright (C) 2012 ARM Ltd. 9 */ 10 11 #include <linux/audit.h> 12 #include <linux/compat.h> 13 #include <linux/kernel.h> 14 #include <linux/sched/signal.h> 15 #include <linux/sched/task_stack.h> 16 #include <linux/mm.h> 17 #include <linux/nospec.h> 18 #include <linux/smp.h> 19 #include <linux/ptrace.h> 20 #include <linux/user.h> 21 #include <linux/seccomp.h> 22 #include <linux/security.h> 23 #include <linux/init.h> 24 #include <linux/signal.h> 25 #include <linux/string.h> 26 #include <linux/uaccess.h> 27 #include <linux/perf_event.h> 28 #include <linux/hw_breakpoint.h> 29 #include <linux/regset.h> 30 #include <linux/elf.h> 31 32 #include <asm/compat.h> 33 #include <asm/cpufeature.h> 34 #include <asm/debug-monitors.h> 35 #include <asm/fpsimd.h> 36 #include <asm/mte.h> 37 #include <asm/pointer_auth.h> 38 #include <asm/stacktrace.h> 39 #include <asm/syscall.h> 40 #include <asm/traps.h> 41 #include <asm/system_misc.h> 42 43 #define CREATE_TRACE_POINTS 44 #include <trace/events/syscalls.h> 45 46 struct pt_regs_offset { 47 const char *name; 48 int offset; 49 }; 50 51 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 52 #define REG_OFFSET_END {.name = NULL, .offset = 0} 53 #define GPR_OFFSET_NAME(r) \ 54 {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])} 55 56 static const struct pt_regs_offset regoffset_table[] = { 57 GPR_OFFSET_NAME(0), 58 GPR_OFFSET_NAME(1), 59 GPR_OFFSET_NAME(2), 60 GPR_OFFSET_NAME(3), 61 GPR_OFFSET_NAME(4), 62 GPR_OFFSET_NAME(5), 63 GPR_OFFSET_NAME(6), 64 GPR_OFFSET_NAME(7), 65 GPR_OFFSET_NAME(8), 66 GPR_OFFSET_NAME(9), 67 GPR_OFFSET_NAME(10), 68 GPR_OFFSET_NAME(11), 69 GPR_OFFSET_NAME(12), 70 GPR_OFFSET_NAME(13), 71 GPR_OFFSET_NAME(14), 72 GPR_OFFSET_NAME(15), 73 GPR_OFFSET_NAME(16), 74 GPR_OFFSET_NAME(17), 75 GPR_OFFSET_NAME(18), 76 GPR_OFFSET_NAME(19), 77 GPR_OFFSET_NAME(20), 78 GPR_OFFSET_NAME(21), 79 GPR_OFFSET_NAME(22), 80 GPR_OFFSET_NAME(23), 81 GPR_OFFSET_NAME(24), 82 GPR_OFFSET_NAME(25), 83 GPR_OFFSET_NAME(26), 84 GPR_OFFSET_NAME(27), 85 GPR_OFFSET_NAME(28), 86 GPR_OFFSET_NAME(29), 87 GPR_OFFSET_NAME(30), 88 {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])}, 89 REG_OFFSET_NAME(sp), 90 REG_OFFSET_NAME(pc), 91 REG_OFFSET_NAME(pstate), 92 REG_OFFSET_END, 93 }; 94 95 /** 96 * regs_query_register_offset() - query register offset from its name 97 * @name: the name of a register 98 * 99 * regs_query_register_offset() returns the offset of a register in struct 100 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 101 */ 102 int regs_query_register_offset(const char *name) 103 { 104 const struct pt_regs_offset *roff; 105 106 for (roff = regoffset_table; roff->name != NULL; roff++) 107 if (!strcmp(roff->name, name)) 108 return roff->offset; 109 return -EINVAL; 110 } 111 112 /** 113 * regs_within_kernel_stack() - check the address in the stack 114 * @regs: pt_regs which contains kernel stack pointer. 115 * @addr: address which is checked. 116 * 117 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). 118 * If @addr is within the kernel stack, it returns true. If not, returns false. 119 */ 120 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) 121 { 122 return ((addr & ~(THREAD_SIZE - 1)) == 123 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))) || 124 on_irq_stack(addr, sizeof(unsigned long), NULL); 125 } 126 127 /** 128 * regs_get_kernel_stack_nth() - get Nth entry of the stack 129 * @regs: pt_regs which contains kernel stack pointer. 130 * @n: stack entry number. 131 * 132 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which 133 * is specified by @regs. If the @n th entry is NOT in the kernel stack, 134 * this returns 0. 135 */ 136 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) 137 { 138 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); 139 140 addr += n; 141 if (regs_within_kernel_stack(regs, (unsigned long)addr)) 142 return *addr; 143 else 144 return 0; 145 } 146 147 /* 148 * TODO: does not yet catch signals sent when the child dies. 149 * in exit.c or in signal.c. 150 */ 151 152 /* 153 * Called by kernel/ptrace.c when detaching.. 154 */ 155 void ptrace_disable(struct task_struct *child) 156 { 157 /* 158 * This would be better off in core code, but PTRACE_DETACH has 159 * grown its fair share of arch-specific worts and changing it 160 * is likely to cause regressions on obscure architectures. 161 */ 162 user_disable_single_step(child); 163 } 164 165 #ifdef CONFIG_HAVE_HW_BREAKPOINT 166 /* 167 * Handle hitting a HW-breakpoint. 168 */ 169 static void ptrace_hbptriggered(struct perf_event *bp, 170 struct perf_sample_data *data, 171 struct pt_regs *regs) 172 { 173 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); 174 const char *desc = "Hardware breakpoint trap (ptrace)"; 175 176 #ifdef CONFIG_COMPAT 177 if (is_compat_task()) { 178 int si_errno = 0; 179 int i; 180 181 for (i = 0; i < ARM_MAX_BRP; ++i) { 182 if (current->thread.debug.hbp_break[i] == bp) { 183 si_errno = (i << 1) + 1; 184 break; 185 } 186 } 187 188 for (i = 0; i < ARM_MAX_WRP; ++i) { 189 if (current->thread.debug.hbp_watch[i] == bp) { 190 si_errno = -((i << 1) + 1); 191 break; 192 } 193 } 194 arm64_force_sig_ptrace_errno_trap(si_errno, bkpt->trigger, 195 desc); 196 return; 197 } 198 #endif 199 arm64_force_sig_fault(SIGTRAP, TRAP_HWBKPT, bkpt->trigger, desc); 200 } 201 202 /* 203 * Unregister breakpoints from this task and reset the pointers in 204 * the thread_struct. 205 */ 206 void flush_ptrace_hw_breakpoint(struct task_struct *tsk) 207 { 208 int i; 209 struct thread_struct *t = &tsk->thread; 210 211 for (i = 0; i < ARM_MAX_BRP; i++) { 212 if (t->debug.hbp_break[i]) { 213 unregister_hw_breakpoint(t->debug.hbp_break[i]); 214 t->debug.hbp_break[i] = NULL; 215 } 216 } 217 218 for (i = 0; i < ARM_MAX_WRP; i++) { 219 if (t->debug.hbp_watch[i]) { 220 unregister_hw_breakpoint(t->debug.hbp_watch[i]); 221 t->debug.hbp_watch[i] = NULL; 222 } 223 } 224 } 225 226 void ptrace_hw_copy_thread(struct task_struct *tsk) 227 { 228 memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); 229 } 230 231 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type, 232 struct task_struct *tsk, 233 unsigned long idx) 234 { 235 struct perf_event *bp = ERR_PTR(-EINVAL); 236 237 switch (note_type) { 238 case NT_ARM_HW_BREAK: 239 if (idx >= ARM_MAX_BRP) 240 goto out; 241 idx = array_index_nospec(idx, ARM_MAX_BRP); 242 bp = tsk->thread.debug.hbp_break[idx]; 243 break; 244 case NT_ARM_HW_WATCH: 245 if (idx >= ARM_MAX_WRP) 246 goto out; 247 idx = array_index_nospec(idx, ARM_MAX_WRP); 248 bp = tsk->thread.debug.hbp_watch[idx]; 249 break; 250 } 251 252 out: 253 return bp; 254 } 255 256 static int ptrace_hbp_set_event(unsigned int note_type, 257 struct task_struct *tsk, 258 unsigned long idx, 259 struct perf_event *bp) 260 { 261 int err = -EINVAL; 262 263 switch (note_type) { 264 case NT_ARM_HW_BREAK: 265 if (idx >= ARM_MAX_BRP) 266 goto out; 267 idx = array_index_nospec(idx, ARM_MAX_BRP); 268 tsk->thread.debug.hbp_break[idx] = bp; 269 err = 0; 270 break; 271 case NT_ARM_HW_WATCH: 272 if (idx >= ARM_MAX_WRP) 273 goto out; 274 idx = array_index_nospec(idx, ARM_MAX_WRP); 275 tsk->thread.debug.hbp_watch[idx] = bp; 276 err = 0; 277 break; 278 } 279 280 out: 281 return err; 282 } 283 284 static struct perf_event *ptrace_hbp_create(unsigned int note_type, 285 struct task_struct *tsk, 286 unsigned long idx) 287 { 288 struct perf_event *bp; 289 struct perf_event_attr attr; 290 int err, type; 291 292 switch (note_type) { 293 case NT_ARM_HW_BREAK: 294 type = HW_BREAKPOINT_X; 295 break; 296 case NT_ARM_HW_WATCH: 297 type = HW_BREAKPOINT_RW; 298 break; 299 default: 300 return ERR_PTR(-EINVAL); 301 } 302 303 ptrace_breakpoint_init(&attr); 304 305 /* 306 * Initialise fields to sane defaults 307 * (i.e. values that will pass validation). 308 */ 309 attr.bp_addr = 0; 310 attr.bp_len = HW_BREAKPOINT_LEN_4; 311 attr.bp_type = type; 312 attr.disabled = 1; 313 314 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); 315 if (IS_ERR(bp)) 316 return bp; 317 318 err = ptrace_hbp_set_event(note_type, tsk, idx, bp); 319 if (err) 320 return ERR_PTR(err); 321 322 return bp; 323 } 324 325 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, 326 struct arch_hw_breakpoint_ctrl ctrl, 327 struct perf_event_attr *attr) 328 { 329 int err, len, type, offset, disabled = !ctrl.enabled; 330 331 attr->disabled = disabled; 332 if (disabled) 333 return 0; 334 335 err = arch_bp_generic_fields(ctrl, &len, &type, &offset); 336 if (err) 337 return err; 338 339 switch (note_type) { 340 case NT_ARM_HW_BREAK: 341 if ((type & HW_BREAKPOINT_X) != type) 342 return -EINVAL; 343 break; 344 case NT_ARM_HW_WATCH: 345 if ((type & HW_BREAKPOINT_RW) != type) 346 return -EINVAL; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 attr->bp_len = len; 353 attr->bp_type = type; 354 attr->bp_addr += offset; 355 356 return 0; 357 } 358 359 static int ptrace_hbp_get_resource_info(unsigned int note_type, u32 *info) 360 { 361 u8 num; 362 u32 reg = 0; 363 364 switch (note_type) { 365 case NT_ARM_HW_BREAK: 366 num = hw_breakpoint_slots(TYPE_INST); 367 break; 368 case NT_ARM_HW_WATCH: 369 num = hw_breakpoint_slots(TYPE_DATA); 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 reg |= debug_monitors_arch(); 376 reg <<= 8; 377 reg |= num; 378 379 *info = reg; 380 return 0; 381 } 382 383 static int ptrace_hbp_get_ctrl(unsigned int note_type, 384 struct task_struct *tsk, 385 unsigned long idx, 386 u32 *ctrl) 387 { 388 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 389 390 if (IS_ERR(bp)) 391 return PTR_ERR(bp); 392 393 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0; 394 return 0; 395 } 396 397 static int ptrace_hbp_get_addr(unsigned int note_type, 398 struct task_struct *tsk, 399 unsigned long idx, 400 u64 *addr) 401 { 402 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 403 404 if (IS_ERR(bp)) 405 return PTR_ERR(bp); 406 407 *addr = bp ? counter_arch_bp(bp)->address : 0; 408 return 0; 409 } 410 411 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type, 412 struct task_struct *tsk, 413 unsigned long idx) 414 { 415 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 416 417 if (!bp) 418 bp = ptrace_hbp_create(note_type, tsk, idx); 419 420 return bp; 421 } 422 423 static int ptrace_hbp_set_ctrl(unsigned int note_type, 424 struct task_struct *tsk, 425 unsigned long idx, 426 u32 uctrl) 427 { 428 int err; 429 struct perf_event *bp; 430 struct perf_event_attr attr; 431 struct arch_hw_breakpoint_ctrl ctrl; 432 433 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 434 if (IS_ERR(bp)) { 435 err = PTR_ERR(bp); 436 return err; 437 } 438 439 attr = bp->attr; 440 decode_ctrl_reg(uctrl, &ctrl); 441 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr); 442 if (err) 443 return err; 444 445 return modify_user_hw_breakpoint(bp, &attr); 446 } 447 448 static int ptrace_hbp_set_addr(unsigned int note_type, 449 struct task_struct *tsk, 450 unsigned long idx, 451 u64 addr) 452 { 453 int err; 454 struct perf_event *bp; 455 struct perf_event_attr attr; 456 457 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 458 if (IS_ERR(bp)) { 459 err = PTR_ERR(bp); 460 return err; 461 } 462 463 attr = bp->attr; 464 attr.bp_addr = addr; 465 err = modify_user_hw_breakpoint(bp, &attr); 466 return err; 467 } 468 469 #define PTRACE_HBP_ADDR_SZ sizeof(u64) 470 #define PTRACE_HBP_CTRL_SZ sizeof(u32) 471 #define PTRACE_HBP_PAD_SZ sizeof(u32) 472 473 static int hw_break_get(struct task_struct *target, 474 const struct user_regset *regset, 475 struct membuf to) 476 { 477 unsigned int note_type = regset->core_note_type; 478 int ret, idx = 0; 479 u32 info, ctrl; 480 u64 addr; 481 482 /* Resource info */ 483 ret = ptrace_hbp_get_resource_info(note_type, &info); 484 if (ret) 485 return ret; 486 487 membuf_write(&to, &info, sizeof(info)); 488 membuf_zero(&to, sizeof(u32)); 489 /* (address, ctrl) registers */ 490 while (to.left) { 491 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr); 492 if (ret) 493 return ret; 494 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl); 495 if (ret) 496 return ret; 497 membuf_store(&to, addr); 498 membuf_store(&to, ctrl); 499 membuf_zero(&to, sizeof(u32)); 500 idx++; 501 } 502 return 0; 503 } 504 505 static int hw_break_set(struct task_struct *target, 506 const struct user_regset *regset, 507 unsigned int pos, unsigned int count, 508 const void *kbuf, const void __user *ubuf) 509 { 510 unsigned int note_type = regset->core_note_type; 511 int ret, idx = 0, offset, limit; 512 u32 ctrl; 513 u64 addr; 514 515 /* Resource info and pad */ 516 offset = offsetof(struct user_hwdebug_state, dbg_regs); 517 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset); 518 if (ret) 519 return ret; 520 521 /* (address, ctrl) registers */ 522 limit = regset->n * regset->size; 523 while (count && offset < limit) { 524 if (count < PTRACE_HBP_ADDR_SZ) 525 return -EINVAL; 526 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr, 527 offset, offset + PTRACE_HBP_ADDR_SZ); 528 if (ret) 529 return ret; 530 ret = ptrace_hbp_set_addr(note_type, target, idx, addr); 531 if (ret) 532 return ret; 533 offset += PTRACE_HBP_ADDR_SZ; 534 535 if (!count) 536 break; 537 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 538 offset, offset + PTRACE_HBP_CTRL_SZ); 539 if (ret) 540 return ret; 541 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl); 542 if (ret) 543 return ret; 544 offset += PTRACE_HBP_CTRL_SZ; 545 546 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 547 offset, 548 offset + PTRACE_HBP_PAD_SZ); 549 if (ret) 550 return ret; 551 offset += PTRACE_HBP_PAD_SZ; 552 idx++; 553 } 554 555 return 0; 556 } 557 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 558 559 static int gpr_get(struct task_struct *target, 560 const struct user_regset *regset, 561 struct membuf to) 562 { 563 struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs; 564 return membuf_write(&to, uregs, sizeof(*uregs)); 565 } 566 567 static int gpr_set(struct task_struct *target, const struct user_regset *regset, 568 unsigned int pos, unsigned int count, 569 const void *kbuf, const void __user *ubuf) 570 { 571 int ret; 572 struct user_pt_regs newregs = task_pt_regs(target)->user_regs; 573 574 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1); 575 if (ret) 576 return ret; 577 578 if (!valid_user_regs(&newregs, target)) 579 return -EINVAL; 580 581 task_pt_regs(target)->user_regs = newregs; 582 return 0; 583 } 584 585 static int fpr_active(struct task_struct *target, const struct user_regset *regset) 586 { 587 if (!system_supports_fpsimd()) 588 return -ENODEV; 589 return regset->n; 590 } 591 592 /* 593 * TODO: update fp accessors for lazy context switching (sync/flush hwstate) 594 */ 595 static int __fpr_get(struct task_struct *target, 596 const struct user_regset *regset, 597 struct membuf to) 598 { 599 struct user_fpsimd_state *uregs; 600 601 sve_sync_to_fpsimd(target); 602 603 uregs = &target->thread.uw.fpsimd_state; 604 605 return membuf_write(&to, uregs, sizeof(*uregs)); 606 } 607 608 static int fpr_get(struct task_struct *target, const struct user_regset *regset, 609 struct membuf to) 610 { 611 if (!system_supports_fpsimd()) 612 return -EINVAL; 613 614 if (target == current) 615 fpsimd_preserve_current_state(); 616 617 return __fpr_get(target, regset, to); 618 } 619 620 static int __fpr_set(struct task_struct *target, 621 const struct user_regset *regset, 622 unsigned int pos, unsigned int count, 623 const void *kbuf, const void __user *ubuf, 624 unsigned int start_pos) 625 { 626 int ret; 627 struct user_fpsimd_state newstate; 628 629 /* 630 * Ensure target->thread.uw.fpsimd_state is up to date, so that a 631 * short copyin can't resurrect stale data. 632 */ 633 sve_sync_to_fpsimd(target); 634 635 newstate = target->thread.uw.fpsimd_state; 636 637 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 638 start_pos, start_pos + sizeof(newstate)); 639 if (ret) 640 return ret; 641 642 target->thread.uw.fpsimd_state = newstate; 643 644 return ret; 645 } 646 647 static int fpr_set(struct task_struct *target, const struct user_regset *regset, 648 unsigned int pos, unsigned int count, 649 const void *kbuf, const void __user *ubuf) 650 { 651 int ret; 652 653 if (!system_supports_fpsimd()) 654 return -EINVAL; 655 656 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0); 657 if (ret) 658 return ret; 659 660 sve_sync_from_fpsimd_zeropad(target); 661 fpsimd_flush_task_state(target); 662 663 return ret; 664 } 665 666 static int tls_get(struct task_struct *target, const struct user_regset *regset, 667 struct membuf to) 668 { 669 if (target == current) 670 tls_preserve_current_state(); 671 672 return membuf_store(&to, target->thread.uw.tp_value); 673 } 674 675 static int tls_set(struct task_struct *target, const struct user_regset *regset, 676 unsigned int pos, unsigned int count, 677 const void *kbuf, const void __user *ubuf) 678 { 679 int ret; 680 unsigned long tls = target->thread.uw.tp_value; 681 682 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1); 683 if (ret) 684 return ret; 685 686 target->thread.uw.tp_value = tls; 687 return ret; 688 } 689 690 static int system_call_get(struct task_struct *target, 691 const struct user_regset *regset, 692 struct membuf to) 693 { 694 return membuf_store(&to, task_pt_regs(target)->syscallno); 695 } 696 697 static int system_call_set(struct task_struct *target, 698 const struct user_regset *regset, 699 unsigned int pos, unsigned int count, 700 const void *kbuf, const void __user *ubuf) 701 { 702 int syscallno = task_pt_regs(target)->syscallno; 703 int ret; 704 705 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1); 706 if (ret) 707 return ret; 708 709 task_pt_regs(target)->syscallno = syscallno; 710 return ret; 711 } 712 713 #ifdef CONFIG_ARM64_SVE 714 715 static void sve_init_header_from_task(struct user_sve_header *header, 716 struct task_struct *target, 717 enum vec_type type) 718 { 719 unsigned int vq; 720 bool active; 721 bool fpsimd_only; 722 enum vec_type task_type; 723 724 memset(header, 0, sizeof(*header)); 725 726 /* Check if the requested registers are active for the task */ 727 if (thread_sm_enabled(&target->thread)) 728 task_type = ARM64_VEC_SME; 729 else 730 task_type = ARM64_VEC_SVE; 731 active = (task_type == type); 732 733 switch (type) { 734 case ARM64_VEC_SVE: 735 if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT)) 736 header->flags |= SVE_PT_VL_INHERIT; 737 fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE); 738 break; 739 case ARM64_VEC_SME: 740 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 741 header->flags |= SVE_PT_VL_INHERIT; 742 fpsimd_only = false; 743 break; 744 default: 745 WARN_ON_ONCE(1); 746 return; 747 } 748 749 if (active) { 750 if (fpsimd_only) { 751 header->flags |= SVE_PT_REGS_FPSIMD; 752 } else { 753 header->flags |= SVE_PT_REGS_SVE; 754 } 755 } 756 757 header->vl = task_get_vl(target, type); 758 vq = sve_vq_from_vl(header->vl); 759 760 header->max_vl = vec_max_vl(type); 761 header->size = SVE_PT_SIZE(vq, header->flags); 762 header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl), 763 SVE_PT_REGS_SVE); 764 } 765 766 static unsigned int sve_size_from_header(struct user_sve_header const *header) 767 { 768 return ALIGN(header->size, SVE_VQ_BYTES); 769 } 770 771 static int sve_get_common(struct task_struct *target, 772 const struct user_regset *regset, 773 struct membuf to, 774 enum vec_type type) 775 { 776 struct user_sve_header header; 777 unsigned int vq; 778 unsigned long start, end; 779 780 /* Header */ 781 sve_init_header_from_task(&header, target, type); 782 vq = sve_vq_from_vl(header.vl); 783 784 membuf_write(&to, &header, sizeof(header)); 785 786 if (target == current) 787 fpsimd_preserve_current_state(); 788 789 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 790 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 791 792 switch ((header.flags & SVE_PT_REGS_MASK)) { 793 case SVE_PT_REGS_FPSIMD: 794 return __fpr_get(target, regset, to); 795 796 case SVE_PT_REGS_SVE: 797 start = SVE_PT_SVE_OFFSET; 798 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 799 membuf_write(&to, target->thread.sve_state, end - start); 800 801 start = end; 802 end = SVE_PT_SVE_FPSR_OFFSET(vq); 803 membuf_zero(&to, end - start); 804 805 /* 806 * Copy fpsr, and fpcr which must follow contiguously in 807 * struct fpsimd_state: 808 */ 809 start = end; 810 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 811 membuf_write(&to, &target->thread.uw.fpsimd_state.fpsr, 812 end - start); 813 814 start = end; 815 end = sve_size_from_header(&header); 816 return membuf_zero(&to, end - start); 817 818 default: 819 return 0; 820 } 821 } 822 823 static int sve_get(struct task_struct *target, 824 const struct user_regset *regset, 825 struct membuf to) 826 { 827 if (!system_supports_sve()) 828 return -EINVAL; 829 830 return sve_get_common(target, regset, to, ARM64_VEC_SVE); 831 } 832 833 static int sve_set_common(struct task_struct *target, 834 const struct user_regset *regset, 835 unsigned int pos, unsigned int count, 836 const void *kbuf, const void __user *ubuf, 837 enum vec_type type) 838 { 839 int ret; 840 struct user_sve_header header; 841 unsigned int vq; 842 unsigned long start, end; 843 844 /* Header */ 845 if (count < sizeof(header)) 846 return -EINVAL; 847 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 848 0, sizeof(header)); 849 if (ret) 850 goto out; 851 852 /* 853 * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by 854 * vec_set_vector_length(), which will also validate them for us: 855 */ 856 ret = vec_set_vector_length(target, type, header.vl, 857 ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16); 858 if (ret) 859 goto out; 860 861 /* Actual VL set may be less than the user asked for: */ 862 vq = sve_vq_from_vl(task_get_vl(target, type)); 863 864 /* Enter/exit streaming mode */ 865 if (system_supports_sme()) { 866 u64 old_svcr = target->thread.svcr; 867 868 switch (type) { 869 case ARM64_VEC_SVE: 870 target->thread.svcr &= ~SVCR_SM_MASK; 871 break; 872 case ARM64_VEC_SME: 873 target->thread.svcr |= SVCR_SM_MASK; 874 break; 875 default: 876 WARN_ON_ONCE(1); 877 return -EINVAL; 878 } 879 880 /* 881 * If we switched then invalidate any existing SVE 882 * state and ensure there's storage. 883 */ 884 if (target->thread.svcr != old_svcr) 885 sve_alloc(target, true); 886 } 887 888 /* Registers: FPSIMD-only case */ 889 890 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header)); 891 if ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) { 892 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 893 SVE_PT_FPSIMD_OFFSET); 894 clear_tsk_thread_flag(target, TIF_SVE); 895 if (type == ARM64_VEC_SME) 896 fpsimd_force_sync_to_sve(target); 897 goto out; 898 } 899 900 /* 901 * Otherwise: no registers or full SVE case. For backwards 902 * compatibility reasons we treat empty flags as SVE registers. 903 */ 904 905 /* 906 * If setting a different VL from the requested VL and there is 907 * register data, the data layout will be wrong: don't even 908 * try to set the registers in this case. 909 */ 910 if (count && vq != sve_vq_from_vl(header.vl)) { 911 ret = -EIO; 912 goto out; 913 } 914 915 sve_alloc(target, true); 916 if (!target->thread.sve_state) { 917 ret = -ENOMEM; 918 clear_tsk_thread_flag(target, TIF_SVE); 919 goto out; 920 } 921 922 /* 923 * Ensure target->thread.sve_state is up to date with target's 924 * FPSIMD regs, so that a short copyin leaves trailing 925 * registers unmodified. Always enable SVE even if going into 926 * streaming mode. 927 */ 928 fpsimd_sync_to_sve(target); 929 set_tsk_thread_flag(target, TIF_SVE); 930 931 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); 932 start = SVE_PT_SVE_OFFSET; 933 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq); 934 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 935 target->thread.sve_state, 936 start, end); 937 if (ret) 938 goto out; 939 940 start = end; 941 end = SVE_PT_SVE_FPSR_OFFSET(vq); 942 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 943 start, end); 944 if (ret) 945 goto out; 946 947 /* 948 * Copy fpsr, and fpcr which must follow contiguously in 949 * struct fpsimd_state: 950 */ 951 start = end; 952 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE; 953 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 954 &target->thread.uw.fpsimd_state.fpsr, 955 start, end); 956 957 out: 958 fpsimd_flush_task_state(target); 959 return ret; 960 } 961 962 static int sve_set(struct task_struct *target, 963 const struct user_regset *regset, 964 unsigned int pos, unsigned int count, 965 const void *kbuf, const void __user *ubuf) 966 { 967 if (!system_supports_sve()) 968 return -EINVAL; 969 970 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 971 ARM64_VEC_SVE); 972 } 973 974 #endif /* CONFIG_ARM64_SVE */ 975 976 #ifdef CONFIG_ARM64_SME 977 978 static int ssve_get(struct task_struct *target, 979 const struct user_regset *regset, 980 struct membuf to) 981 { 982 if (!system_supports_sme()) 983 return -EINVAL; 984 985 return sve_get_common(target, regset, to, ARM64_VEC_SME); 986 } 987 988 static int ssve_set(struct task_struct *target, 989 const struct user_regset *regset, 990 unsigned int pos, unsigned int count, 991 const void *kbuf, const void __user *ubuf) 992 { 993 if (!system_supports_sme()) 994 return -EINVAL; 995 996 return sve_set_common(target, regset, pos, count, kbuf, ubuf, 997 ARM64_VEC_SME); 998 } 999 1000 static int za_get(struct task_struct *target, 1001 const struct user_regset *regset, 1002 struct membuf to) 1003 { 1004 struct user_za_header header; 1005 unsigned int vq; 1006 unsigned long start, end; 1007 1008 if (!system_supports_sme()) 1009 return -EINVAL; 1010 1011 /* Header */ 1012 memset(&header, 0, sizeof(header)); 1013 1014 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT)) 1015 header.flags |= ZA_PT_VL_INHERIT; 1016 1017 header.vl = task_get_sme_vl(target); 1018 vq = sve_vq_from_vl(header.vl); 1019 header.max_vl = sme_max_vl(); 1020 header.max_size = ZA_PT_SIZE(vq); 1021 1022 /* If ZA is not active there is only the header */ 1023 if (thread_za_enabled(&target->thread)) 1024 header.size = ZA_PT_SIZE(vq); 1025 else 1026 header.size = ZA_PT_ZA_OFFSET; 1027 1028 membuf_write(&to, &header, sizeof(header)); 1029 1030 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1031 end = ZA_PT_ZA_OFFSET; 1032 1033 if (target == current) 1034 fpsimd_preserve_current_state(); 1035 1036 /* Any register data to include? */ 1037 if (thread_za_enabled(&target->thread)) { 1038 start = end; 1039 end = ZA_PT_SIZE(vq); 1040 membuf_write(&to, target->thread.za_state, end - start); 1041 } 1042 1043 /* Zero any trailing padding */ 1044 start = end; 1045 end = ALIGN(header.size, SVE_VQ_BYTES); 1046 return membuf_zero(&to, end - start); 1047 } 1048 1049 static int za_set(struct task_struct *target, 1050 const struct user_regset *regset, 1051 unsigned int pos, unsigned int count, 1052 const void *kbuf, const void __user *ubuf) 1053 { 1054 int ret; 1055 struct user_za_header header; 1056 unsigned int vq; 1057 unsigned long start, end; 1058 1059 if (!system_supports_sme()) 1060 return -EINVAL; 1061 1062 /* Header */ 1063 if (count < sizeof(header)) 1064 return -EINVAL; 1065 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header, 1066 0, sizeof(header)); 1067 if (ret) 1068 goto out; 1069 1070 /* 1071 * All current ZA_PT_* flags are consumed by 1072 * vec_set_vector_length(), which will also validate them for 1073 * us: 1074 */ 1075 ret = vec_set_vector_length(target, ARM64_VEC_SME, header.vl, 1076 ((unsigned long)header.flags) << 16); 1077 if (ret) 1078 goto out; 1079 1080 /* Actual VL set may be less than the user asked for: */ 1081 vq = sve_vq_from_vl(task_get_sme_vl(target)); 1082 1083 /* Ensure there is some SVE storage for streaming mode */ 1084 if (!target->thread.sve_state) { 1085 sve_alloc(target, false); 1086 if (!target->thread.sve_state) { 1087 ret = -ENOMEM; 1088 goto out; 1089 } 1090 } 1091 1092 /* Allocate/reinit ZA storage */ 1093 sme_alloc(target); 1094 if (!target->thread.za_state) { 1095 ret = -ENOMEM; 1096 goto out; 1097 } 1098 1099 /* If there is no data then disable ZA */ 1100 if (!count) { 1101 target->thread.svcr &= ~SVCR_ZA_MASK; 1102 goto out; 1103 } 1104 1105 /* 1106 * If setting a different VL from the requested VL and there is 1107 * register data, the data layout will be wrong: don't even 1108 * try to set the registers in this case. 1109 */ 1110 if (vq != sve_vq_from_vl(header.vl)) { 1111 ret = -EIO; 1112 goto out; 1113 } 1114 1115 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header)); 1116 start = ZA_PT_ZA_OFFSET; 1117 end = ZA_PT_SIZE(vq); 1118 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1119 target->thread.za_state, 1120 start, end); 1121 if (ret) 1122 goto out; 1123 1124 /* Mark ZA as active and let userspace use it */ 1125 set_tsk_thread_flag(target, TIF_SME); 1126 target->thread.svcr |= SVCR_ZA_MASK; 1127 1128 out: 1129 fpsimd_flush_task_state(target); 1130 return ret; 1131 } 1132 1133 #endif /* CONFIG_ARM64_SME */ 1134 1135 #ifdef CONFIG_ARM64_PTR_AUTH 1136 static int pac_mask_get(struct task_struct *target, 1137 const struct user_regset *regset, 1138 struct membuf to) 1139 { 1140 /* 1141 * The PAC bits can differ across data and instruction pointers 1142 * depending on TCR_EL1.TBID*, which we may make use of in future, so 1143 * we expose separate masks. 1144 */ 1145 unsigned long mask = ptrauth_user_pac_mask(); 1146 struct user_pac_mask uregs = { 1147 .data_mask = mask, 1148 .insn_mask = mask, 1149 }; 1150 1151 if (!system_supports_address_auth()) 1152 return -EINVAL; 1153 1154 return membuf_write(&to, &uregs, sizeof(uregs)); 1155 } 1156 1157 static int pac_enabled_keys_get(struct task_struct *target, 1158 const struct user_regset *regset, 1159 struct membuf to) 1160 { 1161 long enabled_keys = ptrauth_get_enabled_keys(target); 1162 1163 if (IS_ERR_VALUE(enabled_keys)) 1164 return enabled_keys; 1165 1166 return membuf_write(&to, &enabled_keys, sizeof(enabled_keys)); 1167 } 1168 1169 static int pac_enabled_keys_set(struct task_struct *target, 1170 const struct user_regset *regset, 1171 unsigned int pos, unsigned int count, 1172 const void *kbuf, const void __user *ubuf) 1173 { 1174 int ret; 1175 long enabled_keys = ptrauth_get_enabled_keys(target); 1176 1177 if (IS_ERR_VALUE(enabled_keys)) 1178 return enabled_keys; 1179 1180 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &enabled_keys, 0, 1181 sizeof(long)); 1182 if (ret) 1183 return ret; 1184 1185 return ptrauth_set_enabled_keys(target, PR_PAC_ENABLED_KEYS_MASK, 1186 enabled_keys); 1187 } 1188 1189 #ifdef CONFIG_CHECKPOINT_RESTORE 1190 static __uint128_t pac_key_to_user(const struct ptrauth_key *key) 1191 { 1192 return (__uint128_t)key->hi << 64 | key->lo; 1193 } 1194 1195 static struct ptrauth_key pac_key_from_user(__uint128_t ukey) 1196 { 1197 struct ptrauth_key key = { 1198 .lo = (unsigned long)ukey, 1199 .hi = (unsigned long)(ukey >> 64), 1200 }; 1201 1202 return key; 1203 } 1204 1205 static void pac_address_keys_to_user(struct user_pac_address_keys *ukeys, 1206 const struct ptrauth_keys_user *keys) 1207 { 1208 ukeys->apiakey = pac_key_to_user(&keys->apia); 1209 ukeys->apibkey = pac_key_to_user(&keys->apib); 1210 ukeys->apdakey = pac_key_to_user(&keys->apda); 1211 ukeys->apdbkey = pac_key_to_user(&keys->apdb); 1212 } 1213 1214 static void pac_address_keys_from_user(struct ptrauth_keys_user *keys, 1215 const struct user_pac_address_keys *ukeys) 1216 { 1217 keys->apia = pac_key_from_user(ukeys->apiakey); 1218 keys->apib = pac_key_from_user(ukeys->apibkey); 1219 keys->apda = pac_key_from_user(ukeys->apdakey); 1220 keys->apdb = pac_key_from_user(ukeys->apdbkey); 1221 } 1222 1223 static int pac_address_keys_get(struct task_struct *target, 1224 const struct user_regset *regset, 1225 struct membuf to) 1226 { 1227 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1228 struct user_pac_address_keys user_keys; 1229 1230 if (!system_supports_address_auth()) 1231 return -EINVAL; 1232 1233 pac_address_keys_to_user(&user_keys, keys); 1234 1235 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1236 } 1237 1238 static int pac_address_keys_set(struct task_struct *target, 1239 const struct user_regset *regset, 1240 unsigned int pos, unsigned int count, 1241 const void *kbuf, const void __user *ubuf) 1242 { 1243 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1244 struct user_pac_address_keys user_keys; 1245 int ret; 1246 1247 if (!system_supports_address_auth()) 1248 return -EINVAL; 1249 1250 pac_address_keys_to_user(&user_keys, keys); 1251 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1252 &user_keys, 0, -1); 1253 if (ret) 1254 return ret; 1255 pac_address_keys_from_user(keys, &user_keys); 1256 1257 return 0; 1258 } 1259 1260 static void pac_generic_keys_to_user(struct user_pac_generic_keys *ukeys, 1261 const struct ptrauth_keys_user *keys) 1262 { 1263 ukeys->apgakey = pac_key_to_user(&keys->apga); 1264 } 1265 1266 static void pac_generic_keys_from_user(struct ptrauth_keys_user *keys, 1267 const struct user_pac_generic_keys *ukeys) 1268 { 1269 keys->apga = pac_key_from_user(ukeys->apgakey); 1270 } 1271 1272 static int pac_generic_keys_get(struct task_struct *target, 1273 const struct user_regset *regset, 1274 struct membuf to) 1275 { 1276 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1277 struct user_pac_generic_keys user_keys; 1278 1279 if (!system_supports_generic_auth()) 1280 return -EINVAL; 1281 1282 pac_generic_keys_to_user(&user_keys, keys); 1283 1284 return membuf_write(&to, &user_keys, sizeof(user_keys)); 1285 } 1286 1287 static int pac_generic_keys_set(struct task_struct *target, 1288 const struct user_regset *regset, 1289 unsigned int pos, unsigned int count, 1290 const void *kbuf, const void __user *ubuf) 1291 { 1292 struct ptrauth_keys_user *keys = &target->thread.keys_user; 1293 struct user_pac_generic_keys user_keys; 1294 int ret; 1295 1296 if (!system_supports_generic_auth()) 1297 return -EINVAL; 1298 1299 pac_generic_keys_to_user(&user_keys, keys); 1300 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 1301 &user_keys, 0, -1); 1302 if (ret) 1303 return ret; 1304 pac_generic_keys_from_user(keys, &user_keys); 1305 1306 return 0; 1307 } 1308 #endif /* CONFIG_CHECKPOINT_RESTORE */ 1309 #endif /* CONFIG_ARM64_PTR_AUTH */ 1310 1311 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1312 static int tagged_addr_ctrl_get(struct task_struct *target, 1313 const struct user_regset *regset, 1314 struct membuf to) 1315 { 1316 long ctrl = get_tagged_addr_ctrl(target); 1317 1318 if (IS_ERR_VALUE(ctrl)) 1319 return ctrl; 1320 1321 return membuf_write(&to, &ctrl, sizeof(ctrl)); 1322 } 1323 1324 static int tagged_addr_ctrl_set(struct task_struct *target, const struct 1325 user_regset *regset, unsigned int pos, 1326 unsigned int count, const void *kbuf, const 1327 void __user *ubuf) 1328 { 1329 int ret; 1330 long ctrl; 1331 1332 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); 1333 if (ret) 1334 return ret; 1335 1336 return set_tagged_addr_ctrl(target, ctrl); 1337 } 1338 #endif 1339 1340 enum aarch64_regset { 1341 REGSET_GPR, 1342 REGSET_FPR, 1343 REGSET_TLS, 1344 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1345 REGSET_HW_BREAK, 1346 REGSET_HW_WATCH, 1347 #endif 1348 REGSET_SYSTEM_CALL, 1349 #ifdef CONFIG_ARM64_SVE 1350 REGSET_SVE, 1351 #endif 1352 #ifdef CONFIG_ARM64_SVE 1353 REGSET_SSVE, 1354 REGSET_ZA, 1355 #endif 1356 #ifdef CONFIG_ARM64_PTR_AUTH 1357 REGSET_PAC_MASK, 1358 REGSET_PAC_ENABLED_KEYS, 1359 #ifdef CONFIG_CHECKPOINT_RESTORE 1360 REGSET_PACA_KEYS, 1361 REGSET_PACG_KEYS, 1362 #endif 1363 #endif 1364 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1365 REGSET_TAGGED_ADDR_CTRL, 1366 #endif 1367 }; 1368 1369 static const struct user_regset aarch64_regsets[] = { 1370 [REGSET_GPR] = { 1371 .core_note_type = NT_PRSTATUS, 1372 .n = sizeof(struct user_pt_regs) / sizeof(u64), 1373 .size = sizeof(u64), 1374 .align = sizeof(u64), 1375 .regset_get = gpr_get, 1376 .set = gpr_set 1377 }, 1378 [REGSET_FPR] = { 1379 .core_note_type = NT_PRFPREG, 1380 .n = sizeof(struct user_fpsimd_state) / sizeof(u32), 1381 /* 1382 * We pretend we have 32-bit registers because the fpsr and 1383 * fpcr are 32-bits wide. 1384 */ 1385 .size = sizeof(u32), 1386 .align = sizeof(u32), 1387 .active = fpr_active, 1388 .regset_get = fpr_get, 1389 .set = fpr_set 1390 }, 1391 [REGSET_TLS] = { 1392 .core_note_type = NT_ARM_TLS, 1393 .n = 1, 1394 .size = sizeof(void *), 1395 .align = sizeof(void *), 1396 .regset_get = tls_get, 1397 .set = tls_set, 1398 }, 1399 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1400 [REGSET_HW_BREAK] = { 1401 .core_note_type = NT_ARM_HW_BREAK, 1402 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1403 .size = sizeof(u32), 1404 .align = sizeof(u32), 1405 .regset_get = hw_break_get, 1406 .set = hw_break_set, 1407 }, 1408 [REGSET_HW_WATCH] = { 1409 .core_note_type = NT_ARM_HW_WATCH, 1410 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1411 .size = sizeof(u32), 1412 .align = sizeof(u32), 1413 .regset_get = hw_break_get, 1414 .set = hw_break_set, 1415 }, 1416 #endif 1417 [REGSET_SYSTEM_CALL] = { 1418 .core_note_type = NT_ARM_SYSTEM_CALL, 1419 .n = 1, 1420 .size = sizeof(int), 1421 .align = sizeof(int), 1422 .regset_get = system_call_get, 1423 .set = system_call_set, 1424 }, 1425 #ifdef CONFIG_ARM64_SVE 1426 [REGSET_SVE] = { /* Scalable Vector Extension */ 1427 .core_note_type = NT_ARM_SVE, 1428 .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE), 1429 SVE_VQ_BYTES), 1430 .size = SVE_VQ_BYTES, 1431 .align = SVE_VQ_BYTES, 1432 .regset_get = sve_get, 1433 .set = sve_set, 1434 }, 1435 #endif 1436 #ifdef CONFIG_ARM64_SME 1437 [REGSET_SSVE] = { /* Streaming mode SVE */ 1438 .core_note_type = NT_ARM_SSVE, 1439 .n = DIV_ROUND_UP(SVE_PT_SIZE(SME_VQ_MAX, SVE_PT_REGS_SVE), 1440 SVE_VQ_BYTES), 1441 .size = SVE_VQ_BYTES, 1442 .align = SVE_VQ_BYTES, 1443 .regset_get = ssve_get, 1444 .set = ssve_set, 1445 }, 1446 [REGSET_ZA] = { /* SME ZA */ 1447 .core_note_type = NT_ARM_ZA, 1448 /* 1449 * ZA is a single register but it's variably sized and 1450 * the ptrace core requires that the size of any data 1451 * be an exact multiple of the configured register 1452 * size so report as though we had SVE_VQ_BYTES 1453 * registers. These values aren't exposed to 1454 * userspace. 1455 */ 1456 .n = DIV_ROUND_UP(ZA_PT_SIZE(SME_VQ_MAX), SVE_VQ_BYTES), 1457 .size = SVE_VQ_BYTES, 1458 .align = SVE_VQ_BYTES, 1459 .regset_get = za_get, 1460 .set = za_set, 1461 }, 1462 #endif 1463 #ifdef CONFIG_ARM64_PTR_AUTH 1464 [REGSET_PAC_MASK] = { 1465 .core_note_type = NT_ARM_PAC_MASK, 1466 .n = sizeof(struct user_pac_mask) / sizeof(u64), 1467 .size = sizeof(u64), 1468 .align = sizeof(u64), 1469 .regset_get = pac_mask_get, 1470 /* this cannot be set dynamically */ 1471 }, 1472 [REGSET_PAC_ENABLED_KEYS] = { 1473 .core_note_type = NT_ARM_PAC_ENABLED_KEYS, 1474 .n = 1, 1475 .size = sizeof(long), 1476 .align = sizeof(long), 1477 .regset_get = pac_enabled_keys_get, 1478 .set = pac_enabled_keys_set, 1479 }, 1480 #ifdef CONFIG_CHECKPOINT_RESTORE 1481 [REGSET_PACA_KEYS] = { 1482 .core_note_type = NT_ARM_PACA_KEYS, 1483 .n = sizeof(struct user_pac_address_keys) / sizeof(__uint128_t), 1484 .size = sizeof(__uint128_t), 1485 .align = sizeof(__uint128_t), 1486 .regset_get = pac_address_keys_get, 1487 .set = pac_address_keys_set, 1488 }, 1489 [REGSET_PACG_KEYS] = { 1490 .core_note_type = NT_ARM_PACG_KEYS, 1491 .n = sizeof(struct user_pac_generic_keys) / sizeof(__uint128_t), 1492 .size = sizeof(__uint128_t), 1493 .align = sizeof(__uint128_t), 1494 .regset_get = pac_generic_keys_get, 1495 .set = pac_generic_keys_set, 1496 }, 1497 #endif 1498 #endif 1499 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 1500 [REGSET_TAGGED_ADDR_CTRL] = { 1501 .core_note_type = NT_ARM_TAGGED_ADDR_CTRL, 1502 .n = 1, 1503 .size = sizeof(long), 1504 .align = sizeof(long), 1505 .regset_get = tagged_addr_ctrl_get, 1506 .set = tagged_addr_ctrl_set, 1507 }, 1508 #endif 1509 }; 1510 1511 static const struct user_regset_view user_aarch64_view = { 1512 .name = "aarch64", .e_machine = EM_AARCH64, 1513 .regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets) 1514 }; 1515 1516 #ifdef CONFIG_COMPAT 1517 enum compat_regset { 1518 REGSET_COMPAT_GPR, 1519 REGSET_COMPAT_VFP, 1520 }; 1521 1522 static inline compat_ulong_t compat_get_user_reg(struct task_struct *task, int idx) 1523 { 1524 struct pt_regs *regs = task_pt_regs(task); 1525 1526 switch (idx) { 1527 case 15: 1528 return regs->pc; 1529 case 16: 1530 return pstate_to_compat_psr(regs->pstate); 1531 case 17: 1532 return regs->orig_x0; 1533 default: 1534 return regs->regs[idx]; 1535 } 1536 } 1537 1538 static int compat_gpr_get(struct task_struct *target, 1539 const struct user_regset *regset, 1540 struct membuf to) 1541 { 1542 int i = 0; 1543 1544 while (to.left) 1545 membuf_store(&to, compat_get_user_reg(target, i++)); 1546 return 0; 1547 } 1548 1549 static int compat_gpr_set(struct task_struct *target, 1550 const struct user_regset *regset, 1551 unsigned int pos, unsigned int count, 1552 const void *kbuf, const void __user *ubuf) 1553 { 1554 struct pt_regs newregs; 1555 int ret = 0; 1556 unsigned int i, start, num_regs; 1557 1558 /* Calculate the number of AArch32 registers contained in count */ 1559 num_regs = count / regset->size; 1560 1561 /* Convert pos into an register number */ 1562 start = pos / regset->size; 1563 1564 if (start + num_regs > regset->n) 1565 return -EIO; 1566 1567 newregs = *task_pt_regs(target); 1568 1569 for (i = 0; i < num_regs; ++i) { 1570 unsigned int idx = start + i; 1571 compat_ulong_t reg; 1572 1573 if (kbuf) { 1574 memcpy(®, kbuf, sizeof(reg)); 1575 kbuf += sizeof(reg); 1576 } else { 1577 ret = copy_from_user(®, ubuf, sizeof(reg)); 1578 if (ret) { 1579 ret = -EFAULT; 1580 break; 1581 } 1582 1583 ubuf += sizeof(reg); 1584 } 1585 1586 switch (idx) { 1587 case 15: 1588 newregs.pc = reg; 1589 break; 1590 case 16: 1591 reg = compat_psr_to_pstate(reg); 1592 newregs.pstate = reg; 1593 break; 1594 case 17: 1595 newregs.orig_x0 = reg; 1596 break; 1597 default: 1598 newregs.regs[idx] = reg; 1599 } 1600 1601 } 1602 1603 if (valid_user_regs(&newregs.user_regs, target)) 1604 *task_pt_regs(target) = newregs; 1605 else 1606 ret = -EINVAL; 1607 1608 return ret; 1609 } 1610 1611 static int compat_vfp_get(struct task_struct *target, 1612 const struct user_regset *regset, 1613 struct membuf to) 1614 { 1615 struct user_fpsimd_state *uregs; 1616 compat_ulong_t fpscr; 1617 1618 if (!system_supports_fpsimd()) 1619 return -EINVAL; 1620 1621 uregs = &target->thread.uw.fpsimd_state; 1622 1623 if (target == current) 1624 fpsimd_preserve_current_state(); 1625 1626 /* 1627 * The VFP registers are packed into the fpsimd_state, so they all sit 1628 * nicely together for us. We just need to create the fpscr separately. 1629 */ 1630 membuf_write(&to, uregs, VFP_STATE_SIZE - sizeof(compat_ulong_t)); 1631 fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) | 1632 (uregs->fpcr & VFP_FPSCR_CTRL_MASK); 1633 return membuf_store(&to, fpscr); 1634 } 1635 1636 static int compat_vfp_set(struct task_struct *target, 1637 const struct user_regset *regset, 1638 unsigned int pos, unsigned int count, 1639 const void *kbuf, const void __user *ubuf) 1640 { 1641 struct user_fpsimd_state *uregs; 1642 compat_ulong_t fpscr; 1643 int ret, vregs_end_pos; 1644 1645 if (!system_supports_fpsimd()) 1646 return -EINVAL; 1647 1648 uregs = &target->thread.uw.fpsimd_state; 1649 1650 vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t); 1651 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 1652 vregs_end_pos); 1653 1654 if (count && !ret) { 1655 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpscr, 1656 vregs_end_pos, VFP_STATE_SIZE); 1657 if (!ret) { 1658 uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK; 1659 uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK; 1660 } 1661 } 1662 1663 fpsimd_flush_task_state(target); 1664 return ret; 1665 } 1666 1667 static int compat_tls_get(struct task_struct *target, 1668 const struct user_regset *regset, 1669 struct membuf to) 1670 { 1671 return membuf_store(&to, (compat_ulong_t)target->thread.uw.tp_value); 1672 } 1673 1674 static int compat_tls_set(struct task_struct *target, 1675 const struct user_regset *regset, unsigned int pos, 1676 unsigned int count, const void *kbuf, 1677 const void __user *ubuf) 1678 { 1679 int ret; 1680 compat_ulong_t tls = target->thread.uw.tp_value; 1681 1682 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1); 1683 if (ret) 1684 return ret; 1685 1686 target->thread.uw.tp_value = tls; 1687 return ret; 1688 } 1689 1690 static const struct user_regset aarch32_regsets[] = { 1691 [REGSET_COMPAT_GPR] = { 1692 .core_note_type = NT_PRSTATUS, 1693 .n = COMPAT_ELF_NGREG, 1694 .size = sizeof(compat_elf_greg_t), 1695 .align = sizeof(compat_elf_greg_t), 1696 .regset_get = compat_gpr_get, 1697 .set = compat_gpr_set 1698 }, 1699 [REGSET_COMPAT_VFP] = { 1700 .core_note_type = NT_ARM_VFP, 1701 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1702 .size = sizeof(compat_ulong_t), 1703 .align = sizeof(compat_ulong_t), 1704 .active = fpr_active, 1705 .regset_get = compat_vfp_get, 1706 .set = compat_vfp_set 1707 }, 1708 }; 1709 1710 static const struct user_regset_view user_aarch32_view = { 1711 .name = "aarch32", .e_machine = EM_ARM, 1712 .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets) 1713 }; 1714 1715 static const struct user_regset aarch32_ptrace_regsets[] = { 1716 [REGSET_GPR] = { 1717 .core_note_type = NT_PRSTATUS, 1718 .n = COMPAT_ELF_NGREG, 1719 .size = sizeof(compat_elf_greg_t), 1720 .align = sizeof(compat_elf_greg_t), 1721 .regset_get = compat_gpr_get, 1722 .set = compat_gpr_set 1723 }, 1724 [REGSET_FPR] = { 1725 .core_note_type = NT_ARM_VFP, 1726 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t), 1727 .size = sizeof(compat_ulong_t), 1728 .align = sizeof(compat_ulong_t), 1729 .regset_get = compat_vfp_get, 1730 .set = compat_vfp_set 1731 }, 1732 [REGSET_TLS] = { 1733 .core_note_type = NT_ARM_TLS, 1734 .n = 1, 1735 .size = sizeof(compat_ulong_t), 1736 .align = sizeof(compat_ulong_t), 1737 .regset_get = compat_tls_get, 1738 .set = compat_tls_set, 1739 }, 1740 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1741 [REGSET_HW_BREAK] = { 1742 .core_note_type = NT_ARM_HW_BREAK, 1743 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1744 .size = sizeof(u32), 1745 .align = sizeof(u32), 1746 .regset_get = hw_break_get, 1747 .set = hw_break_set, 1748 }, 1749 [REGSET_HW_WATCH] = { 1750 .core_note_type = NT_ARM_HW_WATCH, 1751 .n = sizeof(struct user_hwdebug_state) / sizeof(u32), 1752 .size = sizeof(u32), 1753 .align = sizeof(u32), 1754 .regset_get = hw_break_get, 1755 .set = hw_break_set, 1756 }, 1757 #endif 1758 [REGSET_SYSTEM_CALL] = { 1759 .core_note_type = NT_ARM_SYSTEM_CALL, 1760 .n = 1, 1761 .size = sizeof(int), 1762 .align = sizeof(int), 1763 .regset_get = system_call_get, 1764 .set = system_call_set, 1765 }, 1766 }; 1767 1768 static const struct user_regset_view user_aarch32_ptrace_view = { 1769 .name = "aarch32", .e_machine = EM_ARM, 1770 .regsets = aarch32_ptrace_regsets, .n = ARRAY_SIZE(aarch32_ptrace_regsets) 1771 }; 1772 1773 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off, 1774 compat_ulong_t __user *ret) 1775 { 1776 compat_ulong_t tmp; 1777 1778 if (off & 3) 1779 return -EIO; 1780 1781 if (off == COMPAT_PT_TEXT_ADDR) 1782 tmp = tsk->mm->start_code; 1783 else if (off == COMPAT_PT_DATA_ADDR) 1784 tmp = tsk->mm->start_data; 1785 else if (off == COMPAT_PT_TEXT_END_ADDR) 1786 tmp = tsk->mm->end_code; 1787 else if (off < sizeof(compat_elf_gregset_t)) 1788 tmp = compat_get_user_reg(tsk, off >> 2); 1789 else if (off >= COMPAT_USER_SZ) 1790 return -EIO; 1791 else 1792 tmp = 0; 1793 1794 return put_user(tmp, ret); 1795 } 1796 1797 static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off, 1798 compat_ulong_t val) 1799 { 1800 struct pt_regs newregs = *task_pt_regs(tsk); 1801 unsigned int idx = off / 4; 1802 1803 if (off & 3 || off >= COMPAT_USER_SZ) 1804 return -EIO; 1805 1806 if (off >= sizeof(compat_elf_gregset_t)) 1807 return 0; 1808 1809 switch (idx) { 1810 case 15: 1811 newregs.pc = val; 1812 break; 1813 case 16: 1814 newregs.pstate = compat_psr_to_pstate(val); 1815 break; 1816 case 17: 1817 newregs.orig_x0 = val; 1818 break; 1819 default: 1820 newregs.regs[idx] = val; 1821 } 1822 1823 if (!valid_user_regs(&newregs.user_regs, tsk)) 1824 return -EINVAL; 1825 1826 *task_pt_regs(tsk) = newregs; 1827 return 0; 1828 } 1829 1830 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1831 1832 /* 1833 * Convert a virtual register number into an index for a thread_info 1834 * breakpoint array. Breakpoints are identified using positive numbers 1835 * whilst watchpoints are negative. The registers are laid out as pairs 1836 * of (address, control), each pair mapping to a unique hw_breakpoint struct. 1837 * Register 0 is reserved for describing resource information. 1838 */ 1839 static int compat_ptrace_hbp_num_to_idx(compat_long_t num) 1840 { 1841 return (abs(num) - 1) >> 1; 1842 } 1843 1844 static int compat_ptrace_hbp_get_resource_info(u32 *kdata) 1845 { 1846 u8 num_brps, num_wrps, debug_arch, wp_len; 1847 u32 reg = 0; 1848 1849 num_brps = hw_breakpoint_slots(TYPE_INST); 1850 num_wrps = hw_breakpoint_slots(TYPE_DATA); 1851 1852 debug_arch = debug_monitors_arch(); 1853 wp_len = 8; 1854 reg |= debug_arch; 1855 reg <<= 8; 1856 reg |= wp_len; 1857 reg <<= 8; 1858 reg |= num_wrps; 1859 reg <<= 8; 1860 reg |= num_brps; 1861 1862 *kdata = reg; 1863 return 0; 1864 } 1865 1866 static int compat_ptrace_hbp_get(unsigned int note_type, 1867 struct task_struct *tsk, 1868 compat_long_t num, 1869 u32 *kdata) 1870 { 1871 u64 addr = 0; 1872 u32 ctrl = 0; 1873 1874 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1875 1876 if (num & 1) { 1877 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr); 1878 *kdata = (u32)addr; 1879 } else { 1880 err = ptrace_hbp_get_ctrl(note_type, tsk, idx, &ctrl); 1881 *kdata = ctrl; 1882 } 1883 1884 return err; 1885 } 1886 1887 static int compat_ptrace_hbp_set(unsigned int note_type, 1888 struct task_struct *tsk, 1889 compat_long_t num, 1890 u32 *kdata) 1891 { 1892 u64 addr; 1893 u32 ctrl; 1894 1895 int err, idx = compat_ptrace_hbp_num_to_idx(num); 1896 1897 if (num & 1) { 1898 addr = *kdata; 1899 err = ptrace_hbp_set_addr(note_type, tsk, idx, addr); 1900 } else { 1901 ctrl = *kdata; 1902 err = ptrace_hbp_set_ctrl(note_type, tsk, idx, ctrl); 1903 } 1904 1905 return err; 1906 } 1907 1908 static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num, 1909 compat_ulong_t __user *data) 1910 { 1911 int ret; 1912 u32 kdata; 1913 1914 /* Watchpoint */ 1915 if (num < 0) { 1916 ret = compat_ptrace_hbp_get(NT_ARM_HW_WATCH, tsk, num, &kdata); 1917 /* Resource info */ 1918 } else if (num == 0) { 1919 ret = compat_ptrace_hbp_get_resource_info(&kdata); 1920 /* Breakpoint */ 1921 } else { 1922 ret = compat_ptrace_hbp_get(NT_ARM_HW_BREAK, tsk, num, &kdata); 1923 } 1924 1925 if (!ret) 1926 ret = put_user(kdata, data); 1927 1928 return ret; 1929 } 1930 1931 static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num, 1932 compat_ulong_t __user *data) 1933 { 1934 int ret; 1935 u32 kdata = 0; 1936 1937 if (num == 0) 1938 return 0; 1939 1940 ret = get_user(kdata, data); 1941 if (ret) 1942 return ret; 1943 1944 if (num < 0) 1945 ret = compat_ptrace_hbp_set(NT_ARM_HW_WATCH, tsk, num, &kdata); 1946 else 1947 ret = compat_ptrace_hbp_set(NT_ARM_HW_BREAK, tsk, num, &kdata); 1948 1949 return ret; 1950 } 1951 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 1952 1953 long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 1954 compat_ulong_t caddr, compat_ulong_t cdata) 1955 { 1956 unsigned long addr = caddr; 1957 unsigned long data = cdata; 1958 void __user *datap = compat_ptr(data); 1959 int ret; 1960 1961 switch (request) { 1962 case PTRACE_PEEKUSR: 1963 ret = compat_ptrace_read_user(child, addr, datap); 1964 break; 1965 1966 case PTRACE_POKEUSR: 1967 ret = compat_ptrace_write_user(child, addr, data); 1968 break; 1969 1970 case COMPAT_PTRACE_GETREGS: 1971 ret = copy_regset_to_user(child, 1972 &user_aarch32_view, 1973 REGSET_COMPAT_GPR, 1974 0, sizeof(compat_elf_gregset_t), 1975 datap); 1976 break; 1977 1978 case COMPAT_PTRACE_SETREGS: 1979 ret = copy_regset_from_user(child, 1980 &user_aarch32_view, 1981 REGSET_COMPAT_GPR, 1982 0, sizeof(compat_elf_gregset_t), 1983 datap); 1984 break; 1985 1986 case COMPAT_PTRACE_GET_THREAD_AREA: 1987 ret = put_user((compat_ulong_t)child->thread.uw.tp_value, 1988 (compat_ulong_t __user *)datap); 1989 break; 1990 1991 case COMPAT_PTRACE_SET_SYSCALL: 1992 task_pt_regs(child)->syscallno = data; 1993 ret = 0; 1994 break; 1995 1996 case COMPAT_PTRACE_GETVFPREGS: 1997 ret = copy_regset_to_user(child, 1998 &user_aarch32_view, 1999 REGSET_COMPAT_VFP, 2000 0, VFP_STATE_SIZE, 2001 datap); 2002 break; 2003 2004 case COMPAT_PTRACE_SETVFPREGS: 2005 ret = copy_regset_from_user(child, 2006 &user_aarch32_view, 2007 REGSET_COMPAT_VFP, 2008 0, VFP_STATE_SIZE, 2009 datap); 2010 break; 2011 2012 #ifdef CONFIG_HAVE_HW_BREAKPOINT 2013 case COMPAT_PTRACE_GETHBPREGS: 2014 ret = compat_ptrace_gethbpregs(child, addr, datap); 2015 break; 2016 2017 case COMPAT_PTRACE_SETHBPREGS: 2018 ret = compat_ptrace_sethbpregs(child, addr, datap); 2019 break; 2020 #endif 2021 2022 default: 2023 ret = compat_ptrace_request(child, request, addr, 2024 data); 2025 break; 2026 } 2027 2028 return ret; 2029 } 2030 #endif /* CONFIG_COMPAT */ 2031 2032 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 2033 { 2034 #ifdef CONFIG_COMPAT 2035 /* 2036 * Core dumping of 32-bit tasks or compat ptrace requests must use the 2037 * user_aarch32_view compatible with arm32. Native ptrace requests on 2038 * 32-bit children use an extended user_aarch32_ptrace_view to allow 2039 * access to the TLS register. 2040 */ 2041 if (is_compat_task()) 2042 return &user_aarch32_view; 2043 else if (is_compat_thread(task_thread_info(task))) 2044 return &user_aarch32_ptrace_view; 2045 #endif 2046 return &user_aarch64_view; 2047 } 2048 2049 long arch_ptrace(struct task_struct *child, long request, 2050 unsigned long addr, unsigned long data) 2051 { 2052 switch (request) { 2053 case PTRACE_PEEKMTETAGS: 2054 case PTRACE_POKEMTETAGS: 2055 return mte_ptrace_copy_tags(child, request, addr, data); 2056 } 2057 2058 return ptrace_request(child, request, addr, data); 2059 } 2060 2061 enum ptrace_syscall_dir { 2062 PTRACE_SYSCALL_ENTER = 0, 2063 PTRACE_SYSCALL_EXIT, 2064 }; 2065 2066 static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir) 2067 { 2068 int regno; 2069 unsigned long saved_reg; 2070 2071 /* 2072 * We have some ABI weirdness here in the way that we handle syscall 2073 * exit stops because we indicate whether or not the stop has been 2074 * signalled from syscall entry or syscall exit by clobbering a general 2075 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee 2076 * and restoring its old value after the stop. This means that: 2077 * 2078 * - Any writes by the tracer to this register during the stop are 2079 * ignored/discarded. 2080 * 2081 * - The actual value of the register is not available during the stop, 2082 * so the tracer cannot save it and restore it later. 2083 * 2084 * - Syscall stops behave differently to seccomp and pseudo-step traps 2085 * (the latter do not nobble any registers). 2086 */ 2087 regno = (is_compat_task() ? 12 : 7); 2088 saved_reg = regs->regs[regno]; 2089 regs->regs[regno] = dir; 2090 2091 if (dir == PTRACE_SYSCALL_ENTER) { 2092 if (ptrace_report_syscall_entry(regs)) 2093 forget_syscall(regs); 2094 regs->regs[regno] = saved_reg; 2095 } else if (!test_thread_flag(TIF_SINGLESTEP)) { 2096 ptrace_report_syscall_exit(regs, 0); 2097 regs->regs[regno] = saved_reg; 2098 } else { 2099 regs->regs[regno] = saved_reg; 2100 2101 /* 2102 * Signal a pseudo-step exception since we are stepping but 2103 * tracer modifications to the registers may have rewound the 2104 * state machine. 2105 */ 2106 ptrace_report_syscall_exit(regs, 1); 2107 } 2108 } 2109 2110 int syscall_trace_enter(struct pt_regs *regs) 2111 { 2112 unsigned long flags = read_thread_flags(); 2113 2114 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) { 2115 report_syscall(regs, PTRACE_SYSCALL_ENTER); 2116 if (flags & _TIF_SYSCALL_EMU) 2117 return NO_SYSCALL; 2118 } 2119 2120 /* Do the secure computing after ptrace; failures should be fast. */ 2121 if (secure_computing() == -1) 2122 return NO_SYSCALL; 2123 2124 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) 2125 trace_sys_enter(regs, regs->syscallno); 2126 2127 audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1], 2128 regs->regs[2], regs->regs[3]); 2129 2130 return regs->syscallno; 2131 } 2132 2133 void syscall_trace_exit(struct pt_regs *regs) 2134 { 2135 unsigned long flags = read_thread_flags(); 2136 2137 audit_syscall_exit(regs); 2138 2139 if (flags & _TIF_SYSCALL_TRACEPOINT) 2140 trace_sys_exit(regs, syscall_get_return_value(current, regs)); 2141 2142 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) 2143 report_syscall(regs, PTRACE_SYSCALL_EXIT); 2144 2145 rseq_syscall(regs); 2146 } 2147 2148 /* 2149 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a. 2150 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is 2151 * not described in ARM DDI 0487D.a. 2152 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may 2153 * be allocated an EL0 meaning in future. 2154 * Userspace cannot use these until they have an architectural meaning. 2155 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format. 2156 * We also reserve IL for the kernel; SS is handled dynamically. 2157 */ 2158 #define SPSR_EL1_AARCH64_RES0_BITS \ 2159 (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \ 2160 GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5)) 2161 #define SPSR_EL1_AARCH32_RES0_BITS \ 2162 (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20)) 2163 2164 static int valid_compat_regs(struct user_pt_regs *regs) 2165 { 2166 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; 2167 2168 if (!system_supports_mixed_endian_el0()) { 2169 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 2170 regs->pstate |= PSR_AA32_E_BIT; 2171 else 2172 regs->pstate &= ~PSR_AA32_E_BIT; 2173 } 2174 2175 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) && 2176 (regs->pstate & PSR_AA32_A_BIT) == 0 && 2177 (regs->pstate & PSR_AA32_I_BIT) == 0 && 2178 (regs->pstate & PSR_AA32_F_BIT) == 0) { 2179 return 1; 2180 } 2181 2182 /* 2183 * Force PSR to a valid 32-bit EL0t, preserving the same bits as 2184 * arch/arm. 2185 */ 2186 regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT | 2187 PSR_AA32_C_BIT | PSR_AA32_V_BIT | 2188 PSR_AA32_Q_BIT | PSR_AA32_IT_MASK | 2189 PSR_AA32_GE_MASK | PSR_AA32_E_BIT | 2190 PSR_AA32_T_BIT; 2191 regs->pstate |= PSR_MODE32_BIT; 2192 2193 return 0; 2194 } 2195 2196 static int valid_native_regs(struct user_pt_regs *regs) 2197 { 2198 regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; 2199 2200 if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) && 2201 (regs->pstate & PSR_D_BIT) == 0 && 2202 (regs->pstate & PSR_A_BIT) == 0 && 2203 (regs->pstate & PSR_I_BIT) == 0 && 2204 (regs->pstate & PSR_F_BIT) == 0) { 2205 return 1; 2206 } 2207 2208 /* Force PSR to a valid 64-bit EL0t */ 2209 regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; 2210 2211 return 0; 2212 } 2213 2214 /* 2215 * Are the current registers suitable for user mode? (used to maintain 2216 * security in signal handlers) 2217 */ 2218 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task) 2219 { 2220 /* https://lore.kernel.org/lkml/20191118131525.GA4180@willie-the-truck */ 2221 user_regs_reset_single_step(regs, task); 2222 2223 if (is_compat_thread(task_thread_info(task))) 2224 return valid_compat_regs(regs); 2225 else 2226 return valid_native_regs(regs); 2227 } 2228