xref: /openbmc/linux/arch/arm64/kernel/process.c (revision d2574c33)
1 /*
2  * Based on arch/arm/kernel/process.c
3  *
4  * Original Copyright (C) 1995  Linus Torvalds
5  * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6  * Copyright (C) 2012 ARM Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include <stdarg.h>
22 
23 #include <linux/compat.h>
24 #include <linux/efi.h>
25 #include <linux/export.h>
26 #include <linux/sched.h>
27 #include <linux/sched/debug.h>
28 #include <linux/sched/task.h>
29 #include <linux/sched/task_stack.h>
30 #include <linux/kernel.h>
31 #include <linux/mm.h>
32 #include <linux/stddef.h>
33 #include <linux/unistd.h>
34 #include <linux/user.h>
35 #include <linux/delay.h>
36 #include <linux/reboot.h>
37 #include <linux/interrupt.h>
38 #include <linux/init.h>
39 #include <linux/cpu.h>
40 #include <linux/elfcore.h>
41 #include <linux/pm.h>
42 #include <linux/tick.h>
43 #include <linux/utsname.h>
44 #include <linux/uaccess.h>
45 #include <linux/random.h>
46 #include <linux/hw_breakpoint.h>
47 #include <linux/personality.h>
48 #include <linux/notifier.h>
49 #include <trace/events/power.h>
50 #include <linux/percpu.h>
51 #include <linux/thread_info.h>
52 
53 #include <asm/alternative.h>
54 #include <asm/arch_gicv3.h>
55 #include <asm/compat.h>
56 #include <asm/cacheflush.h>
57 #include <asm/exec.h>
58 #include <asm/fpsimd.h>
59 #include <asm/mmu_context.h>
60 #include <asm/processor.h>
61 #include <asm/pointer_auth.h>
62 #include <asm/stacktrace.h>
63 
64 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
65 #include <linux/stackprotector.h>
66 unsigned long __stack_chk_guard __read_mostly;
67 EXPORT_SYMBOL(__stack_chk_guard);
68 #endif
69 
70 /*
71  * Function pointers to optional machine specific functions
72  */
73 void (*pm_power_off)(void);
74 EXPORT_SYMBOL_GPL(pm_power_off);
75 
76 void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
77 
78 static void __cpu_do_idle(void)
79 {
80 	dsb(sy);
81 	wfi();
82 }
83 
84 static void __cpu_do_idle_irqprio(void)
85 {
86 	unsigned long pmr;
87 	unsigned long daif_bits;
88 
89 	daif_bits = read_sysreg(daif);
90 	write_sysreg(daif_bits | PSR_I_BIT, daif);
91 
92 	/*
93 	 * Unmask PMR before going idle to make sure interrupts can
94 	 * be raised.
95 	 */
96 	pmr = gic_read_pmr();
97 	gic_write_pmr(GIC_PRIO_IRQON);
98 
99 	__cpu_do_idle();
100 
101 	gic_write_pmr(pmr);
102 	write_sysreg(daif_bits, daif);
103 }
104 
105 /*
106  *	cpu_do_idle()
107  *
108  *	Idle the processor (wait for interrupt).
109  *
110  *	If the CPU supports priority masking we must do additional work to
111  *	ensure that interrupts are not masked at the PMR (because the core will
112  *	not wake up if we block the wake up signal in the interrupt controller).
113  */
114 void cpu_do_idle(void)
115 {
116 	if (system_uses_irq_prio_masking())
117 		__cpu_do_idle_irqprio();
118 	else
119 		__cpu_do_idle();
120 }
121 
122 /*
123  * This is our default idle handler.
124  */
125 void arch_cpu_idle(void)
126 {
127 	/*
128 	 * This should do all the clock switching and wait for interrupt
129 	 * tricks
130 	 */
131 	trace_cpu_idle_rcuidle(1, smp_processor_id());
132 	cpu_do_idle();
133 	local_irq_enable();
134 	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
135 }
136 
137 #ifdef CONFIG_HOTPLUG_CPU
138 void arch_cpu_idle_dead(void)
139 {
140        cpu_die();
141 }
142 #endif
143 
144 /*
145  * Called by kexec, immediately prior to machine_kexec().
146  *
147  * This must completely disable all secondary CPUs; simply causing those CPUs
148  * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
149  * kexec'd kernel to use any and all RAM as it sees fit, without having to
150  * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
151  * functionality embodied in disable_nonboot_cpus() to achieve this.
152  */
153 void machine_shutdown(void)
154 {
155 	disable_nonboot_cpus();
156 }
157 
158 /*
159  * Halting simply requires that the secondary CPUs stop performing any
160  * activity (executing tasks, handling interrupts). smp_send_stop()
161  * achieves this.
162  */
163 void machine_halt(void)
164 {
165 	local_irq_disable();
166 	smp_send_stop();
167 	while (1);
168 }
169 
170 /*
171  * Power-off simply requires that the secondary CPUs stop performing any
172  * activity (executing tasks, handling interrupts). smp_send_stop()
173  * achieves this. When the system power is turned off, it will take all CPUs
174  * with it.
175  */
176 void machine_power_off(void)
177 {
178 	local_irq_disable();
179 	smp_send_stop();
180 	if (pm_power_off)
181 		pm_power_off();
182 }
183 
184 /*
185  * Restart requires that the secondary CPUs stop performing any activity
186  * while the primary CPU resets the system. Systems with multiple CPUs must
187  * provide a HW restart implementation, to ensure that all CPUs reset at once.
188  * This is required so that any code running after reset on the primary CPU
189  * doesn't have to co-ordinate with other CPUs to ensure they aren't still
190  * executing pre-reset code, and using RAM that the primary CPU's code wishes
191  * to use. Implementing such co-ordination would be essentially impossible.
192  */
193 void machine_restart(char *cmd)
194 {
195 	/* Disable interrupts first */
196 	local_irq_disable();
197 	smp_send_stop();
198 
199 	/*
200 	 * UpdateCapsule() depends on the system being reset via
201 	 * ResetSystem().
202 	 */
203 	if (efi_enabled(EFI_RUNTIME_SERVICES))
204 		efi_reboot(reboot_mode, NULL);
205 
206 	/* Now call the architecture specific reboot code. */
207 	if (arm_pm_restart)
208 		arm_pm_restart(reboot_mode, cmd);
209 	else
210 		do_kernel_restart(cmd);
211 
212 	/*
213 	 * Whoops - the architecture was unable to reboot.
214 	 */
215 	printk("Reboot failed -- System halted\n");
216 	while (1);
217 }
218 
219 static void print_pstate(struct pt_regs *regs)
220 {
221 	u64 pstate = regs->pstate;
222 
223 	if (compat_user_mode(regs)) {
224 		printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c)\n",
225 			pstate,
226 			pstate & PSR_AA32_N_BIT ? 'N' : 'n',
227 			pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
228 			pstate & PSR_AA32_C_BIT ? 'C' : 'c',
229 			pstate & PSR_AA32_V_BIT ? 'V' : 'v',
230 			pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
231 			pstate & PSR_AA32_T_BIT ? "T32" : "A32",
232 			pstate & PSR_AA32_E_BIT ? "BE" : "LE",
233 			pstate & PSR_AA32_A_BIT ? 'A' : 'a',
234 			pstate & PSR_AA32_I_BIT ? 'I' : 'i',
235 			pstate & PSR_AA32_F_BIT ? 'F' : 'f');
236 	} else {
237 		printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO)\n",
238 			pstate,
239 			pstate & PSR_N_BIT ? 'N' : 'n',
240 			pstate & PSR_Z_BIT ? 'Z' : 'z',
241 			pstate & PSR_C_BIT ? 'C' : 'c',
242 			pstate & PSR_V_BIT ? 'V' : 'v',
243 			pstate & PSR_D_BIT ? 'D' : 'd',
244 			pstate & PSR_A_BIT ? 'A' : 'a',
245 			pstate & PSR_I_BIT ? 'I' : 'i',
246 			pstate & PSR_F_BIT ? 'F' : 'f',
247 			pstate & PSR_PAN_BIT ? '+' : '-',
248 			pstate & PSR_UAO_BIT ? '+' : '-');
249 	}
250 }
251 
252 void __show_regs(struct pt_regs *regs)
253 {
254 	int i, top_reg;
255 	u64 lr, sp;
256 
257 	if (compat_user_mode(regs)) {
258 		lr = regs->compat_lr;
259 		sp = regs->compat_sp;
260 		top_reg = 12;
261 	} else {
262 		lr = regs->regs[30];
263 		sp = regs->sp;
264 		top_reg = 29;
265 	}
266 
267 	show_regs_print_info(KERN_DEFAULT);
268 	print_pstate(regs);
269 
270 	if (!user_mode(regs)) {
271 		printk("pc : %pS\n", (void *)regs->pc);
272 		printk("lr : %pS\n", (void *)lr);
273 	} else {
274 		printk("pc : %016llx\n", regs->pc);
275 		printk("lr : %016llx\n", lr);
276 	}
277 
278 	printk("sp : %016llx\n", sp);
279 
280 	if (system_uses_irq_prio_masking())
281 		printk("pmr_save: %08llx\n", regs->pmr_save);
282 
283 	i = top_reg;
284 
285 	while (i >= 0) {
286 		printk("x%-2d: %016llx ", i, regs->regs[i]);
287 		i--;
288 
289 		if (i % 2 == 0) {
290 			pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
291 			i--;
292 		}
293 
294 		pr_cont("\n");
295 	}
296 }
297 
298 void show_regs(struct pt_regs * regs)
299 {
300 	__show_regs(regs);
301 	dump_backtrace(regs, NULL);
302 }
303 
304 static void tls_thread_flush(void)
305 {
306 	write_sysreg(0, tpidr_el0);
307 
308 	if (is_compat_task()) {
309 		current->thread.uw.tp_value = 0;
310 
311 		/*
312 		 * We need to ensure ordering between the shadow state and the
313 		 * hardware state, so that we don't corrupt the hardware state
314 		 * with a stale shadow state during context switch.
315 		 */
316 		barrier();
317 		write_sysreg(0, tpidrro_el0);
318 	}
319 }
320 
321 void flush_thread(void)
322 {
323 	fpsimd_flush_thread();
324 	tls_thread_flush();
325 	flush_ptrace_hw_breakpoint(current);
326 }
327 
328 void release_thread(struct task_struct *dead_task)
329 {
330 }
331 
332 void arch_release_task_struct(struct task_struct *tsk)
333 {
334 	fpsimd_release_task(tsk);
335 }
336 
337 /*
338  * src and dst may temporarily have aliased sve_state after task_struct
339  * is copied.  We cannot fix this properly here, because src may have
340  * live SVE state and dst's thread_info may not exist yet, so tweaking
341  * either src's or dst's TIF_SVE is not safe.
342  *
343  * The unaliasing is done in copy_thread() instead.  This works because
344  * dst is not schedulable or traceable until both of these functions
345  * have been called.
346  */
347 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
348 {
349 	if (current->mm)
350 		fpsimd_preserve_current_state();
351 	*dst = *src;
352 
353 	return 0;
354 }
355 
356 asmlinkage void ret_from_fork(void) asm("ret_from_fork");
357 
358 int copy_thread(unsigned long clone_flags, unsigned long stack_start,
359 		unsigned long stk_sz, struct task_struct *p)
360 {
361 	struct pt_regs *childregs = task_pt_regs(p);
362 
363 	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
364 
365 	/*
366 	 * Unalias p->thread.sve_state (if any) from the parent task
367 	 * and disable discard SVE state for p:
368 	 */
369 	clear_tsk_thread_flag(p, TIF_SVE);
370 	p->thread.sve_state = NULL;
371 
372 	/*
373 	 * In case p was allocated the same task_struct pointer as some
374 	 * other recently-exited task, make sure p is disassociated from
375 	 * any cpu that may have run that now-exited task recently.
376 	 * Otherwise we could erroneously skip reloading the FPSIMD
377 	 * registers for p.
378 	 */
379 	fpsimd_flush_task_state(p);
380 
381 	if (likely(!(p->flags & PF_KTHREAD))) {
382 		*childregs = *current_pt_regs();
383 		childregs->regs[0] = 0;
384 
385 		/*
386 		 * Read the current TLS pointer from tpidr_el0 as it may be
387 		 * out-of-sync with the saved value.
388 		 */
389 		*task_user_tls(p) = read_sysreg(tpidr_el0);
390 
391 		if (stack_start) {
392 			if (is_compat_thread(task_thread_info(p)))
393 				childregs->compat_sp = stack_start;
394 			else
395 				childregs->sp = stack_start;
396 		}
397 
398 		/*
399 		 * If a TLS pointer was passed to clone (4th argument), use it
400 		 * for the new thread.
401 		 */
402 		if (clone_flags & CLONE_SETTLS)
403 			p->thread.uw.tp_value = childregs->regs[3];
404 	} else {
405 		memset(childregs, 0, sizeof(struct pt_regs));
406 		childregs->pstate = PSR_MODE_EL1h;
407 		if (IS_ENABLED(CONFIG_ARM64_UAO) &&
408 		    cpus_have_const_cap(ARM64_HAS_UAO))
409 			childregs->pstate |= PSR_UAO_BIT;
410 
411 		if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE)
412 			childregs->pstate |= PSR_SSBS_BIT;
413 
414 		if (system_uses_irq_prio_masking())
415 			childregs->pmr_save = GIC_PRIO_IRQON;
416 
417 		p->thread.cpu_context.x19 = stack_start;
418 		p->thread.cpu_context.x20 = stk_sz;
419 	}
420 	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
421 	p->thread.cpu_context.sp = (unsigned long)childregs;
422 
423 	ptrace_hw_copy_thread(p);
424 
425 	return 0;
426 }
427 
428 void tls_preserve_current_state(void)
429 {
430 	*task_user_tls(current) = read_sysreg(tpidr_el0);
431 }
432 
433 static void tls_thread_switch(struct task_struct *next)
434 {
435 	tls_preserve_current_state();
436 
437 	if (is_compat_thread(task_thread_info(next)))
438 		write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
439 	else if (!arm64_kernel_unmapped_at_el0())
440 		write_sysreg(0, tpidrro_el0);
441 
442 	write_sysreg(*task_user_tls(next), tpidr_el0);
443 }
444 
445 /* Restore the UAO state depending on next's addr_limit */
446 void uao_thread_switch(struct task_struct *next)
447 {
448 	if (IS_ENABLED(CONFIG_ARM64_UAO)) {
449 		if (task_thread_info(next)->addr_limit == KERNEL_DS)
450 			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
451 		else
452 			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
453 	}
454 }
455 
456 /*
457  * We store our current task in sp_el0, which is clobbered by userspace. Keep a
458  * shadow copy so that we can restore this upon entry from userspace.
459  *
460  * This is *only* for exception entry from EL0, and is not valid until we
461  * __switch_to() a user task.
462  */
463 DEFINE_PER_CPU(struct task_struct *, __entry_task);
464 
465 static void entry_task_switch(struct task_struct *next)
466 {
467 	__this_cpu_write(__entry_task, next);
468 }
469 
470 /*
471  * Thread switching.
472  */
473 __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
474 				struct task_struct *next)
475 {
476 	struct task_struct *last;
477 
478 	fpsimd_thread_switch(next);
479 	tls_thread_switch(next);
480 	hw_breakpoint_thread_switch(next);
481 	contextidr_thread_switch(next);
482 	entry_task_switch(next);
483 	uao_thread_switch(next);
484 	ptrauth_thread_switch(next);
485 
486 	/*
487 	 * Complete any pending TLB or cache maintenance on this CPU in case
488 	 * the thread migrates to a different CPU.
489 	 * This full barrier is also required by the membarrier system
490 	 * call.
491 	 */
492 	dsb(ish);
493 
494 	/* the actual thread switch */
495 	last = cpu_switch_to(prev, next);
496 
497 	return last;
498 }
499 
500 unsigned long get_wchan(struct task_struct *p)
501 {
502 	struct stackframe frame;
503 	unsigned long stack_page, ret = 0;
504 	int count = 0;
505 	if (!p || p == current || p->state == TASK_RUNNING)
506 		return 0;
507 
508 	stack_page = (unsigned long)try_get_task_stack(p);
509 	if (!stack_page)
510 		return 0;
511 
512 	frame.fp = thread_saved_fp(p);
513 	frame.pc = thread_saved_pc(p);
514 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
515 	frame.graph = 0;
516 #endif
517 	do {
518 		if (unwind_frame(p, &frame))
519 			goto out;
520 		if (!in_sched_functions(frame.pc)) {
521 			ret = frame.pc;
522 			goto out;
523 		}
524 	} while (count ++ < 16);
525 
526 out:
527 	put_task_stack(p);
528 	return ret;
529 }
530 
531 unsigned long arch_align_stack(unsigned long sp)
532 {
533 	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
534 		sp -= get_random_int() & ~PAGE_MASK;
535 	return sp & ~0xf;
536 }
537 
538 unsigned long arch_randomize_brk(struct mm_struct *mm)
539 {
540 	if (is_compat_task())
541 		return randomize_page(mm->brk, SZ_32M);
542 	else
543 		return randomize_page(mm->brk, SZ_1G);
544 }
545 
546 /*
547  * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
548  */
549 void arch_setup_new_exec(void)
550 {
551 	current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;
552 
553 	ptrauth_thread_init_user(current);
554 }
555