xref: /openbmc/linux/arch/arm64/kernel/process.c (revision 52c291a3)
1 /*
2  * Based on arch/arm/kernel/process.c
3  *
4  * Original Copyright (C) 1995  Linus Torvalds
5  * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6  * Copyright (C) 2012 ARM Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include <stdarg.h>
22 
23 #include <linux/compat.h>
24 #include <linux/efi.h>
25 #include <linux/export.h>
26 #include <linux/sched.h>
27 #include <linux/sched/debug.h>
28 #include <linux/sched/task.h>
29 #include <linux/sched/task_stack.h>
30 #include <linux/kernel.h>
31 #include <linux/mm.h>
32 #include <linux/stddef.h>
33 #include <linux/unistd.h>
34 #include <linux/user.h>
35 #include <linux/delay.h>
36 #include <linux/reboot.h>
37 #include <linux/interrupt.h>
38 #include <linux/kallsyms.h>
39 #include <linux/init.h>
40 #include <linux/cpu.h>
41 #include <linux/elfcore.h>
42 #include <linux/pm.h>
43 #include <linux/tick.h>
44 #include <linux/utsname.h>
45 #include <linux/uaccess.h>
46 #include <linux/random.h>
47 #include <linux/hw_breakpoint.h>
48 #include <linux/personality.h>
49 #include <linux/notifier.h>
50 #include <trace/events/power.h>
51 #include <linux/percpu.h>
52 
53 #include <asm/alternative.h>
54 #include <asm/compat.h>
55 #include <asm/cacheflush.h>
56 #include <asm/exec.h>
57 #include <asm/fpsimd.h>
58 #include <asm/mmu_context.h>
59 #include <asm/processor.h>
60 #include <asm/stacktrace.h>
61 
62 #ifdef CONFIG_CC_STACKPROTECTOR
63 #include <linux/stackprotector.h>
64 unsigned long __stack_chk_guard __read_mostly;
65 EXPORT_SYMBOL(__stack_chk_guard);
66 #endif
67 
68 /*
69  * Function pointers to optional machine specific functions
70  */
71 void (*pm_power_off)(void);
72 EXPORT_SYMBOL_GPL(pm_power_off);
73 
74 void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
75 
76 /*
77  * This is our default idle handler.
78  */
79 void arch_cpu_idle(void)
80 {
81 	/*
82 	 * This should do all the clock switching and wait for interrupt
83 	 * tricks
84 	 */
85 	trace_cpu_idle_rcuidle(1, smp_processor_id());
86 	cpu_do_idle();
87 	local_irq_enable();
88 	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
89 }
90 
91 #ifdef CONFIG_HOTPLUG_CPU
92 void arch_cpu_idle_dead(void)
93 {
94        cpu_die();
95 }
96 #endif
97 
98 /*
99  * Called by kexec, immediately prior to machine_kexec().
100  *
101  * This must completely disable all secondary CPUs; simply causing those CPUs
102  * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
103  * kexec'd kernel to use any and all RAM as it sees fit, without having to
104  * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
105  * functionality embodied in disable_nonboot_cpus() to achieve this.
106  */
107 void machine_shutdown(void)
108 {
109 	disable_nonboot_cpus();
110 }
111 
112 /*
113  * Halting simply requires that the secondary CPUs stop performing any
114  * activity (executing tasks, handling interrupts). smp_send_stop()
115  * achieves this.
116  */
117 void machine_halt(void)
118 {
119 	local_irq_disable();
120 	smp_send_stop();
121 	while (1);
122 }
123 
124 /*
125  * Power-off simply requires that the secondary CPUs stop performing any
126  * activity (executing tasks, handling interrupts). smp_send_stop()
127  * achieves this. When the system power is turned off, it will take all CPUs
128  * with it.
129  */
130 void machine_power_off(void)
131 {
132 	local_irq_disable();
133 	smp_send_stop();
134 	if (pm_power_off)
135 		pm_power_off();
136 }
137 
138 /*
139  * Restart requires that the secondary CPUs stop performing any activity
140  * while the primary CPU resets the system. Systems with multiple CPUs must
141  * provide a HW restart implementation, to ensure that all CPUs reset at once.
142  * This is required so that any code running after reset on the primary CPU
143  * doesn't have to co-ordinate with other CPUs to ensure they aren't still
144  * executing pre-reset code, and using RAM that the primary CPU's code wishes
145  * to use. Implementing such co-ordination would be essentially impossible.
146  */
147 void machine_restart(char *cmd)
148 {
149 	/* Disable interrupts first */
150 	local_irq_disable();
151 	smp_send_stop();
152 
153 	/*
154 	 * UpdateCapsule() depends on the system being reset via
155 	 * ResetSystem().
156 	 */
157 	if (efi_enabled(EFI_RUNTIME_SERVICES))
158 		efi_reboot(reboot_mode, NULL);
159 
160 	/* Now call the architecture specific reboot code. */
161 	if (arm_pm_restart)
162 		arm_pm_restart(reboot_mode, cmd);
163 	else
164 		do_kernel_restart(cmd);
165 
166 	/*
167 	 * Whoops - the architecture was unable to reboot.
168 	 */
169 	printk("Reboot failed -- System halted\n");
170 	while (1);
171 }
172 
173 void __show_regs(struct pt_regs *regs)
174 {
175 	int i, top_reg;
176 	u64 lr, sp;
177 
178 	if (compat_user_mode(regs)) {
179 		lr = regs->compat_lr;
180 		sp = regs->compat_sp;
181 		top_reg = 12;
182 	} else {
183 		lr = regs->regs[30];
184 		sp = regs->sp;
185 		top_reg = 29;
186 	}
187 
188 	show_regs_print_info(KERN_DEFAULT);
189 	print_symbol("PC is at %s\n", instruction_pointer(regs));
190 	print_symbol("LR is at %s\n", lr);
191 	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
192 	       regs->pc, lr, regs->pstate);
193 	printk("sp : %016llx\n", sp);
194 
195 	i = top_reg;
196 
197 	while (i >= 0) {
198 		printk("x%-2d: %016llx ", i, regs->regs[i]);
199 		i--;
200 
201 		if (i % 2 == 0) {
202 			pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
203 			i--;
204 		}
205 
206 		pr_cont("\n");
207 	}
208 }
209 
210 void show_regs(struct pt_regs * regs)
211 {
212 	__show_regs(regs);
213 	dump_backtrace(regs, NULL);
214 }
215 
216 static void tls_thread_flush(void)
217 {
218 	write_sysreg(0, tpidr_el0);
219 
220 	if (is_compat_task()) {
221 		current->thread.tp_value = 0;
222 
223 		/*
224 		 * We need to ensure ordering between the shadow state and the
225 		 * hardware state, so that we don't corrupt the hardware state
226 		 * with a stale shadow state during context switch.
227 		 */
228 		barrier();
229 		write_sysreg(0, tpidrro_el0);
230 	}
231 }
232 
233 void flush_thread(void)
234 {
235 	fpsimd_flush_thread();
236 	tls_thread_flush();
237 	flush_ptrace_hw_breakpoint(current);
238 }
239 
240 void release_thread(struct task_struct *dead_task)
241 {
242 }
243 
244 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
245 {
246 	if (current->mm)
247 		fpsimd_preserve_current_state();
248 	*dst = *src;
249 	return 0;
250 }
251 
252 asmlinkage void ret_from_fork(void) asm("ret_from_fork");
253 
254 int copy_thread(unsigned long clone_flags, unsigned long stack_start,
255 		unsigned long stk_sz, struct task_struct *p)
256 {
257 	struct pt_regs *childregs = task_pt_regs(p);
258 
259 	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
260 
261 	if (likely(!(p->flags & PF_KTHREAD))) {
262 		*childregs = *current_pt_regs();
263 		childregs->regs[0] = 0;
264 
265 		/*
266 		 * Read the current TLS pointer from tpidr_el0 as it may be
267 		 * out-of-sync with the saved value.
268 		 */
269 		*task_user_tls(p) = read_sysreg(tpidr_el0);
270 
271 		if (stack_start) {
272 			if (is_compat_thread(task_thread_info(p)))
273 				childregs->compat_sp = stack_start;
274 			else
275 				childregs->sp = stack_start;
276 		}
277 
278 		/*
279 		 * If a TLS pointer was passed to clone (4th argument), use it
280 		 * for the new thread.
281 		 */
282 		if (clone_flags & CLONE_SETTLS)
283 			p->thread.tp_value = childregs->regs[3];
284 	} else {
285 		memset(childregs, 0, sizeof(struct pt_regs));
286 		childregs->pstate = PSR_MODE_EL1h;
287 		if (IS_ENABLED(CONFIG_ARM64_UAO) &&
288 		    cpus_have_const_cap(ARM64_HAS_UAO))
289 			childregs->pstate |= PSR_UAO_BIT;
290 		p->thread.cpu_context.x19 = stack_start;
291 		p->thread.cpu_context.x20 = stk_sz;
292 	}
293 	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
294 	p->thread.cpu_context.sp = (unsigned long)childregs;
295 
296 	ptrace_hw_copy_thread(p);
297 
298 	return 0;
299 }
300 
301 void tls_preserve_current_state(void)
302 {
303 	*task_user_tls(current) = read_sysreg(tpidr_el0);
304 }
305 
306 static void tls_thread_switch(struct task_struct *next)
307 {
308 	unsigned long tpidr, tpidrro;
309 
310 	tls_preserve_current_state();
311 
312 	tpidr = *task_user_tls(next);
313 	tpidrro = is_compat_thread(task_thread_info(next)) ?
314 		  next->thread.tp_value : 0;
315 
316 	write_sysreg(tpidr, tpidr_el0);
317 	write_sysreg(tpidrro, tpidrro_el0);
318 }
319 
320 /* Restore the UAO state depending on next's addr_limit */
321 void uao_thread_switch(struct task_struct *next)
322 {
323 	if (IS_ENABLED(CONFIG_ARM64_UAO)) {
324 		if (task_thread_info(next)->addr_limit == KERNEL_DS)
325 			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
326 		else
327 			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
328 	}
329 }
330 
331 /*
332  * We store our current task in sp_el0, which is clobbered by userspace. Keep a
333  * shadow copy so that we can restore this upon entry from userspace.
334  *
335  * This is *only* for exception entry from EL0, and is not valid until we
336  * __switch_to() a user task.
337  */
338 DEFINE_PER_CPU(struct task_struct *, __entry_task);
339 
340 static void entry_task_switch(struct task_struct *next)
341 {
342 	__this_cpu_write(__entry_task, next);
343 }
344 
345 /*
346  * Thread switching.
347  */
348 __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
349 				struct task_struct *next)
350 {
351 	struct task_struct *last;
352 
353 	fpsimd_thread_switch(next);
354 	tls_thread_switch(next);
355 	hw_breakpoint_thread_switch(next);
356 	contextidr_thread_switch(next);
357 	entry_task_switch(next);
358 	uao_thread_switch(next);
359 
360 	/*
361 	 * Complete any pending TLB or cache maintenance on this CPU in case
362 	 * the thread migrates to a different CPU.
363 	 * This full barrier is also required by the membarrier system
364 	 * call.
365 	 */
366 	dsb(ish);
367 
368 	/* the actual thread switch */
369 	last = cpu_switch_to(prev, next);
370 
371 	return last;
372 }
373 
374 unsigned long get_wchan(struct task_struct *p)
375 {
376 	struct stackframe frame;
377 	unsigned long stack_page, ret = 0;
378 	int count = 0;
379 	if (!p || p == current || p->state == TASK_RUNNING)
380 		return 0;
381 
382 	stack_page = (unsigned long)try_get_task_stack(p);
383 	if (!stack_page)
384 		return 0;
385 
386 	frame.fp = thread_saved_fp(p);
387 	frame.pc = thread_saved_pc(p);
388 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
389 	frame.graph = p->curr_ret_stack;
390 #endif
391 	do {
392 		if (unwind_frame(p, &frame))
393 			goto out;
394 		if (!in_sched_functions(frame.pc)) {
395 			ret = frame.pc;
396 			goto out;
397 		}
398 	} while (count ++ < 16);
399 
400 out:
401 	put_task_stack(p);
402 	return ret;
403 }
404 
405 unsigned long arch_align_stack(unsigned long sp)
406 {
407 	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
408 		sp -= get_random_int() & ~PAGE_MASK;
409 	return sp & ~0xf;
410 }
411 
412 unsigned long arch_randomize_brk(struct mm_struct *mm)
413 {
414 	if (is_compat_task())
415 		return randomize_page(mm->brk, SZ_32M);
416 	else
417 		return randomize_page(mm->brk, SZ_1G);
418 }
419 
420 /*
421  * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
422  */
423 void arch_setup_new_exec(void)
424 {
425 	current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;
426 }
427