1 /* 2 * AArch64 loadable module support. 3 * 4 * Copyright (C) 2012 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: Will Deacon <will.deacon@arm.com> 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/elf.h> 23 #include <linux/gfp.h> 24 #include <linux/kernel.h> 25 #include <linux/mm.h> 26 #include <linux/moduleloader.h> 27 #include <linux/vmalloc.h> 28 #include <asm/insn.h> 29 #include <asm/sections.h> 30 31 #define AARCH64_INSN_IMM_MOVNZ AARCH64_INSN_IMM_MAX 32 #define AARCH64_INSN_IMM_MOVK AARCH64_INSN_IMM_16 33 34 void *module_alloc(unsigned long size) 35 { 36 return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, 37 GFP_KERNEL, PAGE_KERNEL_EXEC, NUMA_NO_NODE, 38 __builtin_return_address(0)); 39 } 40 41 enum aarch64_reloc_op { 42 RELOC_OP_NONE, 43 RELOC_OP_ABS, 44 RELOC_OP_PREL, 45 RELOC_OP_PAGE, 46 }; 47 48 static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val) 49 { 50 switch (reloc_op) { 51 case RELOC_OP_ABS: 52 return val; 53 case RELOC_OP_PREL: 54 return val - (u64)place; 55 case RELOC_OP_PAGE: 56 return (val & ~0xfff) - ((u64)place & ~0xfff); 57 case RELOC_OP_NONE: 58 return 0; 59 } 60 61 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op); 62 return 0; 63 } 64 65 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) 66 { 67 u64 imm_mask = (1 << len) - 1; 68 s64 sval = do_reloc(op, place, val); 69 70 switch (len) { 71 case 16: 72 *(s16 *)place = sval; 73 break; 74 case 32: 75 *(s32 *)place = sval; 76 break; 77 case 64: 78 *(s64 *)place = sval; 79 break; 80 default: 81 pr_err("Invalid length (%d) for data relocation\n", len); 82 return 0; 83 } 84 85 /* 86 * Extract the upper value bits (including the sign bit) and 87 * shift them to bit 0. 88 */ 89 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1); 90 91 /* 92 * Overflow has occurred if the value is not representable in 93 * len bits (i.e the bottom len bits are not sign-extended and 94 * the top bits are not all zero). 95 */ 96 if ((u64)(sval + 1) > 2) 97 return -ERANGE; 98 99 return 0; 100 } 101 102 static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, 103 int lsb, enum aarch64_insn_imm_type imm_type) 104 { 105 u64 imm, limit = 0; 106 s64 sval; 107 u32 insn = le32_to_cpu(*(u32 *)place); 108 109 sval = do_reloc(op, place, val); 110 sval >>= lsb; 111 imm = sval & 0xffff; 112 113 if (imm_type == AARCH64_INSN_IMM_MOVNZ) { 114 /* 115 * For signed MOVW relocations, we have to manipulate the 116 * instruction encoding depending on whether or not the 117 * immediate is less than zero. 118 */ 119 insn &= ~(3 << 29); 120 if ((s64)imm >= 0) { 121 /* >=0: Set the instruction to MOVZ (opcode 10b). */ 122 insn |= 2 << 29; 123 } else { 124 /* 125 * <0: Set the instruction to MOVN (opcode 00b). 126 * Since we've masked the opcode already, we 127 * don't need to do anything other than 128 * inverting the new immediate field. 129 */ 130 imm = ~imm; 131 } 132 imm_type = AARCH64_INSN_IMM_MOVK; 133 } 134 135 /* Update the instruction with the new encoding. */ 136 insn = aarch64_insn_encode_immediate(imm_type, insn, imm); 137 *(u32 *)place = cpu_to_le32(insn); 138 139 /* Shift out the immediate field. */ 140 sval >>= 16; 141 142 /* 143 * For unsigned immediates, the overflow check is straightforward. 144 * For signed immediates, the sign bit is actually the bit past the 145 * most significant bit of the field. 146 * The AARCH64_INSN_IMM_16 immediate type is unsigned. 147 */ 148 if (imm_type != AARCH64_INSN_IMM_16) { 149 sval++; 150 limit++; 151 } 152 153 /* Check the upper bits depending on the sign of the immediate. */ 154 if ((u64)sval > limit) 155 return -ERANGE; 156 157 return 0; 158 } 159 160 static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val, 161 int lsb, int len, enum aarch64_insn_imm_type imm_type) 162 { 163 u64 imm, imm_mask; 164 s64 sval; 165 u32 insn = le32_to_cpu(*(u32 *)place); 166 167 /* Calculate the relocation value. */ 168 sval = do_reloc(op, place, val); 169 sval >>= lsb; 170 171 /* Extract the value bits and shift them to bit 0. */ 172 imm_mask = (BIT(lsb + len) - 1) >> lsb; 173 imm = sval & imm_mask; 174 175 /* Update the instruction's immediate field. */ 176 insn = aarch64_insn_encode_immediate(imm_type, insn, imm); 177 *(u32 *)place = cpu_to_le32(insn); 178 179 /* 180 * Extract the upper value bits (including the sign bit) and 181 * shift them to bit 0. 182 */ 183 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1); 184 185 /* 186 * Overflow has occurred if the upper bits are not all equal to 187 * the sign bit of the value. 188 */ 189 if ((u64)(sval + 1) >= 2) 190 return -ERANGE; 191 192 return 0; 193 } 194 195 int apply_relocate_add(Elf64_Shdr *sechdrs, 196 const char *strtab, 197 unsigned int symindex, 198 unsigned int relsec, 199 struct module *me) 200 { 201 unsigned int i; 202 int ovf; 203 bool overflow_check; 204 Elf64_Sym *sym; 205 void *loc; 206 u64 val; 207 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr; 208 209 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { 210 /* loc corresponds to P in the AArch64 ELF document. */ 211 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr 212 + rel[i].r_offset; 213 214 /* sym is the ELF symbol we're referring to. */ 215 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr 216 + ELF64_R_SYM(rel[i].r_info); 217 218 /* val corresponds to (S + A) in the AArch64 ELF document. */ 219 val = sym->st_value + rel[i].r_addend; 220 221 /* Check for overflow by default. */ 222 overflow_check = true; 223 224 /* Perform the static relocation. */ 225 switch (ELF64_R_TYPE(rel[i].r_info)) { 226 /* Null relocations. */ 227 case R_ARM_NONE: 228 case R_AARCH64_NONE: 229 ovf = 0; 230 break; 231 232 /* Data relocations. */ 233 case R_AARCH64_ABS64: 234 overflow_check = false; 235 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64); 236 break; 237 case R_AARCH64_ABS32: 238 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32); 239 break; 240 case R_AARCH64_ABS16: 241 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16); 242 break; 243 case R_AARCH64_PREL64: 244 overflow_check = false; 245 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64); 246 break; 247 case R_AARCH64_PREL32: 248 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32); 249 break; 250 case R_AARCH64_PREL16: 251 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16); 252 break; 253 254 /* MOVW instruction relocations. */ 255 case R_AARCH64_MOVW_UABS_G0_NC: 256 overflow_check = false; 257 case R_AARCH64_MOVW_UABS_G0: 258 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, 259 AARCH64_INSN_IMM_16); 260 break; 261 case R_AARCH64_MOVW_UABS_G1_NC: 262 overflow_check = false; 263 case R_AARCH64_MOVW_UABS_G1: 264 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, 265 AARCH64_INSN_IMM_16); 266 break; 267 case R_AARCH64_MOVW_UABS_G2_NC: 268 overflow_check = false; 269 case R_AARCH64_MOVW_UABS_G2: 270 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, 271 AARCH64_INSN_IMM_16); 272 break; 273 case R_AARCH64_MOVW_UABS_G3: 274 /* We're using the top bits so we can't overflow. */ 275 overflow_check = false; 276 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, 277 AARCH64_INSN_IMM_16); 278 break; 279 case R_AARCH64_MOVW_SABS_G0: 280 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, 281 AARCH64_INSN_IMM_MOVNZ); 282 break; 283 case R_AARCH64_MOVW_SABS_G1: 284 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, 285 AARCH64_INSN_IMM_MOVNZ); 286 break; 287 case R_AARCH64_MOVW_SABS_G2: 288 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, 289 AARCH64_INSN_IMM_MOVNZ); 290 break; 291 case R_AARCH64_MOVW_PREL_G0_NC: 292 overflow_check = false; 293 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, 294 AARCH64_INSN_IMM_MOVK); 295 break; 296 case R_AARCH64_MOVW_PREL_G0: 297 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, 298 AARCH64_INSN_IMM_MOVNZ); 299 break; 300 case R_AARCH64_MOVW_PREL_G1_NC: 301 overflow_check = false; 302 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, 303 AARCH64_INSN_IMM_MOVK); 304 break; 305 case R_AARCH64_MOVW_PREL_G1: 306 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, 307 AARCH64_INSN_IMM_MOVNZ); 308 break; 309 case R_AARCH64_MOVW_PREL_G2_NC: 310 overflow_check = false; 311 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, 312 AARCH64_INSN_IMM_MOVK); 313 break; 314 case R_AARCH64_MOVW_PREL_G2: 315 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, 316 AARCH64_INSN_IMM_MOVNZ); 317 break; 318 case R_AARCH64_MOVW_PREL_G3: 319 /* We're using the top bits so we can't overflow. */ 320 overflow_check = false; 321 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48, 322 AARCH64_INSN_IMM_MOVNZ); 323 break; 324 325 /* Immediate instruction relocations. */ 326 case R_AARCH64_LD_PREL_LO19: 327 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, 328 AARCH64_INSN_IMM_19); 329 break; 330 case R_AARCH64_ADR_PREL_LO21: 331 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, 332 AARCH64_INSN_IMM_ADR); 333 break; 334 case R_AARCH64_ADR_PREL_PG_HI21_NC: 335 overflow_check = false; 336 case R_AARCH64_ADR_PREL_PG_HI21: 337 ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21, 338 AARCH64_INSN_IMM_ADR); 339 break; 340 case R_AARCH64_ADD_ABS_LO12_NC: 341 case R_AARCH64_LDST8_ABS_LO12_NC: 342 overflow_check = false; 343 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12, 344 AARCH64_INSN_IMM_12); 345 break; 346 case R_AARCH64_LDST16_ABS_LO12_NC: 347 overflow_check = false; 348 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11, 349 AARCH64_INSN_IMM_12); 350 break; 351 case R_AARCH64_LDST32_ABS_LO12_NC: 352 overflow_check = false; 353 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10, 354 AARCH64_INSN_IMM_12); 355 break; 356 case R_AARCH64_LDST64_ABS_LO12_NC: 357 overflow_check = false; 358 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9, 359 AARCH64_INSN_IMM_12); 360 break; 361 case R_AARCH64_LDST128_ABS_LO12_NC: 362 overflow_check = false; 363 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8, 364 AARCH64_INSN_IMM_12); 365 break; 366 case R_AARCH64_TSTBR14: 367 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14, 368 AARCH64_INSN_IMM_14); 369 break; 370 case R_AARCH64_CONDBR19: 371 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, 372 AARCH64_INSN_IMM_19); 373 break; 374 case R_AARCH64_JUMP26: 375 case R_AARCH64_CALL26: 376 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, 377 AARCH64_INSN_IMM_26); 378 break; 379 380 default: 381 pr_err("module %s: unsupported RELA relocation: %llu\n", 382 me->name, ELF64_R_TYPE(rel[i].r_info)); 383 return -ENOEXEC; 384 } 385 386 if (overflow_check && ovf == -ERANGE) 387 goto overflow; 388 389 } 390 391 return 0; 392 393 overflow: 394 pr_err("module %s: overflow in relocation type %d val %Lx\n", 395 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val); 396 return -ENOEXEC; 397 } 398 399 int module_finalize(const Elf_Ehdr *hdr, 400 const Elf_Shdr *sechdrs, 401 struct module *me) 402 { 403 const Elf_Shdr *s, *se; 404 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; 405 406 for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { 407 if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) { 408 apply_alternatives((void *)s->sh_addr, s->sh_size); 409 return 0; 410 } 411 } 412 413 return 0; 414 } 415