1 /* 2 * AArch64 loadable module support. 3 * 4 * Copyright (C) 2012 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: Will Deacon <will.deacon@arm.com> 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/elf.h> 23 #include <linux/gfp.h> 24 #include <linux/kasan.h> 25 #include <linux/kernel.h> 26 #include <linux/mm.h> 27 #include <linux/moduleloader.h> 28 #include <linux/vmalloc.h> 29 #include <asm/alternative.h> 30 #include <asm/insn.h> 31 #include <asm/sections.h> 32 33 void *module_alloc(unsigned long size) 34 { 35 gfp_t gfp_mask = GFP_KERNEL; 36 void *p; 37 38 /* Silence the initial allocation */ 39 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS)) 40 gfp_mask |= __GFP_NOWARN; 41 42 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, 43 module_alloc_base + MODULES_VSIZE, 44 gfp_mask, PAGE_KERNEL_EXEC, 0, 45 NUMA_NO_NODE, __builtin_return_address(0)); 46 47 if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && 48 !IS_ENABLED(CONFIG_KASAN)) 49 /* 50 * KASAN can only deal with module allocations being served 51 * from the reserved module region, since the remainder of 52 * the vmalloc region is already backed by zero shadow pages, 53 * and punching holes into it is non-trivial. Since the module 54 * region is not randomized when KASAN is enabled, it is even 55 * less likely that the module region gets exhausted, so we 56 * can simply omit this fallback in that case. 57 */ 58 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, 59 module_alloc_base + SZ_2G, GFP_KERNEL, 60 PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, 61 __builtin_return_address(0)); 62 63 if (p && (kasan_module_alloc(p, size) < 0)) { 64 vfree(p); 65 return NULL; 66 } 67 68 return p; 69 } 70 71 enum aarch64_reloc_op { 72 RELOC_OP_NONE, 73 RELOC_OP_ABS, 74 RELOC_OP_PREL, 75 RELOC_OP_PAGE, 76 }; 77 78 static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val) 79 { 80 switch (reloc_op) { 81 case RELOC_OP_ABS: 82 return val; 83 case RELOC_OP_PREL: 84 return val - (u64)place; 85 case RELOC_OP_PAGE: 86 return (val & ~0xfff) - ((u64)place & ~0xfff); 87 case RELOC_OP_NONE: 88 return 0; 89 } 90 91 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op); 92 return 0; 93 } 94 95 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) 96 { 97 s64 sval = do_reloc(op, place, val); 98 99 /* 100 * The ELF psABI for AArch64 documents the 16-bit and 32-bit place 101 * relative and absolute relocations as having a range of [-2^15, 2^16) 102 * or [-2^31, 2^32), respectively. However, in order to be able to 103 * detect overflows reliably, we have to choose whether we interpret 104 * such quantities as signed or as unsigned, and stick with it. 105 * The way we organize our address space requires a signed 106 * interpretation of 32-bit relative references, so let's use that 107 * for all R_AARCH64_PRELxx relocations. This means our upper 108 * bound for overflow detection should be Sxx_MAX rather than Uxx_MAX. 109 */ 110 111 switch (len) { 112 case 16: 113 *(s16 *)place = sval; 114 switch (op) { 115 case RELOC_OP_ABS: 116 if (sval < 0 || sval > U16_MAX) 117 return -ERANGE; 118 break; 119 case RELOC_OP_PREL: 120 if (sval < S16_MIN || sval > S16_MAX) 121 return -ERANGE; 122 break; 123 default: 124 pr_err("Invalid 16-bit data relocation (%d)\n", op); 125 return 0; 126 } 127 break; 128 case 32: 129 *(s32 *)place = sval; 130 switch (op) { 131 case RELOC_OP_ABS: 132 if (sval < 0 || sval > U32_MAX) 133 return -ERANGE; 134 break; 135 case RELOC_OP_PREL: 136 if (sval < S32_MIN || sval > S32_MAX) 137 return -ERANGE; 138 break; 139 default: 140 pr_err("Invalid 32-bit data relocation (%d)\n", op); 141 return 0; 142 } 143 break; 144 case 64: 145 *(s64 *)place = sval; 146 break; 147 default: 148 pr_err("Invalid length (%d) for data relocation\n", len); 149 return 0; 150 } 151 return 0; 152 } 153 154 enum aarch64_insn_movw_imm_type { 155 AARCH64_INSN_IMM_MOVNZ, 156 AARCH64_INSN_IMM_MOVKZ, 157 }; 158 159 static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val, 160 int lsb, enum aarch64_insn_movw_imm_type imm_type) 161 { 162 u64 imm; 163 s64 sval; 164 u32 insn = le32_to_cpu(*place); 165 166 sval = do_reloc(op, place, val); 167 imm = sval >> lsb; 168 169 if (imm_type == AARCH64_INSN_IMM_MOVNZ) { 170 /* 171 * For signed MOVW relocations, we have to manipulate the 172 * instruction encoding depending on whether or not the 173 * immediate is less than zero. 174 */ 175 insn &= ~(3 << 29); 176 if (sval >= 0) { 177 /* >=0: Set the instruction to MOVZ (opcode 10b). */ 178 insn |= 2 << 29; 179 } else { 180 /* 181 * <0: Set the instruction to MOVN (opcode 00b). 182 * Since we've masked the opcode already, we 183 * don't need to do anything other than 184 * inverting the new immediate field. 185 */ 186 imm = ~imm; 187 } 188 } 189 190 /* Update the instruction with the new encoding. */ 191 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); 192 *place = cpu_to_le32(insn); 193 194 if (imm > U16_MAX) 195 return -ERANGE; 196 197 return 0; 198 } 199 200 static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val, 201 int lsb, int len, enum aarch64_insn_imm_type imm_type) 202 { 203 u64 imm, imm_mask; 204 s64 sval; 205 u32 insn = le32_to_cpu(*place); 206 207 /* Calculate the relocation value. */ 208 sval = do_reloc(op, place, val); 209 sval >>= lsb; 210 211 /* Extract the value bits and shift them to bit 0. */ 212 imm_mask = (BIT(lsb + len) - 1) >> lsb; 213 imm = sval & imm_mask; 214 215 /* Update the instruction's immediate field. */ 216 insn = aarch64_insn_encode_immediate(imm_type, insn, imm); 217 *place = cpu_to_le32(insn); 218 219 /* 220 * Extract the upper value bits (including the sign bit) and 221 * shift them to bit 0. 222 */ 223 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1); 224 225 /* 226 * Overflow has occurred if the upper bits are not all equal to 227 * the sign bit of the value. 228 */ 229 if ((u64)(sval + 1) >= 2) 230 return -ERANGE; 231 232 return 0; 233 } 234 235 static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs, 236 __le32 *place, u64 val) 237 { 238 u32 insn; 239 240 if (!is_forbidden_offset_for_adrp(place)) 241 return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21, 242 AARCH64_INSN_IMM_ADR); 243 244 /* patch ADRP to ADR if it is in range */ 245 if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21, 246 AARCH64_INSN_IMM_ADR)) { 247 insn = le32_to_cpu(*place); 248 insn &= ~BIT(31); 249 } else { 250 /* out of range for ADR -> emit a veneer */ 251 val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff); 252 if (!val) 253 return -ENOEXEC; 254 insn = aarch64_insn_gen_branch_imm((u64)place, val, 255 AARCH64_INSN_BRANCH_NOLINK); 256 } 257 258 *place = cpu_to_le32(insn); 259 return 0; 260 } 261 262 int apply_relocate_add(Elf64_Shdr *sechdrs, 263 const char *strtab, 264 unsigned int symindex, 265 unsigned int relsec, 266 struct module *me) 267 { 268 unsigned int i; 269 int ovf; 270 bool overflow_check; 271 Elf64_Sym *sym; 272 void *loc; 273 u64 val; 274 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr; 275 276 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { 277 /* loc corresponds to P in the AArch64 ELF document. */ 278 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr 279 + rel[i].r_offset; 280 281 /* sym is the ELF symbol we're referring to. */ 282 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr 283 + ELF64_R_SYM(rel[i].r_info); 284 285 /* val corresponds to (S + A) in the AArch64 ELF document. */ 286 val = sym->st_value + rel[i].r_addend; 287 288 /* Check for overflow by default. */ 289 overflow_check = true; 290 291 /* Perform the static relocation. */ 292 switch (ELF64_R_TYPE(rel[i].r_info)) { 293 /* Null relocations. */ 294 case R_ARM_NONE: 295 case R_AARCH64_NONE: 296 ovf = 0; 297 break; 298 299 /* Data relocations. */ 300 case R_AARCH64_ABS64: 301 overflow_check = false; 302 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64); 303 break; 304 case R_AARCH64_ABS32: 305 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32); 306 break; 307 case R_AARCH64_ABS16: 308 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16); 309 break; 310 case R_AARCH64_PREL64: 311 overflow_check = false; 312 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64); 313 break; 314 case R_AARCH64_PREL32: 315 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32); 316 break; 317 case R_AARCH64_PREL16: 318 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16); 319 break; 320 321 /* MOVW instruction relocations. */ 322 case R_AARCH64_MOVW_UABS_G0_NC: 323 overflow_check = false; 324 case R_AARCH64_MOVW_UABS_G0: 325 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, 326 AARCH64_INSN_IMM_MOVKZ); 327 break; 328 case R_AARCH64_MOVW_UABS_G1_NC: 329 overflow_check = false; 330 case R_AARCH64_MOVW_UABS_G1: 331 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, 332 AARCH64_INSN_IMM_MOVKZ); 333 break; 334 case R_AARCH64_MOVW_UABS_G2_NC: 335 overflow_check = false; 336 case R_AARCH64_MOVW_UABS_G2: 337 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, 338 AARCH64_INSN_IMM_MOVKZ); 339 break; 340 case R_AARCH64_MOVW_UABS_G3: 341 /* We're using the top bits so we can't overflow. */ 342 overflow_check = false; 343 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, 344 AARCH64_INSN_IMM_MOVKZ); 345 break; 346 case R_AARCH64_MOVW_SABS_G0: 347 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, 348 AARCH64_INSN_IMM_MOVNZ); 349 break; 350 case R_AARCH64_MOVW_SABS_G1: 351 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, 352 AARCH64_INSN_IMM_MOVNZ); 353 break; 354 case R_AARCH64_MOVW_SABS_G2: 355 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, 356 AARCH64_INSN_IMM_MOVNZ); 357 break; 358 case R_AARCH64_MOVW_PREL_G0_NC: 359 overflow_check = false; 360 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, 361 AARCH64_INSN_IMM_MOVKZ); 362 break; 363 case R_AARCH64_MOVW_PREL_G0: 364 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, 365 AARCH64_INSN_IMM_MOVNZ); 366 break; 367 case R_AARCH64_MOVW_PREL_G1_NC: 368 overflow_check = false; 369 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, 370 AARCH64_INSN_IMM_MOVKZ); 371 break; 372 case R_AARCH64_MOVW_PREL_G1: 373 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, 374 AARCH64_INSN_IMM_MOVNZ); 375 break; 376 case R_AARCH64_MOVW_PREL_G2_NC: 377 overflow_check = false; 378 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, 379 AARCH64_INSN_IMM_MOVKZ); 380 break; 381 case R_AARCH64_MOVW_PREL_G2: 382 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, 383 AARCH64_INSN_IMM_MOVNZ); 384 break; 385 case R_AARCH64_MOVW_PREL_G3: 386 /* We're using the top bits so we can't overflow. */ 387 overflow_check = false; 388 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48, 389 AARCH64_INSN_IMM_MOVNZ); 390 break; 391 392 /* Immediate instruction relocations. */ 393 case R_AARCH64_LD_PREL_LO19: 394 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, 395 AARCH64_INSN_IMM_19); 396 break; 397 case R_AARCH64_ADR_PREL_LO21: 398 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, 399 AARCH64_INSN_IMM_ADR); 400 break; 401 case R_AARCH64_ADR_PREL_PG_HI21_NC: 402 overflow_check = false; 403 case R_AARCH64_ADR_PREL_PG_HI21: 404 ovf = reloc_insn_adrp(me, sechdrs, loc, val); 405 if (ovf && ovf != -ERANGE) 406 return ovf; 407 break; 408 case R_AARCH64_ADD_ABS_LO12_NC: 409 case R_AARCH64_LDST8_ABS_LO12_NC: 410 overflow_check = false; 411 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12, 412 AARCH64_INSN_IMM_12); 413 break; 414 case R_AARCH64_LDST16_ABS_LO12_NC: 415 overflow_check = false; 416 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11, 417 AARCH64_INSN_IMM_12); 418 break; 419 case R_AARCH64_LDST32_ABS_LO12_NC: 420 overflow_check = false; 421 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10, 422 AARCH64_INSN_IMM_12); 423 break; 424 case R_AARCH64_LDST64_ABS_LO12_NC: 425 overflow_check = false; 426 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9, 427 AARCH64_INSN_IMM_12); 428 break; 429 case R_AARCH64_LDST128_ABS_LO12_NC: 430 overflow_check = false; 431 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8, 432 AARCH64_INSN_IMM_12); 433 break; 434 case R_AARCH64_TSTBR14: 435 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14, 436 AARCH64_INSN_IMM_14); 437 break; 438 case R_AARCH64_CONDBR19: 439 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, 440 AARCH64_INSN_IMM_19); 441 break; 442 case R_AARCH64_JUMP26: 443 case R_AARCH64_CALL26: 444 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, 445 AARCH64_INSN_IMM_26); 446 447 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && 448 ovf == -ERANGE) { 449 val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym); 450 if (!val) 451 return -ENOEXEC; 452 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 453 26, AARCH64_INSN_IMM_26); 454 } 455 break; 456 457 default: 458 pr_err("module %s: unsupported RELA relocation: %llu\n", 459 me->name, ELF64_R_TYPE(rel[i].r_info)); 460 return -ENOEXEC; 461 } 462 463 if (overflow_check && ovf == -ERANGE) 464 goto overflow; 465 466 } 467 468 return 0; 469 470 overflow: 471 pr_err("module %s: overflow in relocation type %d val %Lx\n", 472 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val); 473 return -ENOEXEC; 474 } 475 476 int module_finalize(const Elf_Ehdr *hdr, 477 const Elf_Shdr *sechdrs, 478 struct module *me) 479 { 480 const Elf_Shdr *s, *se; 481 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; 482 483 for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { 484 if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) 485 apply_alternatives_module((void *)s->sh_addr, s->sh_size); 486 #ifdef CONFIG_ARM64_MODULE_PLTS 487 if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) && 488 !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name)) 489 me->arch.ftrace_trampoline = (void *)s->sh_addr; 490 #endif 491 } 492 493 return 0; 494 } 495