1 /* 2 * AArch64 loadable module support. 3 * 4 * Copyright (C) 2012 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: Will Deacon <will.deacon@arm.com> 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/elf.h> 23 #include <linux/gfp.h> 24 #include <linux/kasan.h> 25 #include <linux/kernel.h> 26 #include <linux/mm.h> 27 #include <linux/moduleloader.h> 28 #include <linux/vmalloc.h> 29 #include <asm/alternative.h> 30 #include <asm/insn.h> 31 #include <asm/sections.h> 32 33 void *module_alloc(unsigned long size) 34 { 35 gfp_t gfp_mask = GFP_KERNEL; 36 void *p; 37 38 /* Silence the initial allocation */ 39 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS)) 40 gfp_mask |= __GFP_NOWARN; 41 42 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, 43 module_alloc_base + MODULES_VSIZE, 44 gfp_mask, PAGE_KERNEL_EXEC, 0, 45 NUMA_NO_NODE, __builtin_return_address(0)); 46 47 if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && 48 !IS_ENABLED(CONFIG_KASAN)) 49 /* 50 * KASAN can only deal with module allocations being served 51 * from the reserved module region, since the remainder of 52 * the vmalloc region is already backed by zero shadow pages, 53 * and punching holes into it is non-trivial. Since the module 54 * region is not randomized when KASAN is enabled, it is even 55 * less likely that the module region gets exhausted, so we 56 * can simply omit this fallback in that case. 57 */ 58 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, 59 module_alloc_base + SZ_4G, GFP_KERNEL, 60 PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, 61 __builtin_return_address(0)); 62 63 if (p && (kasan_module_alloc(p, size) < 0)) { 64 vfree(p); 65 return NULL; 66 } 67 68 return p; 69 } 70 71 enum aarch64_reloc_op { 72 RELOC_OP_NONE, 73 RELOC_OP_ABS, 74 RELOC_OP_PREL, 75 RELOC_OP_PAGE, 76 }; 77 78 static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val) 79 { 80 switch (reloc_op) { 81 case RELOC_OP_ABS: 82 return val; 83 case RELOC_OP_PREL: 84 return val - (u64)place; 85 case RELOC_OP_PAGE: 86 return (val & ~0xfff) - ((u64)place & ~0xfff); 87 case RELOC_OP_NONE: 88 return 0; 89 } 90 91 pr_err("do_reloc: unknown relocation operation %d\n", reloc_op); 92 return 0; 93 } 94 95 static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) 96 { 97 s64 sval = do_reloc(op, place, val); 98 99 switch (len) { 100 case 16: 101 *(s16 *)place = sval; 102 if (sval < S16_MIN || sval > U16_MAX) 103 return -ERANGE; 104 break; 105 case 32: 106 *(s32 *)place = sval; 107 if (sval < S32_MIN || sval > U32_MAX) 108 return -ERANGE; 109 break; 110 case 64: 111 *(s64 *)place = sval; 112 break; 113 default: 114 pr_err("Invalid length (%d) for data relocation\n", len); 115 return 0; 116 } 117 return 0; 118 } 119 120 enum aarch64_insn_movw_imm_type { 121 AARCH64_INSN_IMM_MOVNZ, 122 AARCH64_INSN_IMM_MOVKZ, 123 }; 124 125 static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val, 126 int lsb, enum aarch64_insn_movw_imm_type imm_type) 127 { 128 u64 imm; 129 s64 sval; 130 u32 insn = le32_to_cpu(*place); 131 132 sval = do_reloc(op, place, val); 133 imm = sval >> lsb; 134 135 if (imm_type == AARCH64_INSN_IMM_MOVNZ) { 136 /* 137 * For signed MOVW relocations, we have to manipulate the 138 * instruction encoding depending on whether or not the 139 * immediate is less than zero. 140 */ 141 insn &= ~(3 << 29); 142 if (sval >= 0) { 143 /* >=0: Set the instruction to MOVZ (opcode 10b). */ 144 insn |= 2 << 29; 145 } else { 146 /* 147 * <0: Set the instruction to MOVN (opcode 00b). 148 * Since we've masked the opcode already, we 149 * don't need to do anything other than 150 * inverting the new immediate field. 151 */ 152 imm = ~imm; 153 } 154 } 155 156 /* Update the instruction with the new encoding. */ 157 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); 158 *place = cpu_to_le32(insn); 159 160 if (imm > U16_MAX) 161 return -ERANGE; 162 163 return 0; 164 } 165 166 static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val, 167 int lsb, int len, enum aarch64_insn_imm_type imm_type) 168 { 169 u64 imm, imm_mask; 170 s64 sval; 171 u32 insn = le32_to_cpu(*place); 172 173 /* Calculate the relocation value. */ 174 sval = do_reloc(op, place, val); 175 sval >>= lsb; 176 177 /* Extract the value bits and shift them to bit 0. */ 178 imm_mask = (BIT(lsb + len) - 1) >> lsb; 179 imm = sval & imm_mask; 180 181 /* Update the instruction's immediate field. */ 182 insn = aarch64_insn_encode_immediate(imm_type, insn, imm); 183 *place = cpu_to_le32(insn); 184 185 /* 186 * Extract the upper value bits (including the sign bit) and 187 * shift them to bit 0. 188 */ 189 sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1); 190 191 /* 192 * Overflow has occurred if the upper bits are not all equal to 193 * the sign bit of the value. 194 */ 195 if ((u64)(sval + 1) >= 2) 196 return -ERANGE; 197 198 return 0; 199 } 200 201 static int reloc_insn_adrp(struct module *mod, __le32 *place, u64 val) 202 { 203 u32 insn; 204 205 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) || 206 !cpus_have_const_cap(ARM64_WORKAROUND_843419) || 207 ((u64)place & 0xfff) < 0xff8) 208 return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21, 209 AARCH64_INSN_IMM_ADR); 210 211 /* patch ADRP to ADR if it is in range */ 212 if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21, 213 AARCH64_INSN_IMM_ADR)) { 214 insn = le32_to_cpu(*place); 215 insn &= ~BIT(31); 216 } else { 217 /* out of range for ADR -> emit a veneer */ 218 val = module_emit_veneer_for_adrp(mod, place, val & ~0xfff); 219 if (!val) 220 return -ENOEXEC; 221 insn = aarch64_insn_gen_branch_imm((u64)place, val, 222 AARCH64_INSN_BRANCH_NOLINK); 223 } 224 225 *place = cpu_to_le32(insn); 226 return 0; 227 } 228 229 int apply_relocate_add(Elf64_Shdr *sechdrs, 230 const char *strtab, 231 unsigned int symindex, 232 unsigned int relsec, 233 struct module *me) 234 { 235 unsigned int i; 236 int ovf; 237 bool overflow_check; 238 Elf64_Sym *sym; 239 void *loc; 240 u64 val; 241 Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr; 242 243 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { 244 /* loc corresponds to P in the AArch64 ELF document. */ 245 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr 246 + rel[i].r_offset; 247 248 /* sym is the ELF symbol we're referring to. */ 249 sym = (Elf64_Sym *)sechdrs[symindex].sh_addr 250 + ELF64_R_SYM(rel[i].r_info); 251 252 /* val corresponds to (S + A) in the AArch64 ELF document. */ 253 val = sym->st_value + rel[i].r_addend; 254 255 /* Check for overflow by default. */ 256 overflow_check = true; 257 258 /* Perform the static relocation. */ 259 switch (ELF64_R_TYPE(rel[i].r_info)) { 260 /* Null relocations. */ 261 case R_ARM_NONE: 262 case R_AARCH64_NONE: 263 ovf = 0; 264 break; 265 266 /* Data relocations. */ 267 case R_AARCH64_ABS64: 268 overflow_check = false; 269 ovf = reloc_data(RELOC_OP_ABS, loc, val, 64); 270 break; 271 case R_AARCH64_ABS32: 272 ovf = reloc_data(RELOC_OP_ABS, loc, val, 32); 273 break; 274 case R_AARCH64_ABS16: 275 ovf = reloc_data(RELOC_OP_ABS, loc, val, 16); 276 break; 277 case R_AARCH64_PREL64: 278 overflow_check = false; 279 ovf = reloc_data(RELOC_OP_PREL, loc, val, 64); 280 break; 281 case R_AARCH64_PREL32: 282 ovf = reloc_data(RELOC_OP_PREL, loc, val, 32); 283 break; 284 case R_AARCH64_PREL16: 285 ovf = reloc_data(RELOC_OP_PREL, loc, val, 16); 286 break; 287 288 /* MOVW instruction relocations. */ 289 case R_AARCH64_MOVW_UABS_G0_NC: 290 overflow_check = false; 291 case R_AARCH64_MOVW_UABS_G0: 292 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, 293 AARCH64_INSN_IMM_MOVKZ); 294 break; 295 case R_AARCH64_MOVW_UABS_G1_NC: 296 overflow_check = false; 297 case R_AARCH64_MOVW_UABS_G1: 298 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, 299 AARCH64_INSN_IMM_MOVKZ); 300 break; 301 case R_AARCH64_MOVW_UABS_G2_NC: 302 overflow_check = false; 303 case R_AARCH64_MOVW_UABS_G2: 304 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, 305 AARCH64_INSN_IMM_MOVKZ); 306 break; 307 case R_AARCH64_MOVW_UABS_G3: 308 /* We're using the top bits so we can't overflow. */ 309 overflow_check = false; 310 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, 311 AARCH64_INSN_IMM_MOVKZ); 312 break; 313 case R_AARCH64_MOVW_SABS_G0: 314 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, 315 AARCH64_INSN_IMM_MOVNZ); 316 break; 317 case R_AARCH64_MOVW_SABS_G1: 318 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, 319 AARCH64_INSN_IMM_MOVNZ); 320 break; 321 case R_AARCH64_MOVW_SABS_G2: 322 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, 323 AARCH64_INSN_IMM_MOVNZ); 324 break; 325 case R_AARCH64_MOVW_PREL_G0_NC: 326 overflow_check = false; 327 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, 328 AARCH64_INSN_IMM_MOVKZ); 329 break; 330 case R_AARCH64_MOVW_PREL_G0: 331 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, 332 AARCH64_INSN_IMM_MOVNZ); 333 break; 334 case R_AARCH64_MOVW_PREL_G1_NC: 335 overflow_check = false; 336 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, 337 AARCH64_INSN_IMM_MOVKZ); 338 break; 339 case R_AARCH64_MOVW_PREL_G1: 340 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, 341 AARCH64_INSN_IMM_MOVNZ); 342 break; 343 case R_AARCH64_MOVW_PREL_G2_NC: 344 overflow_check = false; 345 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, 346 AARCH64_INSN_IMM_MOVKZ); 347 break; 348 case R_AARCH64_MOVW_PREL_G2: 349 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, 350 AARCH64_INSN_IMM_MOVNZ); 351 break; 352 case R_AARCH64_MOVW_PREL_G3: 353 /* We're using the top bits so we can't overflow. */ 354 overflow_check = false; 355 ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48, 356 AARCH64_INSN_IMM_MOVNZ); 357 break; 358 359 /* Immediate instruction relocations. */ 360 case R_AARCH64_LD_PREL_LO19: 361 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, 362 AARCH64_INSN_IMM_19); 363 break; 364 case R_AARCH64_ADR_PREL_LO21: 365 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, 366 AARCH64_INSN_IMM_ADR); 367 break; 368 case R_AARCH64_ADR_PREL_PG_HI21_NC: 369 overflow_check = false; 370 case R_AARCH64_ADR_PREL_PG_HI21: 371 ovf = reloc_insn_adrp(me, loc, val); 372 if (ovf && ovf != -ERANGE) 373 return ovf; 374 break; 375 case R_AARCH64_ADD_ABS_LO12_NC: 376 case R_AARCH64_LDST8_ABS_LO12_NC: 377 overflow_check = false; 378 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12, 379 AARCH64_INSN_IMM_12); 380 break; 381 case R_AARCH64_LDST16_ABS_LO12_NC: 382 overflow_check = false; 383 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11, 384 AARCH64_INSN_IMM_12); 385 break; 386 case R_AARCH64_LDST32_ABS_LO12_NC: 387 overflow_check = false; 388 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10, 389 AARCH64_INSN_IMM_12); 390 break; 391 case R_AARCH64_LDST64_ABS_LO12_NC: 392 overflow_check = false; 393 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9, 394 AARCH64_INSN_IMM_12); 395 break; 396 case R_AARCH64_LDST128_ABS_LO12_NC: 397 overflow_check = false; 398 ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8, 399 AARCH64_INSN_IMM_12); 400 break; 401 case R_AARCH64_TSTBR14: 402 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14, 403 AARCH64_INSN_IMM_14); 404 break; 405 case R_AARCH64_CONDBR19: 406 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19, 407 AARCH64_INSN_IMM_19); 408 break; 409 case R_AARCH64_JUMP26: 410 case R_AARCH64_CALL26: 411 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, 412 AARCH64_INSN_IMM_26); 413 414 if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && 415 ovf == -ERANGE) { 416 val = module_emit_plt_entry(me, loc, &rel[i], sym); 417 if (!val) 418 return -ENOEXEC; 419 ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 420 26, AARCH64_INSN_IMM_26); 421 } 422 break; 423 424 default: 425 pr_err("module %s: unsupported RELA relocation: %llu\n", 426 me->name, ELF64_R_TYPE(rel[i].r_info)); 427 return -ENOEXEC; 428 } 429 430 if (overflow_check && ovf == -ERANGE) 431 goto overflow; 432 433 } 434 435 return 0; 436 437 overflow: 438 pr_err("module %s: overflow in relocation type %d val %Lx\n", 439 me->name, (int)ELF64_R_TYPE(rel[i].r_info), val); 440 return -ENOEXEC; 441 } 442 443 int module_finalize(const Elf_Ehdr *hdr, 444 const Elf_Shdr *sechdrs, 445 struct module *me) 446 { 447 const Elf_Shdr *s, *se; 448 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; 449 450 for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { 451 if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) 452 apply_alternatives_module((void *)s->sh_addr, s->sh_size); 453 #ifdef CONFIG_ARM64_MODULE_PLTS 454 if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) && 455 !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name)) 456 me->arch.ftrace_trampoline = (void *)s->sh_addr; 457 #endif 458 } 459 460 return 0; 461 } 462