1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2fd045f6cSArd Biesheuvel /* 324af6c4eSArd Biesheuvel * Copyright (C) 2014-2017 Linaro Ltd. <ard.biesheuvel@linaro.org> 4fd045f6cSArd Biesheuvel */ 5fd045f6cSArd Biesheuvel 6fd045f6cSArd Biesheuvel #include <linux/elf.h> 73b23e499STorsten Duwe #include <linux/ftrace.h> 8fd045f6cSArd Biesheuvel #include <linux/kernel.h> 9fd045f6cSArd Biesheuvel #include <linux/module.h> 1060a0aab7SArnd Bergmann #include <linux/moduleloader.h> 11fd045f6cSArd Biesheuvel #include <linux/sort.h> 12fd045f6cSArd Biesheuvel 13bdb85cd1SArd Biesheuvel static struct plt_entry __get_adrp_add_pair(u64 dst, u64 pc, 14bdb85cd1SArd Biesheuvel enum aarch64_insn_register reg) 15bdb85cd1SArd Biesheuvel { 16bdb85cd1SArd Biesheuvel u32 adrp, add; 17bdb85cd1SArd Biesheuvel 18bdb85cd1SArd Biesheuvel adrp = aarch64_insn_gen_adr(pc, dst, reg, AARCH64_INSN_ADR_TYPE_ADRP); 19bdb85cd1SArd Biesheuvel add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K, 20bdb85cd1SArd Biesheuvel AARCH64_INSN_VARIANT_64BIT, 21bdb85cd1SArd Biesheuvel AARCH64_INSN_ADSB_ADD); 22bdb85cd1SArd Biesheuvel 23bdb85cd1SArd Biesheuvel return (struct plt_entry){ cpu_to_le32(adrp), cpu_to_le32(add) }; 24bdb85cd1SArd Biesheuvel } 25bdb85cd1SArd Biesheuvel 26bdb85cd1SArd Biesheuvel struct plt_entry get_plt_entry(u64 dst, void *pc) 27bdb85cd1SArd Biesheuvel { 28bdb85cd1SArd Biesheuvel struct plt_entry plt; 29bdb85cd1SArd Biesheuvel static u32 br; 30bdb85cd1SArd Biesheuvel 31bdb85cd1SArd Biesheuvel if (!br) 32bdb85cd1SArd Biesheuvel br = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_16, 33bdb85cd1SArd Biesheuvel AARCH64_INSN_BRANCH_NOLINK); 34bdb85cd1SArd Biesheuvel 35bdb85cd1SArd Biesheuvel plt = __get_adrp_add_pair(dst, (u64)pc, AARCH64_INSN_REG_16); 36bdb85cd1SArd Biesheuvel plt.br = cpu_to_le32(br); 37bdb85cd1SArd Biesheuvel 38bdb85cd1SArd Biesheuvel return plt; 39bdb85cd1SArd Biesheuvel } 40bdb85cd1SArd Biesheuvel 413fb420f5SLi Huafei static bool plt_entries_equal(const struct plt_entry *a, 423fb420f5SLi Huafei const struct plt_entry *b) 43bdb85cd1SArd Biesheuvel { 44bdb85cd1SArd Biesheuvel u64 p, q; 45bdb85cd1SArd Biesheuvel 46bdb85cd1SArd Biesheuvel /* 47bdb85cd1SArd Biesheuvel * Check whether both entries refer to the same target: 48bdb85cd1SArd Biesheuvel * do the cheapest checks first. 49bdb85cd1SArd Biesheuvel * If the 'add' or 'br' opcodes are different, then the target 50bdb85cd1SArd Biesheuvel * cannot be the same. 51bdb85cd1SArd Biesheuvel */ 52bdb85cd1SArd Biesheuvel if (a->add != b->add || a->br != b->br) 53bdb85cd1SArd Biesheuvel return false; 54bdb85cd1SArd Biesheuvel 55bdb85cd1SArd Biesheuvel p = ALIGN_DOWN((u64)a, SZ_4K); 56bdb85cd1SArd Biesheuvel q = ALIGN_DOWN((u64)b, SZ_4K); 57bdb85cd1SArd Biesheuvel 58bdb85cd1SArd Biesheuvel /* 59bdb85cd1SArd Biesheuvel * If the 'adrp' opcodes are the same then we just need to check 60bdb85cd1SArd Biesheuvel * that they refer to the same 4k region. 61bdb85cd1SArd Biesheuvel */ 62bdb85cd1SArd Biesheuvel if (a->adrp == b->adrp && p == q) 63bdb85cd1SArd Biesheuvel return true; 64bdb85cd1SArd Biesheuvel 65bdb85cd1SArd Biesheuvel return (p + aarch64_insn_adrp_get_offset(le32_to_cpu(a->adrp))) == 66bdb85cd1SArd Biesheuvel (q + aarch64_insn_adrp_get_offset(le32_to_cpu(b->adrp))); 67bdb85cd1SArd Biesheuvel } 68bdb85cd1SArd Biesheuvel 69c8ebf64eSJessica Yu u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs, 70c8ebf64eSJessica Yu void *loc, const Elf64_Rela *rela, 7124af6c4eSArd Biesheuvel Elf64_Sym *sym) 7224af6c4eSArd Biesheuvel { 73ac3b4328SSong Liu struct mod_plt_sec *pltsec = !within_module_init((unsigned long)loc, mod) ? 74ac3b4328SSong Liu &mod->arch.core : &mod->arch.init; 75c8ebf64eSJessica Yu struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr; 7624af6c4eSArd Biesheuvel int i = pltsec->plt_num_entries; 77bdb85cd1SArd Biesheuvel int j = i - 1; 7824af6c4eSArd Biesheuvel u64 val = sym->st_value + rela->r_addend; 79fd045f6cSArd Biesheuvel 80bdb85cd1SArd Biesheuvel if (is_forbidden_offset_for_adrp(&plt[i].adrp)) 81bdb85cd1SArd Biesheuvel i++; 82bdb85cd1SArd Biesheuvel 83bdb85cd1SArd Biesheuvel plt[i] = get_plt_entry(val, &plt[i]); 84fd045f6cSArd Biesheuvel 8524af6c4eSArd Biesheuvel /* 8624af6c4eSArd Biesheuvel * Check if the entry we just created is a duplicate. Given that the 8724af6c4eSArd Biesheuvel * relocations are sorted, this will be the last entry we allocated. 8824af6c4eSArd Biesheuvel * (if one exists). 8924af6c4eSArd Biesheuvel */ 90bdb85cd1SArd Biesheuvel if (j >= 0 && plt_entries_equal(plt + i, plt + j)) 91bdb85cd1SArd Biesheuvel return (u64)&plt[j]; 9224af6c4eSArd Biesheuvel 93bdb85cd1SArd Biesheuvel pltsec->plt_num_entries += i - j; 945e8307b9SArd Biesheuvel if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries)) 955e8307b9SArd Biesheuvel return 0; 96fd045f6cSArd Biesheuvel 97fd045f6cSArd Biesheuvel return (u64)&plt[i]; 98fd045f6cSArd Biesheuvel } 99fd045f6cSArd Biesheuvel 100a257e025SArd Biesheuvel #ifdef CONFIG_ARM64_ERRATUM_843419 101c8ebf64eSJessica Yu u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs, 102c8ebf64eSJessica Yu void *loc, u64 val) 103a257e025SArd Biesheuvel { 104ac3b4328SSong Liu struct mod_plt_sec *pltsec = !within_module_init((unsigned long)loc, mod) ? 105ac3b4328SSong Liu &mod->arch.core : &mod->arch.init; 106c8ebf64eSJessica Yu struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr; 107a257e025SArd Biesheuvel int i = pltsec->plt_num_entries++; 108bdb85cd1SArd Biesheuvel u32 br; 109a257e025SArd Biesheuvel int rd; 110a257e025SArd Biesheuvel 111a257e025SArd Biesheuvel if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries)) 112a257e025SArd Biesheuvel return 0; 113a257e025SArd Biesheuvel 114bdb85cd1SArd Biesheuvel if (is_forbidden_offset_for_adrp(&plt[i].adrp)) 115bdb85cd1SArd Biesheuvel i = pltsec->plt_num_entries++; 116bdb85cd1SArd Biesheuvel 117a257e025SArd Biesheuvel /* get the destination register of the ADRP instruction */ 118a257e025SArd Biesheuvel rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, 119a257e025SArd Biesheuvel le32_to_cpup((__le32 *)loc)); 120a257e025SArd Biesheuvel 121a257e025SArd Biesheuvel br = aarch64_insn_gen_branch_imm((u64)&plt[i].br, (u64)loc + 4, 122a257e025SArd Biesheuvel AARCH64_INSN_BRANCH_NOLINK); 123a257e025SArd Biesheuvel 124bdb85cd1SArd Biesheuvel plt[i] = __get_adrp_add_pair(val, (u64)&plt[i], rd); 125bdb85cd1SArd Biesheuvel plt[i].br = cpu_to_le32(br); 126a257e025SArd Biesheuvel 127a257e025SArd Biesheuvel return (u64)&plt[i]; 128a257e025SArd Biesheuvel } 129a257e025SArd Biesheuvel #endif 130a257e025SArd Biesheuvel 131fd045f6cSArd Biesheuvel #define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) 132fd045f6cSArd Biesheuvel 133fd045f6cSArd Biesheuvel static int cmp_rela(const void *a, const void *b) 134fd045f6cSArd Biesheuvel { 135fd045f6cSArd Biesheuvel const Elf64_Rela *x = a, *y = b; 136fd045f6cSArd Biesheuvel int i; 137fd045f6cSArd Biesheuvel 138fd045f6cSArd Biesheuvel /* sort by type, symbol index and addend */ 139fd045f6cSArd Biesheuvel i = cmp_3way(ELF64_R_TYPE(x->r_info), ELF64_R_TYPE(y->r_info)); 140fd045f6cSArd Biesheuvel if (i == 0) 141fd045f6cSArd Biesheuvel i = cmp_3way(ELF64_R_SYM(x->r_info), ELF64_R_SYM(y->r_info)); 142fd045f6cSArd Biesheuvel if (i == 0) 143fd045f6cSArd Biesheuvel i = cmp_3way(x->r_addend, y->r_addend); 144fd045f6cSArd Biesheuvel return i; 145fd045f6cSArd Biesheuvel } 146fd045f6cSArd Biesheuvel 147fd045f6cSArd Biesheuvel static bool duplicate_rel(const Elf64_Rela *rela, int num) 148fd045f6cSArd Biesheuvel { 149fd045f6cSArd Biesheuvel /* 150fd045f6cSArd Biesheuvel * Entries are sorted by type, symbol index and addend. That means 151fd045f6cSArd Biesheuvel * that, if a duplicate entry exists, it must be in the preceding 152fd045f6cSArd Biesheuvel * slot. 153fd045f6cSArd Biesheuvel */ 154fd045f6cSArd Biesheuvel return num > 0 && cmp_rela(rela + num, rela + num - 1) == 0; 155fd045f6cSArd Biesheuvel } 156fd045f6cSArd Biesheuvel 15724af6c4eSArd Biesheuvel static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num, 158a257e025SArd Biesheuvel Elf64_Word dstidx, Elf_Shdr *dstsec) 159fd045f6cSArd Biesheuvel { 160fd045f6cSArd Biesheuvel unsigned int ret = 0; 161fd045f6cSArd Biesheuvel Elf64_Sym *s; 162fd045f6cSArd Biesheuvel int i; 163fd045f6cSArd Biesheuvel 164fd045f6cSArd Biesheuvel for (i = 0; i < num; i++) { 165a257e025SArd Biesheuvel u64 min_align; 166a257e025SArd Biesheuvel 167fd045f6cSArd Biesheuvel switch (ELF64_R_TYPE(rela[i].r_info)) { 168fd045f6cSArd Biesheuvel case R_AARCH64_JUMP26: 169fd045f6cSArd Biesheuvel case R_AARCH64_CALL26: 170a257e025SArd Biesheuvel if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 171a257e025SArd Biesheuvel break; 172a257e025SArd Biesheuvel 173fd045f6cSArd Biesheuvel /* 174fd045f6cSArd Biesheuvel * We only have to consider branch targets that resolve 17524af6c4eSArd Biesheuvel * to symbols that are defined in a different section. 17624af6c4eSArd Biesheuvel * This is not simply a heuristic, it is a fundamental 17724af6c4eSArd Biesheuvel * limitation, since there is no guaranteed way to emit 17824af6c4eSArd Biesheuvel * PLT entries sufficiently close to the branch if the 17924af6c4eSArd Biesheuvel * section size exceeds the range of a branch 18024af6c4eSArd Biesheuvel * instruction. So ignore relocations against defined 18124af6c4eSArd Biesheuvel * symbols if they live in the same section as the 18224af6c4eSArd Biesheuvel * relocation target. 183fd045f6cSArd Biesheuvel */ 184fd045f6cSArd Biesheuvel s = syms + ELF64_R_SYM(rela[i].r_info); 18524af6c4eSArd Biesheuvel if (s->st_shndx == dstidx) 186fd045f6cSArd Biesheuvel break; 187fd045f6cSArd Biesheuvel 188fd045f6cSArd Biesheuvel /* 189fd045f6cSArd Biesheuvel * Jump relocations with non-zero addends against 190fd045f6cSArd Biesheuvel * undefined symbols are supported by the ELF spec, but 191fd045f6cSArd Biesheuvel * do not occur in practice (e.g., 'jump n bytes past 192fd045f6cSArd Biesheuvel * the entry point of undefined function symbol f'). 193fd045f6cSArd Biesheuvel * So we need to support them, but there is no need to 194fd045f6cSArd Biesheuvel * take them into consideration when trying to optimize 195fd045f6cSArd Biesheuvel * this code. So let's only check for duplicates when 196fd045f6cSArd Biesheuvel * the addend is zero: this allows us to record the PLT 197fd045f6cSArd Biesheuvel * entry address in the symbol table itself, rather than 198fd045f6cSArd Biesheuvel * having to search the list for duplicates each time we 199fd045f6cSArd Biesheuvel * emit one. 200fd045f6cSArd Biesheuvel */ 201fd045f6cSArd Biesheuvel if (rela[i].r_addend != 0 || !duplicate_rel(rela, i)) 202fd045f6cSArd Biesheuvel ret++; 203fd045f6cSArd Biesheuvel break; 204a257e025SArd Biesheuvel case R_AARCH64_ADR_PREL_PG_HI21_NC: 205a257e025SArd Biesheuvel case R_AARCH64_ADR_PREL_PG_HI21: 206ca79accaSArd Biesheuvel if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) || 207ca79accaSArd Biesheuvel !cpus_have_const_cap(ARM64_WORKAROUND_843419)) 208a257e025SArd Biesheuvel break; 209a257e025SArd Biesheuvel 210a257e025SArd Biesheuvel /* 211a257e025SArd Biesheuvel * Determine the minimal safe alignment for this ADRP 212a257e025SArd Biesheuvel * instruction: the section alignment at which it is 213a257e025SArd Biesheuvel * guaranteed not to appear at a vulnerable offset. 214a257e025SArd Biesheuvel * 215a257e025SArd Biesheuvel * This comes down to finding the least significant zero 216a257e025SArd Biesheuvel * bit in bits [11:3] of the section offset, and 217a257e025SArd Biesheuvel * increasing the section's alignment so that the 218a257e025SArd Biesheuvel * resulting address of this instruction is guaranteed 219a257e025SArd Biesheuvel * to equal the offset in that particular bit (as well 220dd671f16SJulia Lawall * as all less significant bits). This ensures that the 221a257e025SArd Biesheuvel * address modulo 4 KB != 0xfff8 or 0xfffc (which would 222a257e025SArd Biesheuvel * have all ones in bits [11:3]) 223a257e025SArd Biesheuvel */ 224a257e025SArd Biesheuvel min_align = 2ULL << ffz(rela[i].r_offset | 0x7); 225a257e025SArd Biesheuvel 226a257e025SArd Biesheuvel /* 227a257e025SArd Biesheuvel * Allocate veneer space for each ADRP that may appear 228a257e025SArd Biesheuvel * at a vulnerable offset nonetheless. At relocation 229a257e025SArd Biesheuvel * time, some of these will remain unused since some 230a257e025SArd Biesheuvel * ADRP instructions can be patched to ADR instructions 231a257e025SArd Biesheuvel * instead. 232a257e025SArd Biesheuvel */ 233a257e025SArd Biesheuvel if (min_align > SZ_4K) 234a257e025SArd Biesheuvel ret++; 235a257e025SArd Biesheuvel else 236a257e025SArd Biesheuvel dstsec->sh_addralign = max(dstsec->sh_addralign, 237a257e025SArd Biesheuvel min_align); 238a257e025SArd Biesheuvel break; 239fd045f6cSArd Biesheuvel } 240fd045f6cSArd Biesheuvel } 241bdb85cd1SArd Biesheuvel 242bdb85cd1SArd Biesheuvel if (IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) && 243bdb85cd1SArd Biesheuvel cpus_have_const_cap(ARM64_WORKAROUND_843419)) 244bdb85cd1SArd Biesheuvel /* 245bdb85cd1SArd Biesheuvel * Add some slack so we can skip PLT slots that may trigger 246bdb85cd1SArd Biesheuvel * the erratum due to the placement of the ADRP instruction. 247bdb85cd1SArd Biesheuvel */ 248bdb85cd1SArd Biesheuvel ret += DIV_ROUND_UP(ret, (SZ_4K / sizeof(struct plt_entry))); 249bdb85cd1SArd Biesheuvel 250fd045f6cSArd Biesheuvel return ret; 251fd045f6cSArd Biesheuvel } 252fd045f6cSArd Biesheuvel 253d4e03409SSaravana Kannan static bool branch_rela_needs_plt(Elf64_Sym *syms, Elf64_Rela *rela, 254d4e03409SSaravana Kannan Elf64_Word dstidx) 255d4e03409SSaravana Kannan { 256d4e03409SSaravana Kannan 257d4e03409SSaravana Kannan Elf64_Sym *s = syms + ELF64_R_SYM(rela->r_info); 258d4e03409SSaravana Kannan 259d4e03409SSaravana Kannan if (s->st_shndx == dstidx) 260d4e03409SSaravana Kannan return false; 261d4e03409SSaravana Kannan 262d4e03409SSaravana Kannan return ELF64_R_TYPE(rela->r_info) == R_AARCH64_JUMP26 || 263d4e03409SSaravana Kannan ELF64_R_TYPE(rela->r_info) == R_AARCH64_CALL26; 264d4e03409SSaravana Kannan } 265d4e03409SSaravana Kannan 266d4e03409SSaravana Kannan /* Group branch PLT relas at the front end of the array. */ 267d4e03409SSaravana Kannan static int partition_branch_plt_relas(Elf64_Sym *syms, Elf64_Rela *rela, 268d4e03409SSaravana Kannan int numrels, Elf64_Word dstidx) 269d4e03409SSaravana Kannan { 270d4e03409SSaravana Kannan int i = 0, j = numrels - 1; 271d4e03409SSaravana Kannan 272d4e03409SSaravana Kannan if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 273d4e03409SSaravana Kannan return 0; 274d4e03409SSaravana Kannan 275d4e03409SSaravana Kannan while (i < j) { 276d4e03409SSaravana Kannan if (branch_rela_needs_plt(syms, &rela[i], dstidx)) 277d4e03409SSaravana Kannan i++; 278d4e03409SSaravana Kannan else if (branch_rela_needs_plt(syms, &rela[j], dstidx)) 279d4e03409SSaravana Kannan swap(rela[i], rela[j]); 280d4e03409SSaravana Kannan else 281d4e03409SSaravana Kannan j--; 282d4e03409SSaravana Kannan } 283d4e03409SSaravana Kannan 284d4e03409SSaravana Kannan return i; 285d4e03409SSaravana Kannan } 286d4e03409SSaravana Kannan 287fd045f6cSArd Biesheuvel int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, 288fd045f6cSArd Biesheuvel char *secstrings, struct module *mod) 289fd045f6cSArd Biesheuvel { 29024af6c4eSArd Biesheuvel unsigned long core_plts = 0; 29124af6c4eSArd Biesheuvel unsigned long init_plts = 0; 292fd045f6cSArd Biesheuvel Elf64_Sym *syms = NULL; 293c8ebf64eSJessica Yu Elf_Shdr *pltsec, *tramp = NULL; 294fd045f6cSArd Biesheuvel int i; 295fd045f6cSArd Biesheuvel 296fd045f6cSArd Biesheuvel /* 297fd045f6cSArd Biesheuvel * Find the empty .plt section so we can expand it to store the PLT 298fd045f6cSArd Biesheuvel * entries. Record the symtab address as well. 299fd045f6cSArd Biesheuvel */ 300fd045f6cSArd Biesheuvel for (i = 0; i < ehdr->e_shnum; i++) { 30124af6c4eSArd Biesheuvel if (!strcmp(secstrings + sechdrs[i].sh_name, ".plt")) 302c8ebf64eSJessica Yu mod->arch.core.plt_shndx = i; 30324af6c4eSArd Biesheuvel else if (!strcmp(secstrings + sechdrs[i].sh_name, ".init.plt")) 304c8ebf64eSJessica Yu mod->arch.init.plt_shndx = i; 305e0328fedSJessica Yu else if (!strcmp(secstrings + sechdrs[i].sh_name, 306be0f272bSArd Biesheuvel ".text.ftrace_trampoline")) 307be0f272bSArd Biesheuvel tramp = sechdrs + i; 308fd045f6cSArd Biesheuvel else if (sechdrs[i].sh_type == SHT_SYMTAB) 309fd045f6cSArd Biesheuvel syms = (Elf64_Sym *)sechdrs[i].sh_addr; 310fd045f6cSArd Biesheuvel } 311fd045f6cSArd Biesheuvel 312c8ebf64eSJessica Yu if (!mod->arch.core.plt_shndx || !mod->arch.init.plt_shndx) { 31324af6c4eSArd Biesheuvel pr_err("%s: module PLT section(s) missing\n", mod->name); 314fd045f6cSArd Biesheuvel return -ENOEXEC; 315fd045f6cSArd Biesheuvel } 316fd045f6cSArd Biesheuvel if (!syms) { 317fd045f6cSArd Biesheuvel pr_err("%s: module symtab section missing\n", mod->name); 318fd045f6cSArd Biesheuvel return -ENOEXEC; 319fd045f6cSArd Biesheuvel } 320fd045f6cSArd Biesheuvel 321fd045f6cSArd Biesheuvel for (i = 0; i < ehdr->e_shnum; i++) { 322fd045f6cSArd Biesheuvel Elf64_Rela *rels = (void *)ehdr + sechdrs[i].sh_offset; 323d4e03409SSaravana Kannan int nents, numrels = sechdrs[i].sh_size / sizeof(Elf64_Rela); 324fd045f6cSArd Biesheuvel Elf64_Shdr *dstsec = sechdrs + sechdrs[i].sh_info; 325fd045f6cSArd Biesheuvel 326fd045f6cSArd Biesheuvel if (sechdrs[i].sh_type != SHT_RELA) 327fd045f6cSArd Biesheuvel continue; 328fd045f6cSArd Biesheuvel 329fd045f6cSArd Biesheuvel /* ignore relocations that operate on non-exec sections */ 330fd045f6cSArd Biesheuvel if (!(dstsec->sh_flags & SHF_EXECINSTR)) 331fd045f6cSArd Biesheuvel continue; 332fd045f6cSArd Biesheuvel 333d4e03409SSaravana Kannan /* 334d4e03409SSaravana Kannan * sort branch relocations requiring a PLT by type, symbol index 335d4e03409SSaravana Kannan * and addend 336d4e03409SSaravana Kannan */ 337d4e03409SSaravana Kannan nents = partition_branch_plt_relas(syms, rels, numrels, 338d4e03409SSaravana Kannan sechdrs[i].sh_info); 339d4e03409SSaravana Kannan if (nents) 340d4e03409SSaravana Kannan sort(rels, nents, sizeof(Elf64_Rela), cmp_rela, NULL); 341fd045f6cSArd Biesheuvel 342*f928f8b1SJames Morse if (!module_init_layout_section(secstrings + dstsec->sh_name)) 34324af6c4eSArd Biesheuvel core_plts += count_plts(syms, rels, numrels, 344a257e025SArd Biesheuvel sechdrs[i].sh_info, dstsec); 34524af6c4eSArd Biesheuvel else 34624af6c4eSArd Biesheuvel init_plts += count_plts(syms, rels, numrels, 347a257e025SArd Biesheuvel sechdrs[i].sh_info, dstsec); 348fd045f6cSArd Biesheuvel } 349fd045f6cSArd Biesheuvel 350c8ebf64eSJessica Yu pltsec = sechdrs + mod->arch.core.plt_shndx; 351c8ebf64eSJessica Yu pltsec->sh_type = SHT_NOBITS; 352c8ebf64eSJessica Yu pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC; 353c8ebf64eSJessica Yu pltsec->sh_addralign = L1_CACHE_BYTES; 354c8ebf64eSJessica Yu pltsec->sh_size = (core_plts + 1) * sizeof(struct plt_entry); 35524af6c4eSArd Biesheuvel mod->arch.core.plt_num_entries = 0; 35624af6c4eSArd Biesheuvel mod->arch.core.plt_max_entries = core_plts; 35724af6c4eSArd Biesheuvel 358c8ebf64eSJessica Yu pltsec = sechdrs + mod->arch.init.plt_shndx; 359c8ebf64eSJessica Yu pltsec->sh_type = SHT_NOBITS; 360c8ebf64eSJessica Yu pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC; 361c8ebf64eSJessica Yu pltsec->sh_addralign = L1_CACHE_BYTES; 362c8ebf64eSJessica Yu pltsec->sh_size = (init_plts + 1) * sizeof(struct plt_entry); 36324af6c4eSArd Biesheuvel mod->arch.init.plt_num_entries = 0; 36424af6c4eSArd Biesheuvel mod->arch.init.plt_max_entries = init_plts; 36524af6c4eSArd Biesheuvel 366be0f272bSArd Biesheuvel if (tramp) { 367be0f272bSArd Biesheuvel tramp->sh_type = SHT_NOBITS; 368be0f272bSArd Biesheuvel tramp->sh_flags = SHF_EXECINSTR | SHF_ALLOC; 369be0f272bSArd Biesheuvel tramp->sh_addralign = __alignof__(struct plt_entry); 3703b23e499STorsten Duwe tramp->sh_size = NR_FTRACE_PLTS * sizeof(struct plt_entry); 371be0f272bSArd Biesheuvel } 372be0f272bSArd Biesheuvel 373fd045f6cSArd Biesheuvel return 0; 374fd045f6cSArd Biesheuvel } 375