xref: /openbmc/linux/arch/arm64/kernel/head.S (revision f5ad1c74)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Low-level CPU initialisation
4 * Based on arch/arm/kernel/head.S
5 *
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
8 * Authors:	Catalin Marinas <catalin.marinas@arm.com>
9 *		Will Deacon <will.deacon@arm.com>
10 */
11
12#include <linux/linkage.h>
13#include <linux/init.h>
14#include <linux/irqchip/arm-gic-v3.h>
15#include <linux/pgtable.h>
16
17#include <asm/asm_pointer_auth.h>
18#include <asm/assembler.h>
19#include <asm/boot.h>
20#include <asm/ptrace.h>
21#include <asm/asm-offsets.h>
22#include <asm/cache.h>
23#include <asm/cputype.h>
24#include <asm/elf.h>
25#include <asm/image.h>
26#include <asm/kernel-pgtable.h>
27#include <asm/kvm_arm.h>
28#include <asm/memory.h>
29#include <asm/pgtable-hwdef.h>
30#include <asm/page.h>
31#include <asm/scs.h>
32#include <asm/smp.h>
33#include <asm/sysreg.h>
34#include <asm/thread_info.h>
35#include <asm/virt.h>
36
37#include "efi-header.S"
38
39#define __PHYS_OFFSET	KERNEL_START
40
41#if (PAGE_OFFSET & 0x1fffff) != 0
42#error PAGE_OFFSET must be at least 2MB aligned
43#endif
44
45/*
46 * Kernel startup entry point.
47 * ---------------------------
48 *
49 * The requirements are:
50 *   MMU = off, D-cache = off, I-cache = on or off,
51 *   x0 = physical address to the FDT blob.
52 *
53 * This code is mostly position independent so you call this at
54 * __pa(PAGE_OFFSET).
55 *
56 * Note that the callee-saved registers are used for storing variables
57 * that are useful before the MMU is enabled. The allocations are described
58 * in the entry routines.
59 */
60	__HEAD
61	/*
62	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
63	 */
64	efi_signature_nop			// special NOP to identity as PE/COFF executable
65	b	primary_entry			// branch to kernel start, magic
66	.quad	0				// Image load offset from start of RAM, little-endian
67	le64sym	_kernel_size_le			// Effective size of kernel image, little-endian
68	le64sym	_kernel_flags_le		// Informative flags, little-endian
69	.quad	0				// reserved
70	.quad	0				// reserved
71	.quad	0				// reserved
72	.ascii	ARM64_IMAGE_MAGIC		// Magic number
73	.long	.Lpe_header_offset		// Offset to the PE header.
74
75	__EFI_PE_HEADER
76
77	__INIT
78
79	/*
80	 * The following callee saved general purpose registers are used on the
81	 * primary lowlevel boot path:
82	 *
83	 *  Register   Scope                      Purpose
84	 *  x21        primary_entry() .. start_kernel()        FDT pointer passed at boot in x0
85	 *  x23        primary_entry() .. start_kernel()        physical misalignment/KASLR offset
86	 *  x28        __create_page_tables()                   callee preserved temp register
87	 *  x19/x20    __primary_switch()                       callee preserved temp registers
88	 *  x24        __primary_switch() .. relocate_kernel()  current RELR displacement
89	 */
90SYM_CODE_START(primary_entry)
91	bl	preserve_boot_args
92	bl	init_kernel_el			// w0=cpu_boot_mode
93	adrp	x23, __PHYS_OFFSET
94	and	x23, x23, MIN_KIMG_ALIGN - 1	// KASLR offset, defaults to 0
95	bl	set_cpu_boot_mode_flag
96	bl	__create_page_tables
97	/*
98	 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
99	 * details.
100	 * On return, the CPU will be ready for the MMU to be turned on and
101	 * the TCR will have been set.
102	 */
103	bl	__cpu_setup			// initialise processor
104	b	__primary_switch
105SYM_CODE_END(primary_entry)
106
107/*
108 * Preserve the arguments passed by the bootloader in x0 .. x3
109 */
110SYM_CODE_START_LOCAL(preserve_boot_args)
111	mov	x21, x0				// x21=FDT
112
113	adr_l	x0, boot_args			// record the contents of
114	stp	x21, x1, [x0]			// x0 .. x3 at kernel entry
115	stp	x2, x3, [x0, #16]
116
117	dmb	sy				// needed before dc ivac with
118						// MMU off
119
120	mov	x1, #0x20			// 4 x 8 bytes
121	b	__inval_dcache_area		// tail call
122SYM_CODE_END(preserve_boot_args)
123
124/*
125 * Macro to create a table entry to the next page.
126 *
127 *	tbl:	page table address
128 *	virt:	virtual address
129 *	shift:	#imm page table shift
130 *	ptrs:	#imm pointers per table page
131 *
132 * Preserves:	virt
133 * Corrupts:	ptrs, tmp1, tmp2
134 * Returns:	tbl -> next level table page address
135 */
136	.macro	create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
137	add	\tmp1, \tbl, #PAGE_SIZE
138	phys_to_pte \tmp2, \tmp1
139	orr	\tmp2, \tmp2, #PMD_TYPE_TABLE	// address of next table and entry type
140	lsr	\tmp1, \virt, #\shift
141	sub	\ptrs, \ptrs, #1
142	and	\tmp1, \tmp1, \ptrs		// table index
143	str	\tmp2, [\tbl, \tmp1, lsl #3]
144	add	\tbl, \tbl, #PAGE_SIZE		// next level table page
145	.endm
146
147/*
148 * Macro to populate page table entries, these entries can be pointers to the next level
149 * or last level entries pointing to physical memory.
150 *
151 *	tbl:	page table address
152 *	rtbl:	pointer to page table or physical memory
153 *	index:	start index to write
154 *	eindex:	end index to write - [index, eindex] written to
155 *	flags:	flags for pagetable entry to or in
156 *	inc:	increment to rtbl between each entry
157 *	tmp1:	temporary variable
158 *
159 * Preserves:	tbl, eindex, flags, inc
160 * Corrupts:	index, tmp1
161 * Returns:	rtbl
162 */
163	.macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
164.Lpe\@:	phys_to_pte \tmp1, \rtbl
165	orr	\tmp1, \tmp1, \flags	// tmp1 = table entry
166	str	\tmp1, [\tbl, \index, lsl #3]
167	add	\rtbl, \rtbl, \inc	// rtbl = pa next level
168	add	\index, \index, #1
169	cmp	\index, \eindex
170	b.ls	.Lpe\@
171	.endm
172
173/*
174 * Compute indices of table entries from virtual address range. If multiple entries
175 * were needed in the previous page table level then the next page table level is assumed
176 * to be composed of multiple pages. (This effectively scales the end index).
177 *
178 *	vstart:	virtual address of start of range
179 *	vend:	virtual address of end of range
180 *	shift:	shift used to transform virtual address into index
181 *	ptrs:	number of entries in page table
182 *	istart:	index in table corresponding to vstart
183 *	iend:	index in table corresponding to vend
184 *	count:	On entry: how many extra entries were required in previous level, scales
185 *			  our end index.
186 *		On exit: returns how many extra entries required for next page table level
187 *
188 * Preserves:	vstart, vend, shift, ptrs
189 * Returns:	istart, iend, count
190 */
191	.macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
192	lsr	\iend, \vend, \shift
193	mov	\istart, \ptrs
194	sub	\istart, \istart, #1
195	and	\iend, \iend, \istart	// iend = (vend >> shift) & (ptrs - 1)
196	mov	\istart, \ptrs
197	mul	\istart, \istart, \count
198	add	\iend, \iend, \istart	// iend += (count - 1) * ptrs
199					// our entries span multiple tables
200
201	lsr	\istart, \vstart, \shift
202	mov	\count, \ptrs
203	sub	\count, \count, #1
204	and	\istart, \istart, \count
205
206	sub	\count, \iend, \istart
207	.endm
208
209/*
210 * Map memory for specified virtual address range. Each level of page table needed supports
211 * multiple entries. If a level requires n entries the next page table level is assumed to be
212 * formed from n pages.
213 *
214 *	tbl:	location of page table
215 *	rtbl:	address to be used for first level page table entry (typically tbl + PAGE_SIZE)
216 *	vstart:	start address to map
217 *	vend:	end address to map - we map [vstart, vend]
218 *	flags:	flags to use to map last level entries
219 *	phys:	physical address corresponding to vstart - physical memory is contiguous
220 *	pgds:	the number of pgd entries
221 *
222 * Temporaries:	istart, iend, tmp, count, sv - these need to be different registers
223 * Preserves:	vstart, vend, flags
224 * Corrupts:	tbl, rtbl, istart, iend, tmp, count, sv
225 */
226	.macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
227	add \rtbl, \tbl, #PAGE_SIZE
228	mov \sv, \rtbl
229	mov \count, #0
230	compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
231	populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
232	mov \tbl, \sv
233	mov \sv, \rtbl
234
235#if SWAPPER_PGTABLE_LEVELS > 3
236	compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
237	populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
238	mov \tbl, \sv
239	mov \sv, \rtbl
240#endif
241
242#if SWAPPER_PGTABLE_LEVELS > 2
243	compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
244	populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
245	mov \tbl, \sv
246#endif
247
248	compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
249	bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
250	populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
251	.endm
252
253/*
254 * Setup the initial page tables. We only setup the barest amount which is
255 * required to get the kernel running. The following sections are required:
256 *   - identity mapping to enable the MMU (low address, TTBR0)
257 *   - first few MB of the kernel linear mapping to jump to once the MMU has
258 *     been enabled
259 */
260SYM_FUNC_START_LOCAL(__create_page_tables)
261	mov	x28, lr
262
263	/*
264	 * Invalidate the init page tables to avoid potential dirty cache lines
265	 * being evicted. Other page tables are allocated in rodata as part of
266	 * the kernel image, and thus are clean to the PoC per the boot
267	 * protocol.
268	 */
269	adrp	x0, init_pg_dir
270	adrp	x1, init_pg_end
271	sub	x1, x1, x0
272	bl	__inval_dcache_area
273
274	/*
275	 * Clear the init page tables.
276	 */
277	adrp	x0, init_pg_dir
278	adrp	x1, init_pg_end
279	sub	x1, x1, x0
2801:	stp	xzr, xzr, [x0], #16
281	stp	xzr, xzr, [x0], #16
282	stp	xzr, xzr, [x0], #16
283	stp	xzr, xzr, [x0], #16
284	subs	x1, x1, #64
285	b.ne	1b
286
287	mov	x7, SWAPPER_MM_MMUFLAGS
288
289	/*
290	 * Create the identity mapping.
291	 */
292	adrp	x0, idmap_pg_dir
293	adrp	x3, __idmap_text_start		// __pa(__idmap_text_start)
294
295#ifdef CONFIG_ARM64_VA_BITS_52
296	mrs_s	x6, SYS_ID_AA64MMFR2_EL1
297	and	x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
298	mov	x5, #52
299	cbnz	x6, 1f
300#endif
301	mov	x5, #VA_BITS_MIN
3021:
303	adr_l	x6, vabits_actual
304	str	x5, [x6]
305	dmb	sy
306	dc	ivac, x6		// Invalidate potentially stale cache line
307
308	/*
309	 * VA_BITS may be too small to allow for an ID mapping to be created
310	 * that covers system RAM if that is located sufficiently high in the
311	 * physical address space. So for the ID map, use an extended virtual
312	 * range in that case, and configure an additional translation level
313	 * if needed.
314	 *
315	 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
316	 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
317	 * this number conveniently equals the number of leading zeroes in
318	 * the physical address of __idmap_text_end.
319	 */
320	adrp	x5, __idmap_text_end
321	clz	x5, x5
322	cmp	x5, TCR_T0SZ(VA_BITS)	// default T0SZ small enough?
323	b.ge	1f			// .. then skip VA range extension
324
325	adr_l	x6, idmap_t0sz
326	str	x5, [x6]
327	dmb	sy
328	dc	ivac, x6		// Invalidate potentially stale cache line
329
330#if (VA_BITS < 48)
331#define EXTRA_SHIFT	(PGDIR_SHIFT + PAGE_SHIFT - 3)
332#define EXTRA_PTRS	(1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT))
333
334	/*
335	 * If VA_BITS < 48, we have to configure an additional table level.
336	 * First, we have to verify our assumption that the current value of
337	 * VA_BITS was chosen such that all translation levels are fully
338	 * utilised, and that lowering T0SZ will always result in an additional
339	 * translation level to be configured.
340	 */
341#if VA_BITS != EXTRA_SHIFT
342#error "Mismatch between VA_BITS and page size/number of translation levels"
343#endif
344
345	mov	x4, EXTRA_PTRS
346	create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6
347#else
348	/*
349	 * If VA_BITS == 48, we don't have to configure an additional
350	 * translation level, but the top-level table has more entries.
351	 */
352	mov	x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
353	str_l	x4, idmap_ptrs_per_pgd, x5
354#endif
3551:
356	ldr_l	x4, idmap_ptrs_per_pgd
357	mov	x5, x3				// __pa(__idmap_text_start)
358	adr_l	x6, __idmap_text_end		// __pa(__idmap_text_end)
359
360	map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
361
362	/*
363	 * Map the kernel image (starting with PHYS_OFFSET).
364	 */
365	adrp	x0, init_pg_dir
366	mov_q	x5, KIMAGE_VADDR		// compile time __va(_text)
367	add	x5, x5, x23			// add KASLR displacement
368	mov	x4, PTRS_PER_PGD
369	adrp	x6, _end			// runtime __pa(_end)
370	adrp	x3, _text			// runtime __pa(_text)
371	sub	x6, x6, x3			// _end - _text
372	add	x6, x6, x5			// runtime __va(_end)
373
374	map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
375
376	/*
377	 * Since the page tables have been populated with non-cacheable
378	 * accesses (MMU disabled), invalidate those tables again to
379	 * remove any speculatively loaded cache lines.
380	 */
381	dmb	sy
382
383	adrp	x0, idmap_pg_dir
384	adrp	x1, idmap_pg_end
385	sub	x1, x1, x0
386	bl	__inval_dcache_area
387
388	adrp	x0, init_pg_dir
389	adrp	x1, init_pg_end
390	sub	x1, x1, x0
391	bl	__inval_dcache_area
392
393	ret	x28
394SYM_FUNC_END(__create_page_tables)
395
396/*
397 * The following fragment of code is executed with the MMU enabled.
398 *
399 *   x0 = __PHYS_OFFSET
400 */
401SYM_FUNC_START_LOCAL(__primary_switched)
402	adrp	x4, init_thread_union
403	add	sp, x4, #THREAD_SIZE
404	adr_l	x5, init_task
405	msr	sp_el0, x5			// Save thread_info
406
407#ifdef CONFIG_ARM64_PTR_AUTH
408	__ptrauth_keys_init_cpu	x5, x6, x7, x8
409#endif
410
411	adr_l	x8, vectors			// load VBAR_EL1 with virtual
412	msr	vbar_el1, x8			// vector table address
413	isb
414
415	stp	xzr, x30, [sp, #-16]!
416	mov	x29, sp
417
418#ifdef CONFIG_SHADOW_CALL_STACK
419	adr_l	scs_sp, init_shadow_call_stack	// Set shadow call stack
420#endif
421
422	str_l	x21, __fdt_pointer, x5		// Save FDT pointer
423
424	ldr_l	x4, kimage_vaddr		// Save the offset between
425	sub	x4, x4, x0			// the kernel virtual and
426	str_l	x4, kimage_voffset, x5		// physical mappings
427
428	// Clear BSS
429	adr_l	x0, __bss_start
430	mov	x1, xzr
431	adr_l	x2, __bss_stop
432	sub	x2, x2, x0
433	bl	__pi_memset
434	dsb	ishst				// Make zero page visible to PTW
435
436#ifdef CONFIG_KASAN
437	bl	kasan_early_init
438#endif
439#ifdef CONFIG_RANDOMIZE_BASE
440	tst	x23, ~(MIN_KIMG_ALIGN - 1)	// already running randomized?
441	b.ne	0f
442	mov	x0, x21				// pass FDT address in x0
443	bl	kaslr_early_init		// parse FDT for KASLR options
444	cbz	x0, 0f				// KASLR disabled? just proceed
445	orr	x23, x23, x0			// record KASLR offset
446	ldp	x29, x30, [sp], #16		// we must enable KASLR, return
447	ret					// to __primary_switch()
4480:
449#endif
450	add	sp, sp, #16
451	mov	x29, #0
452	mov	x30, #0
453	b	start_kernel
454SYM_FUNC_END(__primary_switched)
455
456	.pushsection ".rodata", "a"
457SYM_DATA_START(kimage_vaddr)
458	.quad		_text
459SYM_DATA_END(kimage_vaddr)
460EXPORT_SYMBOL(kimage_vaddr)
461	.popsection
462
463/*
464 * end early head section, begin head code that is also used for
465 * hotplug and needs to have the same protections as the text region
466 */
467	.section ".idmap.text","awx"
468
469/*
470 * Starting from EL2 or EL1, configure the CPU to execute at the highest
471 * reachable EL supported by the kernel in a chosen default state. If dropping
472 * from EL2 to EL1, configure EL2 before configuring EL1.
473 *
474 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if
475 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET.
476 *
477 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
478 * booted in EL1 or EL2 respectively.
479 */
480SYM_FUNC_START(init_kernel_el)
481	mrs	x0, CurrentEL
482	cmp	x0, #CurrentEL_EL2
483	b.eq	init_el2
484
485SYM_INNER_LABEL(init_el1, SYM_L_LOCAL)
486	mov_q	x0, INIT_SCTLR_EL1_MMU_OFF
487	msr	sctlr_el1, x0
488	isb
489	mov_q	x0, INIT_PSTATE_EL1
490	msr	spsr_el1, x0
491	msr	elr_el1, lr
492	mov	w0, #BOOT_CPU_MODE_EL1
493	eret
494
495SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
496	mov_q	x0, INIT_SCTLR_EL2_MMU_OFF
497	msr	sctlr_el2, x0
498
499#ifdef CONFIG_ARM64_VHE
500	/*
501	 * Check for VHE being present. For the rest of the EL2 setup,
502	 * x2 being non-zero indicates that we do have VHE, and that the
503	 * kernel is intended to run at EL2.
504	 */
505	mrs	x2, id_aa64mmfr1_el1
506	ubfx	x2, x2, #ID_AA64MMFR1_VHE_SHIFT, #4
507#else
508	mov	x2, xzr
509#endif
510
511	/* Hyp configuration. */
512	mov_q	x0, HCR_HOST_NVHE_FLAGS
513	cbz	x2, set_hcr
514	mov_q	x0, HCR_HOST_VHE_FLAGS
515set_hcr:
516	msr	hcr_el2, x0
517	isb
518
519	/*
520	 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
521	 * This is not necessary for VHE, since the host kernel runs in EL2,
522	 * and EL0 accesses are configured in the later stage of boot process.
523	 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
524	 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
525	 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
526	 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
527	 * EL2.
528	 */
529	cbnz	x2, 1f
530	mrs	x0, cnthctl_el2
531	orr	x0, x0, #3			// Enable EL1 physical timers
532	msr	cnthctl_el2, x0
5331:
534	msr	cntvoff_el2, xzr		// Clear virtual offset
535
536#ifdef CONFIG_ARM_GIC_V3
537	/* GICv3 system register access */
538	mrs	x0, id_aa64pfr0_el1
539	ubfx	x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
540	cbz	x0, 3f
541
542	mrs_s	x0, SYS_ICC_SRE_EL2
543	orr	x0, x0, #ICC_SRE_EL2_SRE	// Set ICC_SRE_EL2.SRE==1
544	orr	x0, x0, #ICC_SRE_EL2_ENABLE	// Set ICC_SRE_EL2.Enable==1
545	msr_s	SYS_ICC_SRE_EL2, x0
546	isb					// Make sure SRE is now set
547	mrs_s	x0, SYS_ICC_SRE_EL2		// Read SRE back,
548	tbz	x0, #0, 3f			// and check that it sticks
549	msr_s	SYS_ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults
550
5513:
552#endif
553
554	/* Populate ID registers. */
555	mrs	x0, midr_el1
556	mrs	x1, mpidr_el1
557	msr	vpidr_el2, x0
558	msr	vmpidr_el2, x1
559
560#ifdef CONFIG_COMPAT
561	msr	hstr_el2, xzr			// Disable CP15 traps to EL2
562#endif
563
564	/* EL2 debug */
565	mrs	x1, id_aa64dfr0_el1
566	sbfx	x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
567	cmp	x0, #1
568	b.lt	4f				// Skip if no PMU present
569	mrs	x0, pmcr_el0			// Disable debug access traps
570	ubfx	x0, x0, #11, #5			// to EL2 and allow access to
5714:
572	csel	x3, xzr, x0, lt			// all PMU counters from EL1
573
574	/* Statistical profiling */
575	ubfx	x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
576	cbz	x0, 7f				// Skip if SPE not present
577	cbnz	x2, 6f				// VHE?
578	mrs_s	x4, SYS_PMBIDR_EL1		// If SPE available at EL2,
579	and	x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
580	cbnz	x4, 5f				// then permit sampling of physical
581	mov	x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
582		      1 << SYS_PMSCR_EL2_PA_SHIFT)
583	msr_s	SYS_PMSCR_EL2, x4		// addresses and physical counter
5845:
585	mov	x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
586	orr	x3, x3, x1			// If we don't have VHE, then
587	b	7f				// use EL1&0 translation.
5886:						// For VHE, use EL2 translation
589	orr	x3, x3, #MDCR_EL2_TPMS		// and disable access from EL1
5907:
591	msr	mdcr_el2, x3			// Configure debug traps
592
593	/* LORegions */
594	mrs	x1, id_aa64mmfr1_el1
595	ubfx	x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
596	cbz	x0, 1f
597	msr_s	SYS_LORC_EL1, xzr
5981:
599
600	/* Stage-2 translation */
601	msr	vttbr_el2, xzr
602
603	cbz	x2, install_el2_stub
604
605	isb
606	mov_q	x0, INIT_PSTATE_EL2
607	msr	spsr_el2, x0
608	msr	elr_el2, lr
609	mov	w0, #BOOT_CPU_MODE_EL2
610	eret
611
612SYM_INNER_LABEL(install_el2_stub, SYM_L_LOCAL)
613	/*
614	 * When VHE is not in use, early init of EL2 and EL1 needs to be
615	 * done here.
616	 * When VHE _is_ in use, EL1 will not be used in the host and
617	 * requires no configuration, and all non-hyp-specific EL2 setup
618	 * will be done via the _EL1 system register aliases in __cpu_setup.
619	 */
620	mov_q	x0, INIT_SCTLR_EL1_MMU_OFF
621	msr	sctlr_el1, x0
622
623	/* Coprocessor traps. */
624	mov	x0, #0x33ff
625	msr	cptr_el2, x0			// Disable copro. traps to EL2
626
627	/* SVE register access */
628	mrs	x1, id_aa64pfr0_el1
629	ubfx	x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
630	cbz	x1, 7f
631
632	bic	x0, x0, #CPTR_EL2_TZ		// Also disable SVE traps
633	msr	cptr_el2, x0			// Disable copro. traps to EL2
634	isb
635	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector
636	msr_s	SYS_ZCR_EL2, x1			// length for EL1.
637
638	/* Hypervisor stub */
6397:	adr_l	x0, __hyp_stub_vectors
640	msr	vbar_el2, x0
641
642	isb
643	mov	x0, #INIT_PSTATE_EL1
644	msr	spsr_el2, x0
645	msr	elr_el2, lr
646	mov	w0, #BOOT_CPU_MODE_EL2
647	eret
648SYM_FUNC_END(init_kernel_el)
649
650/*
651 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
652 * in w0. See arch/arm64/include/asm/virt.h for more info.
653 */
654SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag)
655	adr_l	x1, __boot_cpu_mode
656	cmp	w0, #BOOT_CPU_MODE_EL2
657	b.ne	1f
658	add	x1, x1, #4
6591:	str	w0, [x1]			// This CPU has booted in EL1
660	dmb	sy
661	dc	ivac, x1			// Invalidate potentially stale cache line
662	ret
663SYM_FUNC_END(set_cpu_boot_mode_flag)
664
665/*
666 * These values are written with the MMU off, but read with the MMU on.
667 * Writers will invalidate the corresponding address, discarding up to a
668 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
669 * sufficient alignment that the CWG doesn't overlap another section.
670 */
671	.pushsection ".mmuoff.data.write", "aw"
672/*
673 * We need to find out the CPU boot mode long after boot, so we need to
674 * store it in a writable variable.
675 *
676 * This is not in .bss, because we set it sufficiently early that the boot-time
677 * zeroing of .bss would clobber it.
678 */
679SYM_DATA_START(__boot_cpu_mode)
680	.long	BOOT_CPU_MODE_EL2
681	.long	BOOT_CPU_MODE_EL1
682SYM_DATA_END(__boot_cpu_mode)
683/*
684 * The booting CPU updates the failed status @__early_cpu_boot_status,
685 * with MMU turned off.
686 */
687SYM_DATA_START(__early_cpu_boot_status)
688	.quad 	0
689SYM_DATA_END(__early_cpu_boot_status)
690
691	.popsection
692
693	/*
694	 * This provides a "holding pen" for platforms to hold all secondary
695	 * cores are held until we're ready for them to initialise.
696	 */
697SYM_FUNC_START(secondary_holding_pen)
698	bl	init_kernel_el			// w0=cpu_boot_mode
699	bl	set_cpu_boot_mode_flag
700	mrs	x0, mpidr_el1
701	mov_q	x1, MPIDR_HWID_BITMASK
702	and	x0, x0, x1
703	adr_l	x3, secondary_holding_pen_release
704pen:	ldr	x4, [x3]
705	cmp	x4, x0
706	b.eq	secondary_startup
707	wfe
708	b	pen
709SYM_FUNC_END(secondary_holding_pen)
710
711	/*
712	 * Secondary entry point that jumps straight into the kernel. Only to
713	 * be used where CPUs are brought online dynamically by the kernel.
714	 */
715SYM_FUNC_START(secondary_entry)
716	bl	init_kernel_el			// w0=cpu_boot_mode
717	bl	set_cpu_boot_mode_flag
718	b	secondary_startup
719SYM_FUNC_END(secondary_entry)
720
721SYM_FUNC_START_LOCAL(secondary_startup)
722	/*
723	 * Common entry point for secondary CPUs.
724	 */
725	bl	__cpu_secondary_check52bitva
726	bl	__cpu_setup			// initialise processor
727	adrp	x1, swapper_pg_dir
728	bl	__enable_mmu
729	ldr	x8, =__secondary_switched
730	br	x8
731SYM_FUNC_END(secondary_startup)
732
733SYM_FUNC_START_LOCAL(__secondary_switched)
734	adr_l	x5, vectors
735	msr	vbar_el1, x5
736	isb
737
738	adr_l	x0, secondary_data
739	ldr	x1, [x0, #CPU_BOOT_STACK]	// get secondary_data.stack
740	cbz	x1, __secondary_too_slow
741	mov	sp, x1
742	ldr	x2, [x0, #CPU_BOOT_TASK]
743	cbz	x2, __secondary_too_slow
744	msr	sp_el0, x2
745	scs_load x2, x3
746	mov	x29, #0
747	mov	x30, #0
748
749#ifdef CONFIG_ARM64_PTR_AUTH
750	ptrauth_keys_init_cpu x2, x3, x4, x5
751#endif
752
753	b	secondary_start_kernel
754SYM_FUNC_END(__secondary_switched)
755
756SYM_FUNC_START_LOCAL(__secondary_too_slow)
757	wfe
758	wfi
759	b	__secondary_too_slow
760SYM_FUNC_END(__secondary_too_slow)
761
762/*
763 * The booting CPU updates the failed status @__early_cpu_boot_status,
764 * with MMU turned off.
765 *
766 * update_early_cpu_boot_status tmp, status
767 *  - Corrupts tmp1, tmp2
768 *  - Writes 'status' to __early_cpu_boot_status and makes sure
769 *    it is committed to memory.
770 */
771
772	.macro	update_early_cpu_boot_status status, tmp1, tmp2
773	mov	\tmp2, #\status
774	adr_l	\tmp1, __early_cpu_boot_status
775	str	\tmp2, [\tmp1]
776	dmb	sy
777	dc	ivac, \tmp1			// Invalidate potentially stale cache line
778	.endm
779
780/*
781 * Enable the MMU.
782 *
783 *  x0  = SCTLR_EL1 value for turning on the MMU.
784 *  x1  = TTBR1_EL1 value
785 *
786 * Returns to the caller via x30/lr. This requires the caller to be covered
787 * by the .idmap.text section.
788 *
789 * Checks if the selected granule size is supported by the CPU.
790 * If it isn't, park the CPU
791 */
792SYM_FUNC_START(__enable_mmu)
793	mrs	x2, ID_AA64MMFR0_EL1
794	ubfx	x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4
795	cmp	x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
796	b.ne	__no_granule_support
797	update_early_cpu_boot_status 0, x2, x3
798	adrp	x2, idmap_pg_dir
799	phys_to_ttbr x1, x1
800	phys_to_ttbr x2, x2
801	msr	ttbr0_el1, x2			// load TTBR0
802	offset_ttbr1 x1, x3
803	msr	ttbr1_el1, x1			// load TTBR1
804	isb
805	msr	sctlr_el1, x0
806	isb
807	/*
808	 * Invalidate the local I-cache so that any instructions fetched
809	 * speculatively from the PoC are discarded, since they may have
810	 * been dynamically patched at the PoU.
811	 */
812	ic	iallu
813	dsb	nsh
814	isb
815	ret
816SYM_FUNC_END(__enable_mmu)
817
818SYM_FUNC_START(__cpu_secondary_check52bitva)
819#ifdef CONFIG_ARM64_VA_BITS_52
820	ldr_l	x0, vabits_actual
821	cmp	x0, #52
822	b.ne	2f
823
824	mrs_s	x0, SYS_ID_AA64MMFR2_EL1
825	and	x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
826	cbnz	x0, 2f
827
828	update_early_cpu_boot_status \
829		CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
8301:	wfe
831	wfi
832	b	1b
833
834#endif
8352:	ret
836SYM_FUNC_END(__cpu_secondary_check52bitva)
837
838SYM_FUNC_START_LOCAL(__no_granule_support)
839	/* Indicate that this CPU can't boot and is stuck in the kernel */
840	update_early_cpu_boot_status \
841		CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
8421:
843	wfe
844	wfi
845	b	1b
846SYM_FUNC_END(__no_granule_support)
847
848#ifdef CONFIG_RELOCATABLE
849SYM_FUNC_START_LOCAL(__relocate_kernel)
850	/*
851	 * Iterate over each entry in the relocation table, and apply the
852	 * relocations in place.
853	 */
854	ldr	w9, =__rela_offset		// offset to reloc table
855	ldr	w10, =__rela_size		// size of reloc table
856
857	mov_q	x11, KIMAGE_VADDR		// default virtual offset
858	add	x11, x11, x23			// actual virtual offset
859	add	x9, x9, x11			// __va(.rela)
860	add	x10, x9, x10			// __va(.rela) + sizeof(.rela)
861
8620:	cmp	x9, x10
863	b.hs	1f
864	ldp	x12, x13, [x9], #24
865	ldr	x14, [x9, #-8]
866	cmp	w13, #R_AARCH64_RELATIVE
867	b.ne	0b
868	add	x14, x14, x23			// relocate
869	str	x14, [x12, x23]
870	b	0b
871
8721:
873#ifdef CONFIG_RELR
874	/*
875	 * Apply RELR relocations.
876	 *
877	 * RELR is a compressed format for storing relative relocations. The
878	 * encoded sequence of entries looks like:
879	 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ]
880	 *
881	 * i.e. start with an address, followed by any number of bitmaps. The
882	 * address entry encodes 1 relocation. The subsequent bitmap entries
883	 * encode up to 63 relocations each, at subsequent offsets following
884	 * the last address entry.
885	 *
886	 * The bitmap entries must have 1 in the least significant bit. The
887	 * assumption here is that an address cannot have 1 in lsb. Odd
888	 * addresses are not supported. Any odd addresses are stored in the RELA
889	 * section, which is handled above.
890	 *
891	 * Excluding the least significant bit in the bitmap, each non-zero
892	 * bit in the bitmap represents a relocation to be applied to
893	 * a corresponding machine word that follows the base address
894	 * word. The second least significant bit represents the machine
895	 * word immediately following the initial address, and each bit
896	 * that follows represents the next word, in linear order. As such,
897	 * a single bitmap can encode up to 63 relocations in a 64-bit object.
898	 *
899	 * In this implementation we store the address of the next RELR table
900	 * entry in x9, the address being relocated by the current address or
901	 * bitmap entry in x13 and the address being relocated by the current
902	 * bit in x14.
903	 *
904	 * Because addends are stored in place in the binary, RELR relocations
905	 * cannot be applied idempotently. We use x24 to keep track of the
906	 * currently applied displacement so that we can correctly relocate if
907	 * __relocate_kernel is called twice with non-zero displacements (i.e.
908	 * if there is both a physical misalignment and a KASLR displacement).
909	 */
910	ldr	w9, =__relr_offset		// offset to reloc table
911	ldr	w10, =__relr_size		// size of reloc table
912	add	x9, x9, x11			// __va(.relr)
913	add	x10, x9, x10			// __va(.relr) + sizeof(.relr)
914
915	sub	x15, x23, x24			// delta from previous offset
916	cbz	x15, 7f				// nothing to do if unchanged
917	mov	x24, x23			// save new offset
918
9192:	cmp	x9, x10
920	b.hs	7f
921	ldr	x11, [x9], #8
922	tbnz	x11, #0, 3f			// branch to handle bitmaps
923	add	x13, x11, x23
924	ldr	x12, [x13]			// relocate address entry
925	add	x12, x12, x15
926	str	x12, [x13], #8			// adjust to start of bitmap
927	b	2b
928
9293:	mov	x14, x13
9304:	lsr	x11, x11, #1
931	cbz	x11, 6f
932	tbz	x11, #0, 5f			// skip bit if not set
933	ldr	x12, [x14]			// relocate bit
934	add	x12, x12, x15
935	str	x12, [x14]
936
9375:	add	x14, x14, #8			// move to next bit's address
938	b	4b
939
9406:	/*
941	 * Move to the next bitmap's address. 8 is the word size, and 63 is the
942	 * number of significant bits in a bitmap entry.
943	 */
944	add	x13, x13, #(8 * 63)
945	b	2b
946
9477:
948#endif
949	ret
950
951SYM_FUNC_END(__relocate_kernel)
952#endif
953
954SYM_FUNC_START_LOCAL(__primary_switch)
955#ifdef CONFIG_RANDOMIZE_BASE
956	mov	x19, x0				// preserve new SCTLR_EL1 value
957	mrs	x20, sctlr_el1			// preserve old SCTLR_EL1 value
958#endif
959
960	adrp	x1, init_pg_dir
961	bl	__enable_mmu
962#ifdef CONFIG_RELOCATABLE
963#ifdef CONFIG_RELR
964	mov	x24, #0				// no RELR displacement yet
965#endif
966	bl	__relocate_kernel
967#ifdef CONFIG_RANDOMIZE_BASE
968	ldr	x8, =__primary_switched
969	adrp	x0, __PHYS_OFFSET
970	blr	x8
971
972	/*
973	 * If we return here, we have a KASLR displacement in x23 which we need
974	 * to take into account by discarding the current kernel mapping and
975	 * creating a new one.
976	 */
977	pre_disable_mmu_workaround
978	msr	sctlr_el1, x20			// disable the MMU
979	isb
980	bl	__create_page_tables		// recreate kernel mapping
981
982	tlbi	vmalle1				// Remove any stale TLB entries
983	dsb	nsh
984
985	msr	sctlr_el1, x19			// re-enable the MMU
986	isb
987	ic	iallu				// flush instructions fetched
988	dsb	nsh				// via old mapping
989	isb
990
991	bl	__relocate_kernel
992#endif
993#endif
994	ldr	x8, =__primary_switched
995	adrp	x0, __PHYS_OFFSET
996	br	x8
997SYM_FUNC_END(__primary_switch)
998