1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <linux/irqchip/arm-gic-v3.h> 26 27#include <asm/assembler.h> 28#include <asm/boot.h> 29#include <asm/ptrace.h> 30#include <asm/asm-offsets.h> 31#include <asm/cache.h> 32#include <asm/cputype.h> 33#include <asm/elf.h> 34#include <asm/kernel-pgtable.h> 35#include <asm/kvm_arm.h> 36#include <asm/memory.h> 37#include <asm/pgtable-hwdef.h> 38#include <asm/pgtable.h> 39#include <asm/page.h> 40#include <asm/smp.h> 41#include <asm/sysreg.h> 42#include <asm/thread_info.h> 43#include <asm/virt.h> 44 45#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) 46 47#if (TEXT_OFFSET & 0xfff) != 0 48#error TEXT_OFFSET must be at least 4KB aligned 49#elif (PAGE_OFFSET & 0x1fffff) != 0 50#error PAGE_OFFSET must be at least 2MB aligned 51#elif TEXT_OFFSET > 0x1fffff 52#error TEXT_OFFSET must be less than 2MB 53#endif 54 55/* 56 * Kernel startup entry point. 57 * --------------------------- 58 * 59 * The requirements are: 60 * MMU = off, D-cache = off, I-cache = on or off, 61 * x0 = physical address to the FDT blob. 62 * 63 * This code is mostly position independent so you call this at 64 * __pa(PAGE_OFFSET + TEXT_OFFSET). 65 * 66 * Note that the callee-saved registers are used for storing variables 67 * that are useful before the MMU is enabled. The allocations are described 68 * in the entry routines. 69 */ 70 __HEAD 71_head: 72 /* 73 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 74 */ 75#ifdef CONFIG_EFI 76 /* 77 * This add instruction has no meaningful effect except that 78 * its opcode forms the magic "MZ" signature required by UEFI. 79 */ 80 add x13, x18, #0x16 81 b stext 82#else 83 b stext // branch to kernel start, magic 84 .long 0 // reserved 85#endif 86 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian 87 le64sym _kernel_size_le // Effective size of kernel image, little-endian 88 le64sym _kernel_flags_le // Informative flags, little-endian 89 .quad 0 // reserved 90 .quad 0 // reserved 91 .quad 0 // reserved 92 .byte 0x41 // Magic number, "ARM\x64" 93 .byte 0x52 94 .byte 0x4d 95 .byte 0x64 96#ifdef CONFIG_EFI 97 .long pe_header - _head // Offset to the PE header. 98#else 99 .word 0 // reserved 100#endif 101 102#ifdef CONFIG_EFI 103 .align 3 104pe_header: 105 .ascii "PE" 106 .short 0 107coff_header: 108 .short 0xaa64 // AArch64 109 .short 2 // nr_sections 110 .long 0 // TimeDateStamp 111 .long 0 // PointerToSymbolTable 112 .long 1 // NumberOfSymbols 113 .short section_table - optional_header // SizeOfOptionalHeader 114 .short 0x206 // Characteristics. 115 // IMAGE_FILE_DEBUG_STRIPPED | 116 // IMAGE_FILE_EXECUTABLE_IMAGE | 117 // IMAGE_FILE_LINE_NUMS_STRIPPED 118optional_header: 119 .short 0x20b // PE32+ format 120 .byte 0x02 // MajorLinkerVersion 121 .byte 0x14 // MinorLinkerVersion 122 .long _end - efi_header_end // SizeOfCode 123 .long 0 // SizeOfInitializedData 124 .long 0 // SizeOfUninitializedData 125 .long __efistub_entry - _head // AddressOfEntryPoint 126 .long efi_header_end - _head // BaseOfCode 127 128extra_header_fields: 129 .quad 0 // ImageBase 130 .long 0x1000 // SectionAlignment 131 .long PECOFF_FILE_ALIGNMENT // FileAlignment 132 .short 0 // MajorOperatingSystemVersion 133 .short 0 // MinorOperatingSystemVersion 134 .short 0 // MajorImageVersion 135 .short 0 // MinorImageVersion 136 .short 0 // MajorSubsystemVersion 137 .short 0 // MinorSubsystemVersion 138 .long 0 // Win32VersionValue 139 140 .long _end - _head // SizeOfImage 141 142 // Everything before the kernel image is considered part of the header 143 .long efi_header_end - _head // SizeOfHeaders 144 .long 0 // CheckSum 145 .short 0xa // Subsystem (EFI application) 146 .short 0 // DllCharacteristics 147 .quad 0 // SizeOfStackReserve 148 .quad 0 // SizeOfStackCommit 149 .quad 0 // SizeOfHeapReserve 150 .quad 0 // SizeOfHeapCommit 151 .long 0 // LoaderFlags 152 .long 0x6 // NumberOfRvaAndSizes 153 154 .quad 0 // ExportTable 155 .quad 0 // ImportTable 156 .quad 0 // ResourceTable 157 .quad 0 // ExceptionTable 158 .quad 0 // CertificationTable 159 .quad 0 // BaseRelocationTable 160 161 // Section table 162section_table: 163 164 /* 165 * The EFI application loader requires a relocation section 166 * because EFI applications must be relocatable. This is a 167 * dummy section as far as we are concerned. 168 */ 169 .ascii ".reloc" 170 .byte 0 171 .byte 0 // end of 0 padding of section name 172 .long 0 173 .long 0 174 .long 0 // SizeOfRawData 175 .long 0 // PointerToRawData 176 .long 0 // PointerToRelocations 177 .long 0 // PointerToLineNumbers 178 .short 0 // NumberOfRelocations 179 .short 0 // NumberOfLineNumbers 180 .long 0x42100040 // Characteristics (section flags) 181 182 183 .ascii ".text" 184 .byte 0 185 .byte 0 186 .byte 0 // end of 0 padding of section name 187 .long _end - efi_header_end // VirtualSize 188 .long efi_header_end - _head // VirtualAddress 189 .long _edata - efi_header_end // SizeOfRawData 190 .long efi_header_end - _head // PointerToRawData 191 192 .long 0 // PointerToRelocations (0 for executables) 193 .long 0 // PointerToLineNumbers (0 for executables) 194 .short 0 // NumberOfRelocations (0 for executables) 195 .short 0 // NumberOfLineNumbers (0 for executables) 196 .long 0xe0500020 // Characteristics (section flags) 197 198 /* 199 * EFI will load .text onwards at the 4k section alignment 200 * described in the PE/COFF header. To ensure that instruction 201 * sequences using an adrp and a :lo12: immediate will function 202 * correctly at this alignment, we must ensure that .text is 203 * placed at a 4k boundary in the Image to begin with. 204 */ 205 .align 12 206efi_header_end: 207#endif 208 209 __INIT 210 211ENTRY(stext) 212 bl preserve_boot_args 213 bl el2_setup // Drop to EL1, w20=cpu_boot_mode 214 adrp x24, __PHYS_OFFSET 215 and x23, x24, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 216 bl set_cpu_boot_mode_flag 217 bl __create_page_tables // x25=TTBR0, x26=TTBR1 218 /* 219 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 220 * details. 221 * On return, the CPU will be ready for the MMU to be turned on and 222 * the TCR will have been set. 223 */ 224 bl __cpu_setup // initialise processor 225 adr_l x27, __primary_switch // address to jump to after 226 // MMU has been enabled 227 b __enable_mmu 228ENDPROC(stext) 229 230/* 231 * Preserve the arguments passed by the bootloader in x0 .. x3 232 */ 233preserve_boot_args: 234 mov x21, x0 // x21=FDT 235 236 adr_l x0, boot_args // record the contents of 237 stp x21, x1, [x0] // x0 .. x3 at kernel entry 238 stp x2, x3, [x0, #16] 239 240 dmb sy // needed before dc ivac with 241 // MMU off 242 243 add x1, x0, #0x20 // 4 x 8 bytes 244 b __inval_cache_range // tail call 245ENDPROC(preserve_boot_args) 246 247/* 248 * Macro to create a table entry to the next page. 249 * 250 * tbl: page table address 251 * virt: virtual address 252 * shift: #imm page table shift 253 * ptrs: #imm pointers per table page 254 * 255 * Preserves: virt 256 * Corrupts: tmp1, tmp2 257 * Returns: tbl -> next level table page address 258 */ 259 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 260 lsr \tmp1, \virt, #\shift 261 and \tmp1, \tmp1, #\ptrs - 1 // table index 262 add \tmp2, \tbl, #PAGE_SIZE 263 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 264 str \tmp2, [\tbl, \tmp1, lsl #3] 265 add \tbl, \tbl, #PAGE_SIZE // next level table page 266 .endm 267 268/* 269 * Macro to populate the PGD (and possibily PUD) for the corresponding 270 * block entry in the next level (tbl) for the given virtual address. 271 * 272 * Preserves: tbl, next, virt 273 * Corrupts: tmp1, tmp2 274 */ 275 .macro create_pgd_entry, tbl, virt, tmp1, tmp2 276 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 277#if SWAPPER_PGTABLE_LEVELS > 3 278 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2 279#endif 280#if SWAPPER_PGTABLE_LEVELS > 2 281 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 282#endif 283 .endm 284 285/* 286 * Macro to populate block entries in the page table for the start..end 287 * virtual range (inclusive). 288 * 289 * Preserves: tbl, flags 290 * Corrupts: phys, start, end, pstate 291 */ 292 .macro create_block_map, tbl, flags, phys, start, end 293 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT 294 lsr \start, \start, #SWAPPER_BLOCK_SHIFT 295 and \start, \start, #PTRS_PER_PTE - 1 // table index 296 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry 297 lsr \end, \end, #SWAPPER_BLOCK_SHIFT 298 and \end, \end, #PTRS_PER_PTE - 1 // table end index 2999999: str \phys, [\tbl, \start, lsl #3] // store the entry 300 add \start, \start, #1 // next entry 301 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block 302 cmp \start, \end 303 b.ls 9999b 304 .endm 305 306/* 307 * Setup the initial page tables. We only setup the barest amount which is 308 * required to get the kernel running. The following sections are required: 309 * - identity mapping to enable the MMU (low address, TTBR0) 310 * - first few MB of the kernel linear mapping to jump to once the MMU has 311 * been enabled 312 */ 313__create_page_tables: 314 adrp x25, idmap_pg_dir 315 adrp x26, swapper_pg_dir 316 mov x28, lr 317 318 /* 319 * Invalidate the idmap and swapper page tables to avoid potential 320 * dirty cache lines being evicted. 321 */ 322 mov x0, x25 323 add x1, x26, #SWAPPER_DIR_SIZE 324 bl __inval_cache_range 325 326 /* 327 * Clear the idmap and swapper page tables. 328 */ 329 mov x0, x25 330 add x6, x26, #SWAPPER_DIR_SIZE 3311: stp xzr, xzr, [x0], #16 332 stp xzr, xzr, [x0], #16 333 stp xzr, xzr, [x0], #16 334 stp xzr, xzr, [x0], #16 335 cmp x0, x6 336 b.lo 1b 337 338 mov x7, SWAPPER_MM_MMUFLAGS 339 340 /* 341 * Create the identity mapping. 342 */ 343 mov x0, x25 // idmap_pg_dir 344 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 345 346#ifndef CONFIG_ARM64_VA_BITS_48 347#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 348#define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) 349 350 /* 351 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be 352 * created that covers system RAM if that is located sufficiently high 353 * in the physical address space. So for the ID map, use an extended 354 * virtual range in that case, by configuring an additional translation 355 * level. 356 * First, we have to verify our assumption that the current value of 357 * VA_BITS was chosen such that all translation levels are fully 358 * utilised, and that lowering T0SZ will always result in an additional 359 * translation level to be configured. 360 */ 361#if VA_BITS != EXTRA_SHIFT 362#error "Mismatch between VA_BITS and page size/number of translation levels" 363#endif 364 365 /* 366 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 367 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 368 * this number conveniently equals the number of leading zeroes in 369 * the physical address of __idmap_text_end. 370 */ 371 adrp x5, __idmap_text_end 372 clz x5, x5 373 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 374 b.ge 1f // .. then skip additional level 375 376 adr_l x6, idmap_t0sz 377 str x5, [x6] 378 dmb sy 379 dc ivac, x6 // Invalidate potentially stale cache line 380 381 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 3821: 383#endif 384 385 create_pgd_entry x0, x3, x5, x6 386 mov x5, x3 // __pa(__idmap_text_start) 387 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 388 create_block_map x0, x7, x3, x5, x6 389 390 /* 391 * Map the kernel image (starting with PHYS_OFFSET). 392 */ 393 mov x0, x26 // swapper_pg_dir 394 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) 395 add x5, x5, x23 // add KASLR displacement 396 create_pgd_entry x0, x5, x3, x6 397 adrp x6, _end // runtime __pa(_end) 398 adrp x3, _text // runtime __pa(_text) 399 sub x6, x6, x3 // _end - _text 400 add x6, x6, x5 // runtime __va(_end) 401 create_block_map x0, x7, x3, x5, x6 402 403 /* 404 * Since the page tables have been populated with non-cacheable 405 * accesses (MMU disabled), invalidate the idmap and swapper page 406 * tables again to remove any speculatively loaded cache lines. 407 */ 408 mov x0, x25 409 add x1, x26, #SWAPPER_DIR_SIZE 410 dmb sy 411 bl __inval_cache_range 412 413 ret x28 414ENDPROC(__create_page_tables) 415 .ltorg 416 417/* 418 * The following fragment of code is executed with the MMU enabled. 419 */ 420 .set initial_sp, init_thread_union + THREAD_START_SP 421__primary_switched: 422 mov x28, lr // preserve LR 423 adr_l x8, vectors // load VBAR_EL1 with virtual 424 msr vbar_el1, x8 // vector table address 425 isb 426 427 // Clear BSS 428 adr_l x0, __bss_start 429 mov x1, xzr 430 adr_l x2, __bss_stop 431 sub x2, x2, x0 432 bl __pi_memset 433 dsb ishst // Make zero page visible to PTW 434 435 adr_l sp, initial_sp, x4 436 mov x4, sp 437 and x4, x4, #~(THREAD_SIZE - 1) 438 msr sp_el0, x4 // Save thread_info 439 str_l x21, __fdt_pointer, x5 // Save FDT pointer 440 441 ldr_l x4, kimage_vaddr // Save the offset between 442 sub x4, x4, x24 // the kernel virtual and 443 str_l x4, kimage_voffset, x5 // physical mappings 444 445 mov x29, #0 446#ifdef CONFIG_KASAN 447 bl kasan_early_init 448#endif 449#ifdef CONFIG_RANDOMIZE_BASE 450 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 451 b.ne 0f 452 mov x0, x21 // pass FDT address in x0 453 mov x1, x23 // pass modulo offset in x1 454 bl kaslr_early_init // parse FDT for KASLR options 455 cbz x0, 0f // KASLR disabled? just proceed 456 orr x23, x23, x0 // record KASLR offset 457 ret x28 // we must enable KASLR, return 458 // to __enable_mmu() 4590: 460#endif 461 b start_kernel 462ENDPROC(__primary_switched) 463 464/* 465 * end early head section, begin head code that is also used for 466 * hotplug and needs to have the same protections as the text region 467 */ 468 .section ".text","ax" 469 470ENTRY(kimage_vaddr) 471 .quad _text - TEXT_OFFSET 472 473/* 474 * If we're fortunate enough to boot at EL2, ensure that the world is 475 * sane before dropping to EL1. 476 * 477 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if 478 * booted in EL1 or EL2 respectively. 479 */ 480ENTRY(el2_setup) 481 mrs x0, CurrentEL 482 cmp x0, #CurrentEL_EL2 483 b.ne 1f 484 mrs x0, sctlr_el2 485CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 486CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 487 msr sctlr_el2, x0 488 b 2f 4891: mrs x0, sctlr_el1 490CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 491CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 492 msr sctlr_el1, x0 493 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 494 isb 495 ret 496 4972: 498#ifdef CONFIG_ARM64_VHE 499 /* 500 * Check for VHE being present. For the rest of the EL2 setup, 501 * x2 being non-zero indicates that we do have VHE, and that the 502 * kernel is intended to run at EL2. 503 */ 504 mrs x2, id_aa64mmfr1_el1 505 ubfx x2, x2, #8, #4 506#else 507 mov x2, xzr 508#endif 509 510 /* Hyp configuration. */ 511 mov x0, #HCR_RW // 64-bit EL1 512 cbz x2, set_hcr 513 orr x0, x0, #HCR_TGE // Enable Host Extensions 514 orr x0, x0, #HCR_E2H 515set_hcr: 516 msr hcr_el2, x0 517 isb 518 519 /* Generic timers. */ 520 mrs x0, cnthctl_el2 521 orr x0, x0, #3 // Enable EL1 physical timers 522 msr cnthctl_el2, x0 523 msr cntvoff_el2, xzr // Clear virtual offset 524 525#ifdef CONFIG_ARM_GIC_V3 526 /* GICv3 system register access */ 527 mrs x0, id_aa64pfr0_el1 528 ubfx x0, x0, #24, #4 529 cmp x0, #1 530 b.ne 3f 531 532 mrs_s x0, ICC_SRE_EL2 533 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 534 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 535 msr_s ICC_SRE_EL2, x0 536 isb // Make sure SRE is now set 537 mrs_s x0, ICC_SRE_EL2 // Read SRE back, 538 tbz x0, #0, 3f // and check that it sticks 539 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 540 5413: 542#endif 543 544 /* Populate ID registers. */ 545 mrs x0, midr_el1 546 mrs x1, mpidr_el1 547 msr vpidr_el2, x0 548 msr vmpidr_el2, x1 549 550 /* 551 * When VHE is not in use, early init of EL2 and EL1 needs to be 552 * done here. 553 * When VHE _is_ in use, EL1 will not be used in the host and 554 * requires no configuration, and all non-hyp-specific EL2 setup 555 * will be done via the _EL1 system register aliases in __cpu_setup. 556 */ 557 cbnz x2, 1f 558 559 /* sctlr_el1 */ 560 mov x0, #0x0800 // Set/clear RES{1,0} bits 561CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems 562CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems 563 msr sctlr_el1, x0 564 565 /* Coprocessor traps. */ 566 mov x0, #0x33ff 567 msr cptr_el2, x0 // Disable copro. traps to EL2 5681: 569 570#ifdef CONFIG_COMPAT 571 msr hstr_el2, xzr // Disable CP15 traps to EL2 572#endif 573 574 /* EL2 debug */ 575 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer 576 sbfx x0, x0, #8, #4 577 cmp x0, #1 578 b.lt 4f // Skip if no PMU present 579 mrs x0, pmcr_el0 // Disable debug access traps 580 ubfx x0, x0, #11, #5 // to EL2 and allow access to 581 msr mdcr_el2, x0 // all PMU counters from EL1 5824: 583 584 /* Stage-2 translation */ 585 msr vttbr_el2, xzr 586 587 cbz x2, install_el2_stub 588 589 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 590 isb 591 ret 592 593install_el2_stub: 594 /* Hypervisor stub */ 595 adrp x0, __hyp_stub_vectors 596 add x0, x0, #:lo12:__hyp_stub_vectors 597 msr vbar_el2, x0 598 599 /* spsr */ 600 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 601 PSR_MODE_EL1h) 602 msr spsr_el2, x0 603 msr elr_el2, lr 604 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 605 eret 606ENDPROC(el2_setup) 607 608/* 609 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 610 * in x20. See arch/arm64/include/asm/virt.h for more info. 611 */ 612set_cpu_boot_mode_flag: 613 adr_l x1, __boot_cpu_mode 614 cmp w20, #BOOT_CPU_MODE_EL2 615 b.ne 1f 616 add x1, x1, #4 6171: str w20, [x1] // This CPU has booted in EL1 618 dmb sy 619 dc ivac, x1 // Invalidate potentially stale cache line 620 ret 621ENDPROC(set_cpu_boot_mode_flag) 622 623/* 624 * We need to find out the CPU boot mode long after boot, so we need to 625 * store it in a writable variable. 626 * 627 * This is not in .bss, because we set it sufficiently early that the boot-time 628 * zeroing of .bss would clobber it. 629 */ 630 .pushsection .data..cacheline_aligned 631 .align L1_CACHE_SHIFT 632ENTRY(__boot_cpu_mode) 633 .long BOOT_CPU_MODE_EL2 634 .long BOOT_CPU_MODE_EL1 635 .popsection 636 637 /* 638 * This provides a "holding pen" for platforms to hold all secondary 639 * cores are held until we're ready for them to initialise. 640 */ 641ENTRY(secondary_holding_pen) 642 bl el2_setup // Drop to EL1, w20=cpu_boot_mode 643 bl set_cpu_boot_mode_flag 644 mrs x0, mpidr_el1 645 mov_q x1, MPIDR_HWID_BITMASK 646 and x0, x0, x1 647 adr_l x3, secondary_holding_pen_release 648pen: ldr x4, [x3] 649 cmp x4, x0 650 b.eq secondary_startup 651 wfe 652 b pen 653ENDPROC(secondary_holding_pen) 654 655 /* 656 * Secondary entry point that jumps straight into the kernel. Only to 657 * be used where CPUs are brought online dynamically by the kernel. 658 */ 659ENTRY(secondary_entry) 660 bl el2_setup // Drop to EL1 661 bl set_cpu_boot_mode_flag 662 b secondary_startup 663ENDPROC(secondary_entry) 664 665secondary_startup: 666 /* 667 * Common entry point for secondary CPUs. 668 */ 669 adrp x25, idmap_pg_dir 670 adrp x26, swapper_pg_dir 671 bl __cpu_setup // initialise processor 672 673 adr_l x27, __secondary_switch // address to jump to after enabling the MMU 674 b __enable_mmu 675ENDPROC(secondary_startup) 676 677__secondary_switched: 678 adr_l x5, vectors 679 msr vbar_el1, x5 680 isb 681 682 adr_l x0, secondary_data 683 ldr x0, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 684 mov sp, x0 685 and x0, x0, #~(THREAD_SIZE - 1) 686 msr sp_el0, x0 // save thread_info 687 mov x29, #0 688 b secondary_start_kernel 689ENDPROC(__secondary_switched) 690 691/* 692 * The booting CPU updates the failed status @__early_cpu_boot_status, 693 * with MMU turned off. 694 * 695 * update_early_cpu_boot_status tmp, status 696 * - Corrupts tmp1, tmp2 697 * - Writes 'status' to __early_cpu_boot_status and makes sure 698 * it is committed to memory. 699 */ 700 701 .macro update_early_cpu_boot_status status, tmp1, tmp2 702 mov \tmp2, #\status 703 adr_l \tmp1, __early_cpu_boot_status 704 str \tmp2, [\tmp1] 705 dmb sy 706 dc ivac, \tmp1 // Invalidate potentially stale cache line 707 .endm 708 709 .pushsection .data..cacheline_aligned 710 .align L1_CACHE_SHIFT 711ENTRY(__early_cpu_boot_status) 712 .long 0 713 .popsection 714 715/* 716 * Enable the MMU. 717 * 718 * x0 = SCTLR_EL1 value for turning on the MMU. 719 * x27 = *virtual* address to jump to upon completion 720 * 721 * Other registers depend on the function called upon completion. 722 * 723 * Checks if the selected granule size is supported by the CPU. 724 * If it isn't, park the CPU 725 */ 726 .section ".idmap.text", "ax" 727ENTRY(__enable_mmu) 728 mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value 729 mrs x1, ID_AA64MMFR0_EL1 730 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 731 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED 732 b.ne __no_granule_support 733 update_early_cpu_boot_status 0, x1, x2 734 msr ttbr0_el1, x25 // load TTBR0 735 msr ttbr1_el1, x26 // load TTBR1 736 isb 737 msr sctlr_el1, x0 738 isb 739 /* 740 * Invalidate the local I-cache so that any instructions fetched 741 * speculatively from the PoC are discarded, since they may have 742 * been dynamically patched at the PoU. 743 */ 744 ic iallu 745 dsb nsh 746 isb 747#ifdef CONFIG_RANDOMIZE_BASE 748 mov x19, x0 // preserve new SCTLR_EL1 value 749 blr x27 750 751 /* 752 * If we return here, we have a KASLR displacement in x23 which we need 753 * to take into account by discarding the current kernel mapping and 754 * creating a new one. 755 */ 756 msr sctlr_el1, x22 // disable the MMU 757 isb 758 bl __create_page_tables // recreate kernel mapping 759 760 msr sctlr_el1, x19 // re-enable the MMU 761 isb 762 ic iallu // flush instructions fetched 763 dsb nsh // via old mapping 764 isb 765#endif 766 br x27 767ENDPROC(__enable_mmu) 768 769__no_granule_support: 770 /* Indicate that this CPU can't boot and is stuck in the kernel */ 771 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 7721: 773 wfe 774 wfi 775 b 1b 776ENDPROC(__no_granule_support) 777 778__primary_switch: 779#ifdef CONFIG_RELOCATABLE 780 /* 781 * Iterate over each entry in the relocation table, and apply the 782 * relocations in place. 783 */ 784 ldr w9, =__rela_offset // offset to reloc table 785 ldr w10, =__rela_size // size of reloc table 786 787 mov_q x11, KIMAGE_VADDR // default virtual offset 788 add x11, x11, x23 // actual virtual offset 789 add x9, x9, x11 // __va(.rela) 790 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 791 7920: cmp x9, x10 793 b.hs 1f 794 ldp x11, x12, [x9], #24 795 ldr x13, [x9, #-8] 796 cmp w12, #R_AARCH64_RELATIVE 797 b.ne 0b 798 add x13, x13, x23 // relocate 799 str x13, [x11, x23] 800 b 0b 801 8021: 803#endif 804 ldr x8, =__primary_switched 805 br x8 806ENDPROC(__primary_switch) 807 808__secondary_switch: 809 ldr x8, =__secondary_switched 810 br x8 811ENDPROC(__secondary_switch) 812