1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <linux/irqchip/arm-gic-v3.h> 26 27#include <asm/assembler.h> 28#include <asm/ptrace.h> 29#include <asm/asm-offsets.h> 30#include <asm/cache.h> 31#include <asm/cputype.h> 32#include <asm/memory.h> 33#include <asm/thread_info.h> 34#include <asm/pgtable-hwdef.h> 35#include <asm/pgtable.h> 36#include <asm/page.h> 37#include <asm/virt.h> 38 39#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) 40 41#if (TEXT_OFFSET & 0xfff) != 0 42#error TEXT_OFFSET must be at least 4KB aligned 43#elif (PAGE_OFFSET & 0x1fffff) != 0 44#error PAGE_OFFSET must be at least 2MB aligned 45#elif TEXT_OFFSET > 0x1fffff 46#error TEXT_OFFSET must be less than 2MB 47#endif 48 49#ifdef CONFIG_ARM64_64K_PAGES 50#define BLOCK_SHIFT PAGE_SHIFT 51#define BLOCK_SIZE PAGE_SIZE 52#define TABLE_SHIFT PMD_SHIFT 53#else 54#define BLOCK_SHIFT SECTION_SHIFT 55#define BLOCK_SIZE SECTION_SIZE 56#define TABLE_SHIFT PUD_SHIFT 57#endif 58 59#define KERNEL_START _text 60#define KERNEL_END _end 61 62/* 63 * Initial memory map attributes. 64 */ 65#ifndef CONFIG_SMP 66#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF 67#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF 68#else 69#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED 70#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S 71#endif 72 73#ifdef CONFIG_ARM64_64K_PAGES 74#define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS 75#else 76#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS 77#endif 78 79/* 80 * Kernel startup entry point. 81 * --------------------------- 82 * 83 * The requirements are: 84 * MMU = off, D-cache = off, I-cache = on or off, 85 * x0 = physical address to the FDT blob. 86 * 87 * This code is mostly position independent so you call this at 88 * __pa(PAGE_OFFSET + TEXT_OFFSET). 89 * 90 * Note that the callee-saved registers are used for storing variables 91 * that are useful before the MMU is enabled. The allocations are described 92 * in the entry routines. 93 */ 94 __HEAD 95 96 /* 97 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 98 */ 99#ifdef CONFIG_EFI 100efi_head: 101 /* 102 * This add instruction has no meaningful effect except that 103 * its opcode forms the magic "MZ" signature required by UEFI. 104 */ 105 add x13, x18, #0x16 106 b stext 107#else 108 b stext // branch to kernel start, magic 109 .long 0 // reserved 110#endif 111 .quad _kernel_offset_le // Image load offset from start of RAM, little-endian 112 .quad _kernel_size_le // Effective size of kernel image, little-endian 113 .quad _kernel_flags_le // Informative flags, little-endian 114 .quad 0 // reserved 115 .quad 0 // reserved 116 .quad 0 // reserved 117 .byte 0x41 // Magic number, "ARM\x64" 118 .byte 0x52 119 .byte 0x4d 120 .byte 0x64 121#ifdef CONFIG_EFI 122 .long pe_header - efi_head // Offset to the PE header. 123#else 124 .word 0 // reserved 125#endif 126 127#ifdef CONFIG_EFI 128 .globl stext_offset 129 .set stext_offset, stext - efi_head 130 .align 3 131pe_header: 132 .ascii "PE" 133 .short 0 134coff_header: 135 .short 0xaa64 // AArch64 136 .short 2 // nr_sections 137 .long 0 // TimeDateStamp 138 .long 0 // PointerToSymbolTable 139 .long 1 // NumberOfSymbols 140 .short section_table - optional_header // SizeOfOptionalHeader 141 .short 0x206 // Characteristics. 142 // IMAGE_FILE_DEBUG_STRIPPED | 143 // IMAGE_FILE_EXECUTABLE_IMAGE | 144 // IMAGE_FILE_LINE_NUMS_STRIPPED 145optional_header: 146 .short 0x20b // PE32+ format 147 .byte 0x02 // MajorLinkerVersion 148 .byte 0x14 // MinorLinkerVersion 149 .long _end - stext // SizeOfCode 150 .long 0 // SizeOfInitializedData 151 .long 0 // SizeOfUninitializedData 152 .long efi_stub_entry - efi_head // AddressOfEntryPoint 153 .long stext_offset // BaseOfCode 154 155extra_header_fields: 156 .quad 0 // ImageBase 157 .long 0x1000 // SectionAlignment 158 .long PECOFF_FILE_ALIGNMENT // FileAlignment 159 .short 0 // MajorOperatingSystemVersion 160 .short 0 // MinorOperatingSystemVersion 161 .short 0 // MajorImageVersion 162 .short 0 // MinorImageVersion 163 .short 0 // MajorSubsystemVersion 164 .short 0 // MinorSubsystemVersion 165 .long 0 // Win32VersionValue 166 167 .long _end - efi_head // SizeOfImage 168 169 // Everything before the kernel image is considered part of the header 170 .long stext_offset // SizeOfHeaders 171 .long 0 // CheckSum 172 .short 0xa // Subsystem (EFI application) 173 .short 0 // DllCharacteristics 174 .quad 0 // SizeOfStackReserve 175 .quad 0 // SizeOfStackCommit 176 .quad 0 // SizeOfHeapReserve 177 .quad 0 // SizeOfHeapCommit 178 .long 0 // LoaderFlags 179 .long 0x6 // NumberOfRvaAndSizes 180 181 .quad 0 // ExportTable 182 .quad 0 // ImportTable 183 .quad 0 // ResourceTable 184 .quad 0 // ExceptionTable 185 .quad 0 // CertificationTable 186 .quad 0 // BaseRelocationTable 187 188 // Section table 189section_table: 190 191 /* 192 * The EFI application loader requires a relocation section 193 * because EFI applications must be relocatable. This is a 194 * dummy section as far as we are concerned. 195 */ 196 .ascii ".reloc" 197 .byte 0 198 .byte 0 // end of 0 padding of section name 199 .long 0 200 .long 0 201 .long 0 // SizeOfRawData 202 .long 0 // PointerToRawData 203 .long 0 // PointerToRelocations 204 .long 0 // PointerToLineNumbers 205 .short 0 // NumberOfRelocations 206 .short 0 // NumberOfLineNumbers 207 .long 0x42100040 // Characteristics (section flags) 208 209 210 .ascii ".text" 211 .byte 0 212 .byte 0 213 .byte 0 // end of 0 padding of section name 214 .long _end - stext // VirtualSize 215 .long stext_offset // VirtualAddress 216 .long _edata - stext // SizeOfRawData 217 .long stext_offset // PointerToRawData 218 219 .long 0 // PointerToRelocations (0 for executables) 220 .long 0 // PointerToLineNumbers (0 for executables) 221 .short 0 // NumberOfRelocations (0 for executables) 222 .short 0 // NumberOfLineNumbers (0 for executables) 223 .long 0xe0500020 // Characteristics (section flags) 224 225 /* 226 * EFI will load stext onwards at the 4k section alignment 227 * described in the PE/COFF header. To ensure that instruction 228 * sequences using an adrp and a :lo12: immediate will function 229 * correctly at this alignment, we must ensure that stext is 230 * placed at a 4k boundary in the Image to begin with. 231 */ 232 .align 12 233#endif 234 235ENTRY(stext) 236 bl preserve_boot_args 237 bl el2_setup // Drop to EL1, w20=cpu_boot_mode 238 adrp x24, __PHYS_OFFSET 239 bl set_cpu_boot_mode_flag 240 241 bl __vet_fdt 242 bl __create_page_tables // x25=TTBR0, x26=TTBR1 243 /* 244 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 245 * details. 246 * On return, the CPU will be ready for the MMU to be turned on and 247 * the TCR will have been set. 248 */ 249 ldr x27, =__mmap_switched // address to jump to after 250 // MMU has been enabled 251 adr_l lr, __enable_mmu // return (PIC) address 252 b __cpu_setup // initialise processor 253ENDPROC(stext) 254 255/* 256 * Preserve the arguments passed by the bootloader in x0 .. x3 257 */ 258preserve_boot_args: 259 mov x21, x0 // x21=FDT 260 261 adr_l x0, boot_args // record the contents of 262 stp x21, x1, [x0] // x0 .. x3 at kernel entry 263 stp x2, x3, [x0, #16] 264 265 dmb sy // needed before dc ivac with 266 // MMU off 267 268 add x1, x0, #0x20 // 4 x 8 bytes 269 b __inval_cache_range // tail call 270ENDPROC(preserve_boot_args) 271 272/* 273 * Determine validity of the x21 FDT pointer. 274 * The dtb must be 8-byte aligned and live in the first 512M of memory. 275 */ 276__vet_fdt: 277 tst x21, #0x7 278 b.ne 1f 279 cmp x21, x24 280 b.lt 1f 281 mov x0, #(1 << 29) 282 add x0, x0, x24 283 cmp x21, x0 284 b.ge 1f 285 ret 2861: 287 mov x21, #0 288 ret 289ENDPROC(__vet_fdt) 290/* 291 * Macro to create a table entry to the next page. 292 * 293 * tbl: page table address 294 * virt: virtual address 295 * shift: #imm page table shift 296 * ptrs: #imm pointers per table page 297 * 298 * Preserves: virt 299 * Corrupts: tmp1, tmp2 300 * Returns: tbl -> next level table page address 301 */ 302 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 303 lsr \tmp1, \virt, #\shift 304 and \tmp1, \tmp1, #\ptrs - 1 // table index 305 add \tmp2, \tbl, #PAGE_SIZE 306 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 307 str \tmp2, [\tbl, \tmp1, lsl #3] 308 add \tbl, \tbl, #PAGE_SIZE // next level table page 309 .endm 310 311/* 312 * Macro to populate the PGD (and possibily PUD) for the corresponding 313 * block entry in the next level (tbl) for the given virtual address. 314 * 315 * Preserves: tbl, next, virt 316 * Corrupts: tmp1, tmp2 317 */ 318 .macro create_pgd_entry, tbl, virt, tmp1, tmp2 319 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 320#if SWAPPER_PGTABLE_LEVELS == 3 321 create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 322#endif 323 .endm 324 325/* 326 * Macro to populate block entries in the page table for the start..end 327 * virtual range (inclusive). 328 * 329 * Preserves: tbl, flags 330 * Corrupts: phys, start, end, pstate 331 */ 332 .macro create_block_map, tbl, flags, phys, start, end 333 lsr \phys, \phys, #BLOCK_SHIFT 334 lsr \start, \start, #BLOCK_SHIFT 335 and \start, \start, #PTRS_PER_PTE - 1 // table index 336 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry 337 lsr \end, \end, #BLOCK_SHIFT 338 and \end, \end, #PTRS_PER_PTE - 1 // table end index 3399999: str \phys, [\tbl, \start, lsl #3] // store the entry 340 add \start, \start, #1 // next entry 341 add \phys, \phys, #BLOCK_SIZE // next block 342 cmp \start, \end 343 b.ls 9999b 344 .endm 345 346/* 347 * Setup the initial page tables. We only setup the barest amount which is 348 * required to get the kernel running. The following sections are required: 349 * - identity mapping to enable the MMU (low address, TTBR0) 350 * - first few MB of the kernel linear mapping to jump to once the MMU has 351 * been enabled, including the FDT blob (TTBR1) 352 * - pgd entry for fixed mappings (TTBR1) 353 */ 354__create_page_tables: 355 adrp x25, idmap_pg_dir 356 adrp x26, swapper_pg_dir 357 mov x27, lr 358 359 /* 360 * Invalidate the idmap and swapper page tables to avoid potential 361 * dirty cache lines being evicted. 362 */ 363 mov x0, x25 364 add x1, x26, #SWAPPER_DIR_SIZE 365 bl __inval_cache_range 366 367 /* 368 * Clear the idmap and swapper page tables. 369 */ 370 mov x0, x25 371 add x6, x26, #SWAPPER_DIR_SIZE 3721: stp xzr, xzr, [x0], #16 373 stp xzr, xzr, [x0], #16 374 stp xzr, xzr, [x0], #16 375 stp xzr, xzr, [x0], #16 376 cmp x0, x6 377 b.lo 1b 378 379 ldr x7, =MM_MMUFLAGS 380 381 /* 382 * Create the identity mapping. 383 */ 384 mov x0, x25 // idmap_pg_dir 385 adrp x3, KERNEL_START // __pa(KERNEL_START) 386 387#ifndef CONFIG_ARM64_VA_BITS_48 388#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 389#define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) 390 391 /* 392 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be 393 * created that covers system RAM if that is located sufficiently high 394 * in the physical address space. So for the ID map, use an extended 395 * virtual range in that case, by configuring an additional translation 396 * level. 397 * First, we have to verify our assumption that the current value of 398 * VA_BITS was chosen such that all translation levels are fully 399 * utilised, and that lowering T0SZ will always result in an additional 400 * translation level to be configured. 401 */ 402#if VA_BITS != EXTRA_SHIFT 403#error "Mismatch between VA_BITS and page size/number of translation levels" 404#endif 405 406 /* 407 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 408 * entire kernel image can be ID mapped. As T0SZ == (64 - #bits used), 409 * this number conveniently equals the number of leading zeroes in 410 * the physical address of KERNEL_END. 411 */ 412 adrp x5, KERNEL_END 413 clz x5, x5 414 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 415 b.ge 1f // .. then skip additional level 416 417 adr_l x6, idmap_t0sz 418 str x5, [x6] 419 dmb sy 420 dc ivac, x6 // Invalidate potentially stale cache line 421 422 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 4231: 424#endif 425 426 create_pgd_entry x0, x3, x5, x6 427 mov x5, x3 // __pa(KERNEL_START) 428 adr_l x6, KERNEL_END // __pa(KERNEL_END) 429 create_block_map x0, x7, x3, x5, x6 430 431 /* 432 * Map the kernel image (starting with PHYS_OFFSET). 433 */ 434 mov x0, x26 // swapper_pg_dir 435 mov x5, #PAGE_OFFSET 436 create_pgd_entry x0, x5, x3, x6 437 ldr x6, =KERNEL_END // __va(KERNEL_END) 438 mov x3, x24 // phys offset 439 create_block_map x0, x7, x3, x5, x6 440 441 /* 442 * Map the FDT blob (maximum 2MB; must be within 512MB of 443 * PHYS_OFFSET). 444 */ 445 mov x3, x21 // FDT phys address 446 and x3, x3, #~((1 << 21) - 1) // 2MB aligned 447 mov x6, #PAGE_OFFSET 448 sub x5, x3, x24 // subtract PHYS_OFFSET 449 tst x5, #~((1 << 29) - 1) // within 512MB? 450 csel x21, xzr, x21, ne // zero the FDT pointer 451 b.ne 1f 452 add x5, x5, x6 // __va(FDT blob) 453 add x6, x5, #1 << 21 // 2MB for the FDT blob 454 sub x6, x6, #1 // inclusive range 455 create_block_map x0, x7, x3, x5, x6 4561: 457 /* 458 * Since the page tables have been populated with non-cacheable 459 * accesses (MMU disabled), invalidate the idmap and swapper page 460 * tables again to remove any speculatively loaded cache lines. 461 */ 462 mov x0, x25 463 add x1, x26, #SWAPPER_DIR_SIZE 464 dmb sy 465 bl __inval_cache_range 466 467 mov lr, x27 468 ret 469ENDPROC(__create_page_tables) 470 .ltorg 471 472/* 473 * The following fragment of code is executed with the MMU enabled. 474 */ 475 .set initial_sp, init_thread_union + THREAD_START_SP 476__mmap_switched: 477 adr_l x6, __bss_start 478 adr_l x7, __bss_stop 479 4801: cmp x6, x7 481 b.hs 2f 482 str xzr, [x6], #8 // Clear BSS 483 b 1b 4842: 485 adr_l sp, initial_sp, x4 486 str_l x21, __fdt_pointer, x5 // Save FDT pointer 487 str_l x24, memstart_addr, x6 // Save PHYS_OFFSET 488 mov x29, #0 489 b start_kernel 490ENDPROC(__mmap_switched) 491 492/* 493 * end early head section, begin head code that is also used for 494 * hotplug and needs to have the same protections as the text region 495 */ 496 .section ".text","ax" 497/* 498 * If we're fortunate enough to boot at EL2, ensure that the world is 499 * sane before dropping to EL1. 500 * 501 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if 502 * booted in EL1 or EL2 respectively. 503 */ 504ENTRY(el2_setup) 505 mrs x0, CurrentEL 506 cmp x0, #CurrentEL_EL2 507 b.ne 1f 508 mrs x0, sctlr_el2 509CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 510CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 511 msr sctlr_el2, x0 512 b 2f 5131: mrs x0, sctlr_el1 514CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 515CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 516 msr sctlr_el1, x0 517 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 518 isb 519 ret 520 521 /* Hyp configuration. */ 5222: mov x0, #(1 << 31) // 64-bit EL1 523 msr hcr_el2, x0 524 525 /* Generic timers. */ 526 mrs x0, cnthctl_el2 527 orr x0, x0, #3 // Enable EL1 physical timers 528 msr cnthctl_el2, x0 529 msr cntvoff_el2, xzr // Clear virtual offset 530 531#ifdef CONFIG_ARM_GIC_V3 532 /* GICv3 system register access */ 533 mrs x0, id_aa64pfr0_el1 534 ubfx x0, x0, #24, #4 535 cmp x0, #1 536 b.ne 3f 537 538 mrs_s x0, ICC_SRE_EL2 539 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 540 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 541 msr_s ICC_SRE_EL2, x0 542 isb // Make sure SRE is now set 543 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 544 5453: 546#endif 547 548 /* Populate ID registers. */ 549 mrs x0, midr_el1 550 mrs x1, mpidr_el1 551 msr vpidr_el2, x0 552 msr vmpidr_el2, x1 553 554 /* sctlr_el1 */ 555 mov x0, #0x0800 // Set/clear RES{1,0} bits 556CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems 557CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems 558 msr sctlr_el1, x0 559 560 /* Coprocessor traps. */ 561 mov x0, #0x33ff 562 msr cptr_el2, x0 // Disable copro. traps to EL2 563 564#ifdef CONFIG_COMPAT 565 msr hstr_el2, xzr // Disable CP15 traps to EL2 566#endif 567 568 /* Stage-2 translation */ 569 msr vttbr_el2, xzr 570 571 /* Hypervisor stub */ 572 adrp x0, __hyp_stub_vectors 573 add x0, x0, #:lo12:__hyp_stub_vectors 574 msr vbar_el2, x0 575 576 /* spsr */ 577 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 578 PSR_MODE_EL1h) 579 msr spsr_el2, x0 580 msr elr_el2, lr 581 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 582 eret 583ENDPROC(el2_setup) 584 585/* 586 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 587 * in x20. See arch/arm64/include/asm/virt.h for more info. 588 */ 589ENTRY(set_cpu_boot_mode_flag) 590 adr_l x1, __boot_cpu_mode 591 cmp w20, #BOOT_CPU_MODE_EL2 592 b.ne 1f 593 add x1, x1, #4 5941: str w20, [x1] // This CPU has booted in EL1 595 dmb sy 596 dc ivac, x1 // Invalidate potentially stale cache line 597 ret 598ENDPROC(set_cpu_boot_mode_flag) 599 600/* 601 * We need to find out the CPU boot mode long after boot, so we need to 602 * store it in a writable variable. 603 * 604 * This is not in .bss, because we set it sufficiently early that the boot-time 605 * zeroing of .bss would clobber it. 606 */ 607 .pushsection .data..cacheline_aligned 608 .align L1_CACHE_SHIFT 609ENTRY(__boot_cpu_mode) 610 .long BOOT_CPU_MODE_EL2 611 .long BOOT_CPU_MODE_EL1 612 .popsection 613 614#ifdef CONFIG_SMP 615 /* 616 * This provides a "holding pen" for platforms to hold all secondary 617 * cores are held until we're ready for them to initialise. 618 */ 619ENTRY(secondary_holding_pen) 620 bl el2_setup // Drop to EL1, w20=cpu_boot_mode 621 bl set_cpu_boot_mode_flag 622 mrs x0, mpidr_el1 623 ldr x1, =MPIDR_HWID_BITMASK 624 and x0, x0, x1 625 adr_l x3, secondary_holding_pen_release 626pen: ldr x4, [x3] 627 cmp x4, x0 628 b.eq secondary_startup 629 wfe 630 b pen 631ENDPROC(secondary_holding_pen) 632 633 /* 634 * Secondary entry point that jumps straight into the kernel. Only to 635 * be used where CPUs are brought online dynamically by the kernel. 636 */ 637ENTRY(secondary_entry) 638 bl el2_setup // Drop to EL1 639 bl set_cpu_boot_mode_flag 640 b secondary_startup 641ENDPROC(secondary_entry) 642 643ENTRY(secondary_startup) 644 /* 645 * Common entry point for secondary CPUs. 646 */ 647 adrp x25, idmap_pg_dir 648 adrp x26, swapper_pg_dir 649 bl __cpu_setup // initialise processor 650 651 ldr x21, =secondary_data 652 ldr x27, =__secondary_switched // address to jump to after enabling the MMU 653 b __enable_mmu 654ENDPROC(secondary_startup) 655 656ENTRY(__secondary_switched) 657 ldr x0, [x21] // get secondary_data.stack 658 mov sp, x0 659 mov x29, #0 660 b secondary_start_kernel 661ENDPROC(__secondary_switched) 662#endif /* CONFIG_SMP */ 663 664/* 665 * Enable the MMU. 666 * 667 * x0 = SCTLR_EL1 value for turning on the MMU. 668 * x27 = *virtual* address to jump to upon completion 669 * 670 * other registers depend on the function called upon completion 671 */ 672__enable_mmu: 673 ldr x5, =vectors 674 msr vbar_el1, x5 675 msr ttbr0_el1, x25 // load TTBR0 676 msr ttbr1_el1, x26 // load TTBR1 677 isb 678 msr sctlr_el1, x0 679 isb 680 br x27 681ENDPROC(__enable_mmu) 682