1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <linux/irqchip/arm-gic-v3.h> 26 27#include <asm/assembler.h> 28#include <asm/boot.h> 29#include <asm/ptrace.h> 30#include <asm/asm-offsets.h> 31#include <asm/cache.h> 32#include <asm/cputype.h> 33#include <asm/elf.h> 34#include <asm/image.h> 35#include <asm/kernel-pgtable.h> 36#include <asm/kvm_arm.h> 37#include <asm/memory.h> 38#include <asm/pgtable-hwdef.h> 39#include <asm/pgtable.h> 40#include <asm/page.h> 41#include <asm/smp.h> 42#include <asm/sysreg.h> 43#include <asm/thread_info.h> 44#include <asm/virt.h> 45 46#include "efi-header.S" 47 48#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) 49 50#if (TEXT_OFFSET & 0xfff) != 0 51#error TEXT_OFFSET must be at least 4KB aligned 52#elif (PAGE_OFFSET & 0x1fffff) != 0 53#error PAGE_OFFSET must be at least 2MB aligned 54#elif TEXT_OFFSET > 0x1fffff 55#error TEXT_OFFSET must be less than 2MB 56#endif 57 58/* 59 * Kernel startup entry point. 60 * --------------------------- 61 * 62 * The requirements are: 63 * MMU = off, D-cache = off, I-cache = on or off, 64 * x0 = physical address to the FDT blob. 65 * 66 * This code is mostly position independent so you call this at 67 * __pa(PAGE_OFFSET + TEXT_OFFSET). 68 * 69 * Note that the callee-saved registers are used for storing variables 70 * that are useful before the MMU is enabled. The allocations are described 71 * in the entry routines. 72 */ 73 __HEAD 74_head: 75 /* 76 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 77 */ 78#ifdef CONFIG_EFI 79 /* 80 * This add instruction has no meaningful effect except that 81 * its opcode forms the magic "MZ" signature required by UEFI. 82 */ 83 add x13, x18, #0x16 84 b stext 85#else 86 b stext // branch to kernel start, magic 87 .long 0 // reserved 88#endif 89 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian 90 le64sym _kernel_size_le // Effective size of kernel image, little-endian 91 le64sym _kernel_flags_le // Informative flags, little-endian 92 .quad 0 // reserved 93 .quad 0 // reserved 94 .quad 0 // reserved 95 .ascii ARM64_IMAGE_MAGIC // Magic number 96#ifdef CONFIG_EFI 97 .long pe_header - _head // Offset to the PE header. 98 99pe_header: 100 __EFI_PE_HEADER 101#else 102 .long 0 // reserved 103#endif 104 105 __INIT 106 107 /* 108 * The following callee saved general purpose registers are used on the 109 * primary lowlevel boot path: 110 * 111 * Register Scope Purpose 112 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0 113 * x23 stext() .. start_kernel() physical misalignment/KASLR offset 114 * x28 __create_page_tables() callee preserved temp register 115 * x19/x20 __primary_switch() callee preserved temp registers 116 */ 117ENTRY(stext) 118 bl preserve_boot_args 119 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 120 adrp x23, __PHYS_OFFSET 121 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 122 bl set_cpu_boot_mode_flag 123 bl __create_page_tables 124 /* 125 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 126 * details. 127 * On return, the CPU will be ready for the MMU to be turned on and 128 * the TCR will have been set. 129 */ 130 bl __cpu_setup // initialise processor 131 b __primary_switch 132ENDPROC(stext) 133 134/* 135 * Preserve the arguments passed by the bootloader in x0 .. x3 136 */ 137preserve_boot_args: 138 mov x21, x0 // x21=FDT 139 140 adr_l x0, boot_args // record the contents of 141 stp x21, x1, [x0] // x0 .. x3 at kernel entry 142 stp x2, x3, [x0, #16] 143 144 dmb sy // needed before dc ivac with 145 // MMU off 146 147 mov x1, #0x20 // 4 x 8 bytes 148 b __inval_dcache_area // tail call 149ENDPROC(preserve_boot_args) 150 151/* 152 * Macro to create a table entry to the next page. 153 * 154 * tbl: page table address 155 * virt: virtual address 156 * shift: #imm page table shift 157 * ptrs: #imm pointers per table page 158 * 159 * Preserves: virt 160 * Corrupts: ptrs, tmp1, tmp2 161 * Returns: tbl -> next level table page address 162 */ 163 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 164 add \tmp1, \tbl, #PAGE_SIZE 165 phys_to_pte \tmp2, \tmp1 166 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 167 lsr \tmp1, \virt, #\shift 168 sub \ptrs, \ptrs, #1 169 and \tmp1, \tmp1, \ptrs // table index 170 str \tmp2, [\tbl, \tmp1, lsl #3] 171 add \tbl, \tbl, #PAGE_SIZE // next level table page 172 .endm 173 174/* 175 * Macro to populate page table entries, these entries can be pointers to the next level 176 * or last level entries pointing to physical memory. 177 * 178 * tbl: page table address 179 * rtbl: pointer to page table or physical memory 180 * index: start index to write 181 * eindex: end index to write - [index, eindex] written to 182 * flags: flags for pagetable entry to or in 183 * inc: increment to rtbl between each entry 184 * tmp1: temporary variable 185 * 186 * Preserves: tbl, eindex, flags, inc 187 * Corrupts: index, tmp1 188 * Returns: rtbl 189 */ 190 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 191.Lpe\@: phys_to_pte \tmp1, \rtbl 192 orr \tmp1, \tmp1, \flags // tmp1 = table entry 193 str \tmp1, [\tbl, \index, lsl #3] 194 add \rtbl, \rtbl, \inc // rtbl = pa next level 195 add \index, \index, #1 196 cmp \index, \eindex 197 b.ls .Lpe\@ 198 .endm 199 200/* 201 * Compute indices of table entries from virtual address range. If multiple entries 202 * were needed in the previous page table level then the next page table level is assumed 203 * to be composed of multiple pages. (This effectively scales the end index). 204 * 205 * vstart: virtual address of start of range 206 * vend: virtual address of end of range 207 * shift: shift used to transform virtual address into index 208 * ptrs: number of entries in page table 209 * istart: index in table corresponding to vstart 210 * iend: index in table corresponding to vend 211 * count: On entry: how many extra entries were required in previous level, scales 212 * our end index. 213 * On exit: returns how many extra entries required for next page table level 214 * 215 * Preserves: vstart, vend, shift, ptrs 216 * Returns: istart, iend, count 217 */ 218 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count 219 lsr \iend, \vend, \shift 220 mov \istart, \ptrs 221 sub \istart, \istart, #1 222 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) 223 mov \istart, \ptrs 224 mul \istart, \istart, \count 225 add \iend, \iend, \istart // iend += (count - 1) * ptrs 226 // our entries span multiple tables 227 228 lsr \istart, \vstart, \shift 229 mov \count, \ptrs 230 sub \count, \count, #1 231 and \istart, \istart, \count 232 233 sub \count, \iend, \istart 234 .endm 235 236/* 237 * Map memory for specified virtual address range. Each level of page table needed supports 238 * multiple entries. If a level requires n entries the next page table level is assumed to be 239 * formed from n pages. 240 * 241 * tbl: location of page table 242 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 243 * vstart: start address to map 244 * vend: end address to map - we map [vstart, vend] 245 * flags: flags to use to map last level entries 246 * phys: physical address corresponding to vstart - physical memory is contiguous 247 * pgds: the number of pgd entries 248 * 249 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 250 * Preserves: vstart, vend, flags 251 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv 252 */ 253 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv 254 add \rtbl, \tbl, #PAGE_SIZE 255 mov \sv, \rtbl 256 mov \count, #0 257 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count 258 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 259 mov \tbl, \sv 260 mov \sv, \rtbl 261 262#if SWAPPER_PGTABLE_LEVELS > 3 263 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count 264 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 265 mov \tbl, \sv 266 mov \sv, \rtbl 267#endif 268 269#if SWAPPER_PGTABLE_LEVELS > 2 270 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count 271 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 272 mov \tbl, \sv 273#endif 274 275 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count 276 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 277 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 278 .endm 279 280/* 281 * Setup the initial page tables. We only setup the barest amount which is 282 * required to get the kernel running. The following sections are required: 283 * - identity mapping to enable the MMU (low address, TTBR0) 284 * - first few MB of the kernel linear mapping to jump to once the MMU has 285 * been enabled 286 */ 287__create_page_tables: 288 mov x28, lr 289 290 /* 291 * Invalidate the init page tables to avoid potential dirty cache lines 292 * being evicted. Other page tables are allocated in rodata as part of 293 * the kernel image, and thus are clean to the PoC per the boot 294 * protocol. 295 */ 296 adrp x0, init_pg_dir 297 adrp x1, init_pg_end 298 sub x1, x1, x0 299 bl __inval_dcache_area 300 301 /* 302 * Clear the init page tables. 303 */ 304 adrp x0, init_pg_dir 305 adrp x1, init_pg_end 306 sub x1, x1, x0 3071: stp xzr, xzr, [x0], #16 308 stp xzr, xzr, [x0], #16 309 stp xzr, xzr, [x0], #16 310 stp xzr, xzr, [x0], #16 311 subs x1, x1, #64 312 b.ne 1b 313 314 mov x7, SWAPPER_MM_MMUFLAGS 315 316 /* 317 * Create the identity mapping. 318 */ 319 adrp x0, idmap_pg_dir 320 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 321 322#ifdef CONFIG_ARM64_USER_VA_BITS_52 323 mrs_s x6, SYS_ID_AA64MMFR2_EL1 324 and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 325 mov x5, #52 326 cbnz x6, 1f 327#endif 328 mov x5, #VA_BITS 3291: 330 adr_l x6, vabits_user 331 str x5, [x6] 332 dmb sy 333 dc ivac, x6 // Invalidate potentially stale cache line 334 335 /* 336 * VA_BITS may be too small to allow for an ID mapping to be created 337 * that covers system RAM if that is located sufficiently high in the 338 * physical address space. So for the ID map, use an extended virtual 339 * range in that case, and configure an additional translation level 340 * if needed. 341 * 342 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 343 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 344 * this number conveniently equals the number of leading zeroes in 345 * the physical address of __idmap_text_end. 346 */ 347 adrp x5, __idmap_text_end 348 clz x5, x5 349 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 350 b.ge 1f // .. then skip VA range extension 351 352 adr_l x6, idmap_t0sz 353 str x5, [x6] 354 dmb sy 355 dc ivac, x6 // Invalidate potentially stale cache line 356 357#if (VA_BITS < 48) 358#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 359#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) 360 361 /* 362 * If VA_BITS < 48, we have to configure an additional table level. 363 * First, we have to verify our assumption that the current value of 364 * VA_BITS was chosen such that all translation levels are fully 365 * utilised, and that lowering T0SZ will always result in an additional 366 * translation level to be configured. 367 */ 368#if VA_BITS != EXTRA_SHIFT 369#error "Mismatch between VA_BITS and page size/number of translation levels" 370#endif 371 372 mov x4, EXTRA_PTRS 373 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 374#else 375 /* 376 * If VA_BITS == 48, we don't have to configure an additional 377 * translation level, but the top-level table has more entries. 378 */ 379 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) 380 str_l x4, idmap_ptrs_per_pgd, x5 381#endif 3821: 383 ldr_l x4, idmap_ptrs_per_pgd 384 mov x5, x3 // __pa(__idmap_text_start) 385 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 386 387 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 388 389 /* 390 * Map the kernel image (starting with PHYS_OFFSET). 391 */ 392 adrp x0, init_pg_dir 393 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) 394 add x5, x5, x23 // add KASLR displacement 395 mov x4, PTRS_PER_PGD 396 adrp x6, _end // runtime __pa(_end) 397 adrp x3, _text // runtime __pa(_text) 398 sub x6, x6, x3 // _end - _text 399 add x6, x6, x5 // runtime __va(_end) 400 401 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14 402 403 /* 404 * Since the page tables have been populated with non-cacheable 405 * accesses (MMU disabled), invalidate the idmap and swapper page 406 * tables again to remove any speculatively loaded cache lines. 407 */ 408 adrp x0, idmap_pg_dir 409 adrp x1, init_pg_end 410 sub x1, x1, x0 411 dmb sy 412 bl __inval_dcache_area 413 414 ret x28 415ENDPROC(__create_page_tables) 416 .ltorg 417 418/* 419 * The following fragment of code is executed with the MMU enabled. 420 * 421 * x0 = __PHYS_OFFSET 422 */ 423__primary_switched: 424 adrp x4, init_thread_union 425 add sp, x4, #THREAD_SIZE 426 adr_l x5, init_task 427 msr sp_el0, x5 // Save thread_info 428 429 adr_l x8, vectors // load VBAR_EL1 with virtual 430 msr vbar_el1, x8 // vector table address 431 isb 432 433 stp xzr, x30, [sp, #-16]! 434 mov x29, sp 435 436 str_l x21, __fdt_pointer, x5 // Save FDT pointer 437 438 ldr_l x4, kimage_vaddr // Save the offset between 439 sub x4, x4, x0 // the kernel virtual and 440 str_l x4, kimage_voffset, x5 // physical mappings 441 442 // Clear BSS 443 adr_l x0, __bss_start 444 mov x1, xzr 445 adr_l x2, __bss_stop 446 sub x2, x2, x0 447 bl __pi_memset 448 dsb ishst // Make zero page visible to PTW 449 450#ifdef CONFIG_KASAN 451 bl kasan_early_init 452#endif 453#ifdef CONFIG_RANDOMIZE_BASE 454 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 455 b.ne 0f 456 mov x0, x21 // pass FDT address in x0 457 bl kaslr_early_init // parse FDT for KASLR options 458 cbz x0, 0f // KASLR disabled? just proceed 459 orr x23, x23, x0 // record KASLR offset 460 ldp x29, x30, [sp], #16 // we must enable KASLR, return 461 ret // to __primary_switch() 4620: 463#endif 464 add sp, sp, #16 465 mov x29, #0 466 mov x30, #0 467 b start_kernel 468ENDPROC(__primary_switched) 469 470/* 471 * end early head section, begin head code that is also used for 472 * hotplug and needs to have the same protections as the text region 473 */ 474 .section ".idmap.text","awx" 475 476ENTRY(kimage_vaddr) 477 .quad _text - TEXT_OFFSET 478 479/* 480 * If we're fortunate enough to boot at EL2, ensure that the world is 481 * sane before dropping to EL1. 482 * 483 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 484 * booted in EL1 or EL2 respectively. 485 */ 486ENTRY(el2_setup) 487 msr SPsel, #1 // We want to use SP_EL{1,2} 488 mrs x0, CurrentEL 489 cmp x0, #CurrentEL_EL2 490 b.eq 1f 491 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1) 492 msr sctlr_el1, x0 493 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 494 isb 495 ret 496 4971: mov_q x0, (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 498 msr sctlr_el2, x0 499 500#ifdef CONFIG_ARM64_VHE 501 /* 502 * Check for VHE being present. For the rest of the EL2 setup, 503 * x2 being non-zero indicates that we do have VHE, and that the 504 * kernel is intended to run at EL2. 505 */ 506 mrs x2, id_aa64mmfr1_el1 507 ubfx x2, x2, #8, #4 508#else 509 mov x2, xzr 510#endif 511 512 /* Hyp configuration. */ 513 mov_q x0, HCR_HOST_NVHE_FLAGS 514 cbz x2, set_hcr 515 mov_q x0, HCR_HOST_VHE_FLAGS 516set_hcr: 517 msr hcr_el2, x0 518 isb 519 520 /* 521 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 522 * This is not necessary for VHE, since the host kernel runs in EL2, 523 * and EL0 accesses are configured in the later stage of boot process. 524 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 525 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 526 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 527 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 528 * EL2. 529 */ 530 cbnz x2, 1f 531 mrs x0, cnthctl_el2 532 orr x0, x0, #3 // Enable EL1 physical timers 533 msr cnthctl_el2, x0 5341: 535 msr cntvoff_el2, xzr // Clear virtual offset 536 537#ifdef CONFIG_ARM_GIC_V3 538 /* GICv3 system register access */ 539 mrs x0, id_aa64pfr0_el1 540 ubfx x0, x0, #24, #4 541 cmp x0, #1 542 b.ne 3f 543 544 mrs_s x0, SYS_ICC_SRE_EL2 545 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 546 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 547 msr_s SYS_ICC_SRE_EL2, x0 548 isb // Make sure SRE is now set 549 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 550 tbz x0, #0, 3f // and check that it sticks 551 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 552 5533: 554#endif 555 556 /* Populate ID registers. */ 557 mrs x0, midr_el1 558 mrs x1, mpidr_el1 559 msr vpidr_el2, x0 560 msr vmpidr_el2, x1 561 562#ifdef CONFIG_COMPAT 563 msr hstr_el2, xzr // Disable CP15 traps to EL2 564#endif 565 566 /* EL2 debug */ 567 mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer 568 sbfx x0, x1, #8, #4 569 cmp x0, #1 570 b.lt 4f // Skip if no PMU present 571 mrs x0, pmcr_el0 // Disable debug access traps 572 ubfx x0, x0, #11, #5 // to EL2 and allow access to 5734: 574 csel x3, xzr, x0, lt // all PMU counters from EL1 575 576 /* Statistical profiling */ 577 ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer 578 cbz x0, 7f // Skip if SPE not present 579 cbnz x2, 6f // VHE? 580 mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2, 581 and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT) 582 cbnz x4, 5f // then permit sampling of physical 583 mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ 584 1 << SYS_PMSCR_EL2_PA_SHIFT) 585 msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter 5865: 587 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 588 orr x3, x3, x1 // If we don't have VHE, then 589 b 7f // use EL1&0 translation. 5906: // For VHE, use EL2 translation 591 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 5927: 593 msr mdcr_el2, x3 // Configure debug traps 594 595 /* LORegions */ 596 mrs x1, id_aa64mmfr1_el1 597 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4 598 cbz x0, 1f 599 msr_s SYS_LORC_EL1, xzr 6001: 601 602 /* Stage-2 translation */ 603 msr vttbr_el2, xzr 604 605 cbz x2, install_el2_stub 606 607 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 608 isb 609 ret 610 611install_el2_stub: 612 /* 613 * When VHE is not in use, early init of EL2 and EL1 needs to be 614 * done here. 615 * When VHE _is_ in use, EL1 will not be used in the host and 616 * requires no configuration, and all non-hyp-specific EL2 setup 617 * will be done via the _EL1 system register aliases in __cpu_setup. 618 */ 619 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1) 620 msr sctlr_el1, x0 621 622 /* Coprocessor traps. */ 623 mov x0, #0x33ff 624 msr cptr_el2, x0 // Disable copro. traps to EL2 625 626 /* SVE register access */ 627 mrs x1, id_aa64pfr0_el1 628 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4 629 cbz x1, 7f 630 631 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps 632 msr cptr_el2, x0 // Disable copro. traps to EL2 633 isb 634 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 635 msr_s SYS_ZCR_EL2, x1 // length for EL1. 636 637 /* Hypervisor stub */ 6387: adr_l x0, __hyp_stub_vectors 639 msr vbar_el2, x0 640 641 /* spsr */ 642 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 643 PSR_MODE_EL1h) 644 msr spsr_el2, x0 645 msr elr_el2, lr 646 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 647 eret 648ENDPROC(el2_setup) 649 650/* 651 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 652 * in w0. See arch/arm64/include/asm/virt.h for more info. 653 */ 654set_cpu_boot_mode_flag: 655 adr_l x1, __boot_cpu_mode 656 cmp w0, #BOOT_CPU_MODE_EL2 657 b.ne 1f 658 add x1, x1, #4 6591: str w0, [x1] // This CPU has booted in EL1 660 dmb sy 661 dc ivac, x1 // Invalidate potentially stale cache line 662 ret 663ENDPROC(set_cpu_boot_mode_flag) 664 665/* 666 * These values are written with the MMU off, but read with the MMU on. 667 * Writers will invalidate the corresponding address, discarding up to a 668 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 669 * sufficient alignment that the CWG doesn't overlap another section. 670 */ 671 .pushsection ".mmuoff.data.write", "aw" 672/* 673 * We need to find out the CPU boot mode long after boot, so we need to 674 * store it in a writable variable. 675 * 676 * This is not in .bss, because we set it sufficiently early that the boot-time 677 * zeroing of .bss would clobber it. 678 */ 679ENTRY(__boot_cpu_mode) 680 .long BOOT_CPU_MODE_EL2 681 .long BOOT_CPU_MODE_EL1 682/* 683 * The booting CPU updates the failed status @__early_cpu_boot_status, 684 * with MMU turned off. 685 */ 686ENTRY(__early_cpu_boot_status) 687 .long 0 688 689 .popsection 690 691 /* 692 * This provides a "holding pen" for platforms to hold all secondary 693 * cores are held until we're ready for them to initialise. 694 */ 695ENTRY(secondary_holding_pen) 696 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 697 bl set_cpu_boot_mode_flag 698 mrs x0, mpidr_el1 699 mov_q x1, MPIDR_HWID_BITMASK 700 and x0, x0, x1 701 adr_l x3, secondary_holding_pen_release 702pen: ldr x4, [x3] 703 cmp x4, x0 704 b.eq secondary_startup 705 wfe 706 b pen 707ENDPROC(secondary_holding_pen) 708 709 /* 710 * Secondary entry point that jumps straight into the kernel. Only to 711 * be used where CPUs are brought online dynamically by the kernel. 712 */ 713ENTRY(secondary_entry) 714 bl el2_setup // Drop to EL1 715 bl set_cpu_boot_mode_flag 716 b secondary_startup 717ENDPROC(secondary_entry) 718 719secondary_startup: 720 /* 721 * Common entry point for secondary CPUs. 722 */ 723 bl __cpu_secondary_check52bitva 724 bl __cpu_setup // initialise processor 725 adrp x1, swapper_pg_dir 726 bl __enable_mmu 727 ldr x8, =__secondary_switched 728 br x8 729ENDPROC(secondary_startup) 730 731__secondary_switched: 732 adr_l x5, vectors 733 msr vbar_el1, x5 734 isb 735 736 adr_l x0, secondary_data 737 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 738 mov sp, x1 739 ldr x2, [x0, #CPU_BOOT_TASK] 740 msr sp_el0, x2 741 mov x29, #0 742 mov x30, #0 743 b secondary_start_kernel 744ENDPROC(__secondary_switched) 745 746/* 747 * The booting CPU updates the failed status @__early_cpu_boot_status, 748 * with MMU turned off. 749 * 750 * update_early_cpu_boot_status tmp, status 751 * - Corrupts tmp1, tmp2 752 * - Writes 'status' to __early_cpu_boot_status and makes sure 753 * it is committed to memory. 754 */ 755 756 .macro update_early_cpu_boot_status status, tmp1, tmp2 757 mov \tmp2, #\status 758 adr_l \tmp1, __early_cpu_boot_status 759 str \tmp2, [\tmp1] 760 dmb sy 761 dc ivac, \tmp1 // Invalidate potentially stale cache line 762 .endm 763 764/* 765 * Enable the MMU. 766 * 767 * x0 = SCTLR_EL1 value for turning on the MMU. 768 * x1 = TTBR1_EL1 value 769 * 770 * Returns to the caller via x30/lr. This requires the caller to be covered 771 * by the .idmap.text section. 772 * 773 * Checks if the selected granule size is supported by the CPU. 774 * If it isn't, park the CPU 775 */ 776ENTRY(__enable_mmu) 777 mrs x2, ID_AA64MMFR0_EL1 778 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 779 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED 780 b.ne __no_granule_support 781 update_early_cpu_boot_status 0, x2, x3 782 adrp x2, idmap_pg_dir 783 phys_to_ttbr x1, x1 784 phys_to_ttbr x2, x2 785 msr ttbr0_el1, x2 // load TTBR0 786 offset_ttbr1 x1 787 msr ttbr1_el1, x1 // load TTBR1 788 isb 789 msr sctlr_el1, x0 790 isb 791 /* 792 * Invalidate the local I-cache so that any instructions fetched 793 * speculatively from the PoC are discarded, since they may have 794 * been dynamically patched at the PoU. 795 */ 796 ic iallu 797 dsb nsh 798 isb 799 ret 800ENDPROC(__enable_mmu) 801 802ENTRY(__cpu_secondary_check52bitva) 803#ifdef CONFIG_ARM64_USER_VA_BITS_52 804 ldr_l x0, vabits_user 805 cmp x0, #52 806 b.ne 2f 807 808 mrs_s x0, SYS_ID_AA64MMFR2_EL1 809 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 810 cbnz x0, 2f 811 812 update_early_cpu_boot_status \ 813 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 8141: wfe 815 wfi 816 b 1b 817 818#endif 8192: ret 820ENDPROC(__cpu_secondary_check52bitva) 821 822__no_granule_support: 823 /* Indicate that this CPU can't boot and is stuck in the kernel */ 824 update_early_cpu_boot_status \ 825 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 8261: 827 wfe 828 wfi 829 b 1b 830ENDPROC(__no_granule_support) 831 832#ifdef CONFIG_RELOCATABLE 833__relocate_kernel: 834 /* 835 * Iterate over each entry in the relocation table, and apply the 836 * relocations in place. 837 */ 838 ldr w9, =__rela_offset // offset to reloc table 839 ldr w10, =__rela_size // size of reloc table 840 841 mov_q x11, KIMAGE_VADDR // default virtual offset 842 add x11, x11, x23 // actual virtual offset 843 add x9, x9, x11 // __va(.rela) 844 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 845 8460: cmp x9, x10 847 b.hs 1f 848 ldp x11, x12, [x9], #24 849 ldr x13, [x9, #-8] 850 cmp w12, #R_AARCH64_RELATIVE 851 b.ne 0b 852 add x13, x13, x23 // relocate 853 str x13, [x11, x23] 854 b 0b 8551: ret 856ENDPROC(__relocate_kernel) 857#endif 858 859__primary_switch: 860#ifdef CONFIG_RANDOMIZE_BASE 861 mov x19, x0 // preserve new SCTLR_EL1 value 862 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 863#endif 864 865 adrp x1, init_pg_dir 866 bl __enable_mmu 867#ifdef CONFIG_RELOCATABLE 868 bl __relocate_kernel 869#ifdef CONFIG_RANDOMIZE_BASE 870 ldr x8, =__primary_switched 871 adrp x0, __PHYS_OFFSET 872 blr x8 873 874 /* 875 * If we return here, we have a KASLR displacement in x23 which we need 876 * to take into account by discarding the current kernel mapping and 877 * creating a new one. 878 */ 879 pre_disable_mmu_workaround 880 msr sctlr_el1, x20 // disable the MMU 881 isb 882 bl __create_page_tables // recreate kernel mapping 883 884 tlbi vmalle1 // Remove any stale TLB entries 885 dsb nsh 886 887 msr sctlr_el1, x19 // re-enable the MMU 888 isb 889 ic iallu // flush instructions fetched 890 dsb nsh // via old mapping 891 isb 892 893 bl __relocate_kernel 894#endif 895#endif 896 ldr x8, =__primary_switched 897 adrp x0, __PHYS_OFFSET 898 br x8 899ENDPROC(__primary_switch) 900