1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <linux/irqchip/arm-gic-v3.h> 26 27#include <asm/assembler.h> 28#include <asm/boot.h> 29#include <asm/ptrace.h> 30#include <asm/asm-offsets.h> 31#include <asm/cache.h> 32#include <asm/cputype.h> 33#include <asm/elf.h> 34#include <asm/kernel-pgtable.h> 35#include <asm/kvm_arm.h> 36#include <asm/memory.h> 37#include <asm/pgtable-hwdef.h> 38#include <asm/pgtable.h> 39#include <asm/page.h> 40#include <asm/smp.h> 41#include <asm/sysreg.h> 42#include <asm/thread_info.h> 43#include <asm/virt.h> 44 45#include "efi-header.S" 46 47#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) 48 49#if (TEXT_OFFSET & 0xfff) != 0 50#error TEXT_OFFSET must be at least 4KB aligned 51#elif (PAGE_OFFSET & 0x1fffff) != 0 52#error PAGE_OFFSET must be at least 2MB aligned 53#elif TEXT_OFFSET > 0x1fffff 54#error TEXT_OFFSET must be less than 2MB 55#endif 56 57/* 58 * Kernel startup entry point. 59 * --------------------------- 60 * 61 * The requirements are: 62 * MMU = off, D-cache = off, I-cache = on or off, 63 * x0 = physical address to the FDT blob. 64 * 65 * This code is mostly position independent so you call this at 66 * __pa(PAGE_OFFSET + TEXT_OFFSET). 67 * 68 * Note that the callee-saved registers are used for storing variables 69 * that are useful before the MMU is enabled. The allocations are described 70 * in the entry routines. 71 */ 72 __HEAD 73_head: 74 /* 75 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 76 */ 77#ifdef CONFIG_EFI 78 /* 79 * This add instruction has no meaningful effect except that 80 * its opcode forms the magic "MZ" signature required by UEFI. 81 */ 82 add x13, x18, #0x16 83 b stext 84#else 85 b stext // branch to kernel start, magic 86 .long 0 // reserved 87#endif 88 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian 89 le64sym _kernel_size_le // Effective size of kernel image, little-endian 90 le64sym _kernel_flags_le // Informative flags, little-endian 91 .quad 0 // reserved 92 .quad 0 // reserved 93 .quad 0 // reserved 94 .ascii "ARM\x64" // Magic number 95#ifdef CONFIG_EFI 96 .long pe_header - _head // Offset to the PE header. 97 98pe_header: 99 __EFI_PE_HEADER 100#else 101 .long 0 // reserved 102#endif 103 104 __INIT 105 106 /* 107 * The following callee saved general purpose registers are used on the 108 * primary lowlevel boot path: 109 * 110 * Register Scope Purpose 111 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0 112 * x23 stext() .. start_kernel() physical misalignment/KASLR offset 113 * x28 __create_page_tables() callee preserved temp register 114 * x19/x20 __primary_switch() callee preserved temp registers 115 */ 116ENTRY(stext) 117 bl preserve_boot_args 118 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 119 adrp x23, __PHYS_OFFSET 120 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 121 bl set_cpu_boot_mode_flag 122 bl __create_page_tables 123 /* 124 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 125 * details. 126 * On return, the CPU will be ready for the MMU to be turned on and 127 * the TCR will have been set. 128 */ 129 bl __cpu_setup // initialise processor 130 b __primary_switch 131ENDPROC(stext) 132 133/* 134 * Preserve the arguments passed by the bootloader in x0 .. x3 135 */ 136preserve_boot_args: 137 mov x21, x0 // x21=FDT 138 139 adr_l x0, boot_args // record the contents of 140 stp x21, x1, [x0] // x0 .. x3 at kernel entry 141 stp x2, x3, [x0, #16] 142 143 dmb sy // needed before dc ivac with 144 // MMU off 145 146 mov x1, #0x20 // 4 x 8 bytes 147 b __inval_dcache_area // tail call 148ENDPROC(preserve_boot_args) 149 150/* 151 * Macro to create a table entry to the next page. 152 * 153 * tbl: page table address 154 * virt: virtual address 155 * shift: #imm page table shift 156 * ptrs: #imm pointers per table page 157 * 158 * Preserves: virt 159 * Corrupts: ptrs, tmp1, tmp2 160 * Returns: tbl -> next level table page address 161 */ 162 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 163 add \tmp1, \tbl, #PAGE_SIZE 164 phys_to_pte \tmp2, \tmp1 165 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 166 lsr \tmp1, \virt, #\shift 167 sub \ptrs, \ptrs, #1 168 and \tmp1, \tmp1, \ptrs // table index 169 str \tmp2, [\tbl, \tmp1, lsl #3] 170 add \tbl, \tbl, #PAGE_SIZE // next level table page 171 .endm 172 173/* 174 * Macro to populate page table entries, these entries can be pointers to the next level 175 * or last level entries pointing to physical memory. 176 * 177 * tbl: page table address 178 * rtbl: pointer to page table or physical memory 179 * index: start index to write 180 * eindex: end index to write - [index, eindex] written to 181 * flags: flags for pagetable entry to or in 182 * inc: increment to rtbl between each entry 183 * tmp1: temporary variable 184 * 185 * Preserves: tbl, eindex, flags, inc 186 * Corrupts: index, tmp1 187 * Returns: rtbl 188 */ 189 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 190.Lpe\@: phys_to_pte \tmp1, \rtbl 191 orr \tmp1, \tmp1, \flags // tmp1 = table entry 192 str \tmp1, [\tbl, \index, lsl #3] 193 add \rtbl, \rtbl, \inc // rtbl = pa next level 194 add \index, \index, #1 195 cmp \index, \eindex 196 b.ls .Lpe\@ 197 .endm 198 199/* 200 * Compute indices of table entries from virtual address range. If multiple entries 201 * were needed in the previous page table level then the next page table level is assumed 202 * to be composed of multiple pages. (This effectively scales the end index). 203 * 204 * vstart: virtual address of start of range 205 * vend: virtual address of end of range 206 * shift: shift used to transform virtual address into index 207 * ptrs: number of entries in page table 208 * istart: index in table corresponding to vstart 209 * iend: index in table corresponding to vend 210 * count: On entry: how many extra entries were required in previous level, scales 211 * our end index. 212 * On exit: returns how many extra entries required for next page table level 213 * 214 * Preserves: vstart, vend, shift, ptrs 215 * Returns: istart, iend, count 216 */ 217 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count 218 lsr \iend, \vend, \shift 219 mov \istart, \ptrs 220 sub \istart, \istart, #1 221 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) 222 mov \istart, \ptrs 223 mul \istart, \istart, \count 224 add \iend, \iend, \istart // iend += (count - 1) * ptrs 225 // our entries span multiple tables 226 227 lsr \istart, \vstart, \shift 228 mov \count, \ptrs 229 sub \count, \count, #1 230 and \istart, \istart, \count 231 232 sub \count, \iend, \istart 233 .endm 234 235/* 236 * Map memory for specified virtual address range. Each level of page table needed supports 237 * multiple entries. If a level requires n entries the next page table level is assumed to be 238 * formed from n pages. 239 * 240 * tbl: location of page table 241 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 242 * vstart: start address to map 243 * vend: end address to map - we map [vstart, vend] 244 * flags: flags to use to map last level entries 245 * phys: physical address corresponding to vstart - physical memory is contiguous 246 * pgds: the number of pgd entries 247 * 248 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 249 * Preserves: vstart, vend, flags 250 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv 251 */ 252 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv 253 add \rtbl, \tbl, #PAGE_SIZE 254 mov \sv, \rtbl 255 mov \count, #0 256 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count 257 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 258 mov \tbl, \sv 259 mov \sv, \rtbl 260 261#if SWAPPER_PGTABLE_LEVELS > 3 262 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count 263 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 264 mov \tbl, \sv 265 mov \sv, \rtbl 266#endif 267 268#if SWAPPER_PGTABLE_LEVELS > 2 269 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count 270 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 271 mov \tbl, \sv 272#endif 273 274 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count 275 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 276 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 277 .endm 278 279/* 280 * Setup the initial page tables. We only setup the barest amount which is 281 * required to get the kernel running. The following sections are required: 282 * - identity mapping to enable the MMU (low address, TTBR0) 283 * - first few MB of the kernel linear mapping to jump to once the MMU has 284 * been enabled 285 */ 286__create_page_tables: 287 mov x28, lr 288 289 /* 290 * Invalidate the init page tables to avoid potential dirty cache lines 291 * being evicted. Other page tables are allocated in rodata as part of 292 * the kernel image, and thus are clean to the PoC per the boot 293 * protocol. 294 */ 295 adrp x0, init_pg_dir 296 adrp x1, init_pg_end 297 sub x1, x1, x0 298 bl __inval_dcache_area 299 300 /* 301 * Clear the init page tables. 302 */ 303 adrp x0, init_pg_dir 304 adrp x1, init_pg_end 305 sub x1, x1, x0 3061: stp xzr, xzr, [x0], #16 307 stp xzr, xzr, [x0], #16 308 stp xzr, xzr, [x0], #16 309 stp xzr, xzr, [x0], #16 310 subs x1, x1, #64 311 b.ne 1b 312 313 mov x7, SWAPPER_MM_MMUFLAGS 314 315 /* 316 * Create the identity mapping. 317 */ 318 adrp x0, idmap_pg_dir 319 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 320 321 /* 322 * VA_BITS may be too small to allow for an ID mapping to be created 323 * that covers system RAM if that is located sufficiently high in the 324 * physical address space. So for the ID map, use an extended virtual 325 * range in that case, and configure an additional translation level 326 * if needed. 327 * 328 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 329 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 330 * this number conveniently equals the number of leading zeroes in 331 * the physical address of __idmap_text_end. 332 */ 333 adrp x5, __idmap_text_end 334 clz x5, x5 335 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 336 b.ge 1f // .. then skip VA range extension 337 338 adr_l x6, idmap_t0sz 339 str x5, [x6] 340 dmb sy 341 dc ivac, x6 // Invalidate potentially stale cache line 342 343#if (VA_BITS < 48) 344#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 345#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) 346 347 /* 348 * If VA_BITS < 48, we have to configure an additional table level. 349 * First, we have to verify our assumption that the current value of 350 * VA_BITS was chosen such that all translation levels are fully 351 * utilised, and that lowering T0SZ will always result in an additional 352 * translation level to be configured. 353 */ 354#if VA_BITS != EXTRA_SHIFT 355#error "Mismatch between VA_BITS and page size/number of translation levels" 356#endif 357 358 mov x4, EXTRA_PTRS 359 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 360#else 361 /* 362 * If VA_BITS == 48, we don't have to configure an additional 363 * translation level, but the top-level table has more entries. 364 */ 365 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) 366 str_l x4, idmap_ptrs_per_pgd, x5 367#endif 3681: 369 ldr_l x4, idmap_ptrs_per_pgd 370 mov x5, x3 // __pa(__idmap_text_start) 371 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 372 373 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 374 375 /* 376 * Map the kernel image (starting with PHYS_OFFSET). 377 */ 378 adrp x0, init_pg_dir 379 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) 380 add x5, x5, x23 // add KASLR displacement 381 mov x4, PTRS_PER_PGD 382 adrp x6, _end // runtime __pa(_end) 383 adrp x3, _text // runtime __pa(_text) 384 sub x6, x6, x3 // _end - _text 385 add x6, x6, x5 // runtime __va(_end) 386 387 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14 388 389 /* 390 * Since the page tables have been populated with non-cacheable 391 * accesses (MMU disabled), invalidate the idmap and swapper page 392 * tables again to remove any speculatively loaded cache lines. 393 */ 394 adrp x0, idmap_pg_dir 395 adrp x1, init_pg_end 396 sub x1, x1, x0 397 dmb sy 398 bl __inval_dcache_area 399 400 ret x28 401ENDPROC(__create_page_tables) 402 .ltorg 403 404/* 405 * The following fragment of code is executed with the MMU enabled. 406 * 407 * x0 = __PHYS_OFFSET 408 */ 409__primary_switched: 410 adrp x4, init_thread_union 411 add sp, x4, #THREAD_SIZE 412 adr_l x5, init_task 413 msr sp_el0, x5 // Save thread_info 414 415 adr_l x8, vectors // load VBAR_EL1 with virtual 416 msr vbar_el1, x8 // vector table address 417 isb 418 419 stp xzr, x30, [sp, #-16]! 420 mov x29, sp 421 422 str_l x21, __fdt_pointer, x5 // Save FDT pointer 423 424 ldr_l x4, kimage_vaddr // Save the offset between 425 sub x4, x4, x0 // the kernel virtual and 426 str_l x4, kimage_voffset, x5 // physical mappings 427 428 // Clear BSS 429 adr_l x0, __bss_start 430 mov x1, xzr 431 adr_l x2, __bss_stop 432 sub x2, x2, x0 433 bl __pi_memset 434 dsb ishst // Make zero page visible to PTW 435 436#ifdef CONFIG_KASAN 437 bl kasan_early_init 438#endif 439#ifdef CONFIG_RANDOMIZE_BASE 440 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 441 b.ne 0f 442 mov x0, x21 // pass FDT address in x0 443 bl kaslr_early_init // parse FDT for KASLR options 444 cbz x0, 0f // KASLR disabled? just proceed 445 orr x23, x23, x0 // record KASLR offset 446 ldp x29, x30, [sp], #16 // we must enable KASLR, return 447 ret // to __primary_switch() 4480: 449#endif 450 add sp, sp, #16 451 mov x29, #0 452 mov x30, #0 453 b start_kernel 454ENDPROC(__primary_switched) 455 456/* 457 * end early head section, begin head code that is also used for 458 * hotplug and needs to have the same protections as the text region 459 */ 460 .section ".idmap.text","awx" 461 462ENTRY(kimage_vaddr) 463 .quad _text - TEXT_OFFSET 464 465/* 466 * If we're fortunate enough to boot at EL2, ensure that the world is 467 * sane before dropping to EL1. 468 * 469 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 470 * booted in EL1 or EL2 respectively. 471 */ 472ENTRY(el2_setup) 473 msr SPsel, #1 // We want to use SP_EL{1,2} 474 mrs x0, CurrentEL 475 cmp x0, #CurrentEL_EL2 476 b.eq 1f 477 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1) 478 msr sctlr_el1, x0 479 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 480 isb 481 ret 482 4831: mov_q x0, (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 484 msr sctlr_el2, x0 485 486#ifdef CONFIG_ARM64_VHE 487 /* 488 * Check for VHE being present. For the rest of the EL2 setup, 489 * x2 being non-zero indicates that we do have VHE, and that the 490 * kernel is intended to run at EL2. 491 */ 492 mrs x2, id_aa64mmfr1_el1 493 ubfx x2, x2, #8, #4 494#else 495 mov x2, xzr 496#endif 497 498 /* Hyp configuration. */ 499 mov x0, #HCR_RW // 64-bit EL1 500 cbz x2, set_hcr 501 orr x0, x0, #HCR_TGE // Enable Host Extensions 502 orr x0, x0, #HCR_E2H 503set_hcr: 504 msr hcr_el2, x0 505 isb 506 507 /* 508 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 509 * This is not necessary for VHE, since the host kernel runs in EL2, 510 * and EL0 accesses are configured in the later stage of boot process. 511 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 512 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 513 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 514 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 515 * EL2. 516 */ 517 cbnz x2, 1f 518 mrs x0, cnthctl_el2 519 orr x0, x0, #3 // Enable EL1 physical timers 520 msr cnthctl_el2, x0 5211: 522 msr cntvoff_el2, xzr // Clear virtual offset 523 524#ifdef CONFIG_ARM_GIC_V3 525 /* GICv3 system register access */ 526 mrs x0, id_aa64pfr0_el1 527 ubfx x0, x0, #24, #4 528 cmp x0, #1 529 b.ne 3f 530 531 mrs_s x0, SYS_ICC_SRE_EL2 532 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 533 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 534 msr_s SYS_ICC_SRE_EL2, x0 535 isb // Make sure SRE is now set 536 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 537 tbz x0, #0, 3f // and check that it sticks 538 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 539 5403: 541#endif 542 543 /* Populate ID registers. */ 544 mrs x0, midr_el1 545 mrs x1, mpidr_el1 546 msr vpidr_el2, x0 547 msr vmpidr_el2, x1 548 549#ifdef CONFIG_COMPAT 550 msr hstr_el2, xzr // Disable CP15 traps to EL2 551#endif 552 553 /* EL2 debug */ 554 mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer 555 sbfx x0, x1, #8, #4 556 cmp x0, #1 557 b.lt 4f // Skip if no PMU present 558 mrs x0, pmcr_el0 // Disable debug access traps 559 ubfx x0, x0, #11, #5 // to EL2 and allow access to 5604: 561 csel x3, xzr, x0, lt // all PMU counters from EL1 562 563 /* Statistical profiling */ 564 ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer 565 cbz x0, 7f // Skip if SPE not present 566 cbnz x2, 6f // VHE? 567 mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2, 568 and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT) 569 cbnz x4, 5f // then permit sampling of physical 570 mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ 571 1 << SYS_PMSCR_EL2_PA_SHIFT) 572 msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter 5735: 574 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 575 orr x3, x3, x1 // If we don't have VHE, then 576 b 7f // use EL1&0 translation. 5776: // For VHE, use EL2 translation 578 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 5797: 580 msr mdcr_el2, x3 // Configure debug traps 581 582 /* LORegions */ 583 mrs x1, id_aa64mmfr1_el1 584 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4 585 cbz x0, 1f 586 msr_s SYS_LORC_EL1, xzr 5871: 588 589 /* Stage-2 translation */ 590 msr vttbr_el2, xzr 591 592 cbz x2, install_el2_stub 593 594 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 595 isb 596 ret 597 598install_el2_stub: 599 /* 600 * When VHE is not in use, early init of EL2 and EL1 needs to be 601 * done here. 602 * When VHE _is_ in use, EL1 will not be used in the host and 603 * requires no configuration, and all non-hyp-specific EL2 setup 604 * will be done via the _EL1 system register aliases in __cpu_setup. 605 */ 606 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1) 607 msr sctlr_el1, x0 608 609 /* Coprocessor traps. */ 610 mov x0, #0x33ff 611 msr cptr_el2, x0 // Disable copro. traps to EL2 612 613 /* SVE register access */ 614 mrs x1, id_aa64pfr0_el1 615 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4 616 cbz x1, 7f 617 618 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps 619 msr cptr_el2, x0 // Disable copro. traps to EL2 620 isb 621 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 622 msr_s SYS_ZCR_EL2, x1 // length for EL1. 623 624 /* Hypervisor stub */ 6257: adr_l x0, __hyp_stub_vectors 626 msr vbar_el2, x0 627 628 /* spsr */ 629 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 630 PSR_MODE_EL1h) 631 msr spsr_el2, x0 632 msr elr_el2, lr 633 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 634 eret 635ENDPROC(el2_setup) 636 637/* 638 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 639 * in w0. See arch/arm64/include/asm/virt.h for more info. 640 */ 641set_cpu_boot_mode_flag: 642 adr_l x1, __boot_cpu_mode 643 cmp w0, #BOOT_CPU_MODE_EL2 644 b.ne 1f 645 add x1, x1, #4 6461: str w0, [x1] // This CPU has booted in EL1 647 dmb sy 648 dc ivac, x1 // Invalidate potentially stale cache line 649 ret 650ENDPROC(set_cpu_boot_mode_flag) 651 652/* 653 * These values are written with the MMU off, but read with the MMU on. 654 * Writers will invalidate the corresponding address, discarding up to a 655 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 656 * sufficient alignment that the CWG doesn't overlap another section. 657 */ 658 .pushsection ".mmuoff.data.write", "aw" 659/* 660 * We need to find out the CPU boot mode long after boot, so we need to 661 * store it in a writable variable. 662 * 663 * This is not in .bss, because we set it sufficiently early that the boot-time 664 * zeroing of .bss would clobber it. 665 */ 666ENTRY(__boot_cpu_mode) 667 .long BOOT_CPU_MODE_EL2 668 .long BOOT_CPU_MODE_EL1 669/* 670 * The booting CPU updates the failed status @__early_cpu_boot_status, 671 * with MMU turned off. 672 */ 673ENTRY(__early_cpu_boot_status) 674 .long 0 675 676 .popsection 677 678 /* 679 * This provides a "holding pen" for platforms to hold all secondary 680 * cores are held until we're ready for them to initialise. 681 */ 682ENTRY(secondary_holding_pen) 683 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 684 bl set_cpu_boot_mode_flag 685 mrs x0, mpidr_el1 686 mov_q x1, MPIDR_HWID_BITMASK 687 and x0, x0, x1 688 adr_l x3, secondary_holding_pen_release 689pen: ldr x4, [x3] 690 cmp x4, x0 691 b.eq secondary_startup 692 wfe 693 b pen 694ENDPROC(secondary_holding_pen) 695 696 /* 697 * Secondary entry point that jumps straight into the kernel. Only to 698 * be used where CPUs are brought online dynamically by the kernel. 699 */ 700ENTRY(secondary_entry) 701 bl el2_setup // Drop to EL1 702 bl set_cpu_boot_mode_flag 703 b secondary_startup 704ENDPROC(secondary_entry) 705 706secondary_startup: 707 /* 708 * Common entry point for secondary CPUs. 709 */ 710 bl __cpu_setup // initialise processor 711 adrp x1, swapper_pg_dir 712 bl __enable_mmu 713 ldr x8, =__secondary_switched 714 br x8 715ENDPROC(secondary_startup) 716 717__secondary_switched: 718 adr_l x5, vectors 719 msr vbar_el1, x5 720 isb 721 722 adr_l x0, secondary_data 723 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 724 mov sp, x1 725 ldr x2, [x0, #CPU_BOOT_TASK] 726 msr sp_el0, x2 727 mov x29, #0 728 mov x30, #0 729 b secondary_start_kernel 730ENDPROC(__secondary_switched) 731 732/* 733 * The booting CPU updates the failed status @__early_cpu_boot_status, 734 * with MMU turned off. 735 * 736 * update_early_cpu_boot_status tmp, status 737 * - Corrupts tmp1, tmp2 738 * - Writes 'status' to __early_cpu_boot_status and makes sure 739 * it is committed to memory. 740 */ 741 742 .macro update_early_cpu_boot_status status, tmp1, tmp2 743 mov \tmp2, #\status 744 adr_l \tmp1, __early_cpu_boot_status 745 str \tmp2, [\tmp1] 746 dmb sy 747 dc ivac, \tmp1 // Invalidate potentially stale cache line 748 .endm 749 750/* 751 * Enable the MMU. 752 * 753 * x0 = SCTLR_EL1 value for turning on the MMU. 754 * x1 = TTBR1_EL1 value 755 * 756 * Returns to the caller via x30/lr. This requires the caller to be covered 757 * by the .idmap.text section. 758 * 759 * Checks if the selected granule size is supported by the CPU. 760 * If it isn't, park the CPU 761 */ 762ENTRY(__enable_mmu) 763 mrs x2, ID_AA64MMFR0_EL1 764 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 765 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED 766 b.ne __no_granule_support 767 update_early_cpu_boot_status 0, x2, x3 768 adrp x2, idmap_pg_dir 769 phys_to_ttbr x1, x1 770 phys_to_ttbr x2, x2 771 msr ttbr0_el1, x2 // load TTBR0 772 msr ttbr1_el1, x1 // load TTBR1 773 isb 774 msr sctlr_el1, x0 775 isb 776 /* 777 * Invalidate the local I-cache so that any instructions fetched 778 * speculatively from the PoC are discarded, since they may have 779 * been dynamically patched at the PoU. 780 */ 781 ic iallu 782 dsb nsh 783 isb 784 ret 785ENDPROC(__enable_mmu) 786 787__no_granule_support: 788 /* Indicate that this CPU can't boot and is stuck in the kernel */ 789 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 7901: 791 wfe 792 wfi 793 b 1b 794ENDPROC(__no_granule_support) 795 796#ifdef CONFIG_RELOCATABLE 797__relocate_kernel: 798 /* 799 * Iterate over each entry in the relocation table, and apply the 800 * relocations in place. 801 */ 802 ldr w9, =__rela_offset // offset to reloc table 803 ldr w10, =__rela_size // size of reloc table 804 805 mov_q x11, KIMAGE_VADDR // default virtual offset 806 add x11, x11, x23 // actual virtual offset 807 add x9, x9, x11 // __va(.rela) 808 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 809 8100: cmp x9, x10 811 b.hs 1f 812 ldp x11, x12, [x9], #24 813 ldr x13, [x9, #-8] 814 cmp w12, #R_AARCH64_RELATIVE 815 b.ne 0b 816 add x13, x13, x23 // relocate 817 str x13, [x11, x23] 818 b 0b 8191: ret 820ENDPROC(__relocate_kernel) 821#endif 822 823__primary_switch: 824#ifdef CONFIG_RANDOMIZE_BASE 825 mov x19, x0 // preserve new SCTLR_EL1 value 826 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 827#endif 828 829 adrp x1, init_pg_dir 830 bl __enable_mmu 831#ifdef CONFIG_RELOCATABLE 832 bl __relocate_kernel 833#ifdef CONFIG_RANDOMIZE_BASE 834 ldr x8, =__primary_switched 835 adrp x0, __PHYS_OFFSET 836 blr x8 837 838 /* 839 * If we return here, we have a KASLR displacement in x23 which we need 840 * to take into account by discarding the current kernel mapping and 841 * creating a new one. 842 */ 843 pre_disable_mmu_workaround 844 msr sctlr_el1, x20 // disable the MMU 845 isb 846 bl __create_page_tables // recreate kernel mapping 847 848 tlbi vmalle1 // Remove any stale TLB entries 849 dsb nsh 850 851 msr sctlr_el1, x19 // re-enable the MMU 852 isb 853 ic iallu // flush instructions fetched 854 dsb nsh // via old mapping 855 isb 856 857 bl __relocate_kernel 858#endif 859#endif 860 ldr x8, =__primary_switched 861 adrp x0, __PHYS_OFFSET 862 br x8 863ENDPROC(__primary_switch) 864