1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <linux/irqchip/arm-gic-v3.h> 26 27#include <asm/assembler.h> 28#include <asm/ptrace.h> 29#include <asm/asm-offsets.h> 30#include <asm/cache.h> 31#include <asm/cputype.h> 32#include <asm/elf.h> 33#include <asm/kernel-pgtable.h> 34#include <asm/kvm_arm.h> 35#include <asm/memory.h> 36#include <asm/pgtable-hwdef.h> 37#include <asm/pgtable.h> 38#include <asm/page.h> 39#include <asm/smp.h> 40#include <asm/sysreg.h> 41#include <asm/thread_info.h> 42#include <asm/virt.h> 43 44#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) 45 46#if (TEXT_OFFSET & 0xfff) != 0 47#error TEXT_OFFSET must be at least 4KB aligned 48#elif (PAGE_OFFSET & 0x1fffff) != 0 49#error PAGE_OFFSET must be at least 2MB aligned 50#elif TEXT_OFFSET > 0x1fffff 51#error TEXT_OFFSET must be less than 2MB 52#endif 53 54#define KERNEL_START _text 55#define KERNEL_END _end 56 57/* 58 * Kernel startup entry point. 59 * --------------------------- 60 * 61 * The requirements are: 62 * MMU = off, D-cache = off, I-cache = on or off, 63 * x0 = physical address to the FDT blob. 64 * 65 * This code is mostly position independent so you call this at 66 * __pa(PAGE_OFFSET + TEXT_OFFSET). 67 * 68 * Note that the callee-saved registers are used for storing variables 69 * that are useful before the MMU is enabled. The allocations are described 70 * in the entry routines. 71 */ 72 __HEAD 73_head: 74 /* 75 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 76 */ 77#ifdef CONFIG_EFI 78 /* 79 * This add instruction has no meaningful effect except that 80 * its opcode forms the magic "MZ" signature required by UEFI. 81 */ 82 add x13, x18, #0x16 83 b stext 84#else 85 b stext // branch to kernel start, magic 86 .long 0 // reserved 87#endif 88 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian 89 le64sym _kernel_size_le // Effective size of kernel image, little-endian 90 le64sym _kernel_flags_le // Informative flags, little-endian 91 .quad 0 // reserved 92 .quad 0 // reserved 93 .quad 0 // reserved 94 .byte 0x41 // Magic number, "ARM\x64" 95 .byte 0x52 96 .byte 0x4d 97 .byte 0x64 98#ifdef CONFIG_EFI 99 .long pe_header - _head // Offset to the PE header. 100#else 101 .word 0 // reserved 102#endif 103 104#ifdef CONFIG_EFI 105 .globl __efistub_stext_offset 106 .set __efistub_stext_offset, stext - _head 107 .align 3 108pe_header: 109 .ascii "PE" 110 .short 0 111coff_header: 112 .short 0xaa64 // AArch64 113 .short 2 // nr_sections 114 .long 0 // TimeDateStamp 115 .long 0 // PointerToSymbolTable 116 .long 1 // NumberOfSymbols 117 .short section_table - optional_header // SizeOfOptionalHeader 118 .short 0x206 // Characteristics. 119 // IMAGE_FILE_DEBUG_STRIPPED | 120 // IMAGE_FILE_EXECUTABLE_IMAGE | 121 // IMAGE_FILE_LINE_NUMS_STRIPPED 122optional_header: 123 .short 0x20b // PE32+ format 124 .byte 0x02 // MajorLinkerVersion 125 .byte 0x14 // MinorLinkerVersion 126 .long _end - stext // SizeOfCode 127 .long 0 // SizeOfInitializedData 128 .long 0 // SizeOfUninitializedData 129 .long __efistub_entry - _head // AddressOfEntryPoint 130 .long __efistub_stext_offset // BaseOfCode 131 132extra_header_fields: 133 .quad 0 // ImageBase 134 .long 0x1000 // SectionAlignment 135 .long PECOFF_FILE_ALIGNMENT // FileAlignment 136 .short 0 // MajorOperatingSystemVersion 137 .short 0 // MinorOperatingSystemVersion 138 .short 0 // MajorImageVersion 139 .short 0 // MinorImageVersion 140 .short 0 // MajorSubsystemVersion 141 .short 0 // MinorSubsystemVersion 142 .long 0 // Win32VersionValue 143 144 .long _end - _head // SizeOfImage 145 146 // Everything before the kernel image is considered part of the header 147 .long __efistub_stext_offset // SizeOfHeaders 148 .long 0 // CheckSum 149 .short 0xa // Subsystem (EFI application) 150 .short 0 // DllCharacteristics 151 .quad 0 // SizeOfStackReserve 152 .quad 0 // SizeOfStackCommit 153 .quad 0 // SizeOfHeapReserve 154 .quad 0 // SizeOfHeapCommit 155 .long 0 // LoaderFlags 156 .long 0x6 // NumberOfRvaAndSizes 157 158 .quad 0 // ExportTable 159 .quad 0 // ImportTable 160 .quad 0 // ResourceTable 161 .quad 0 // ExceptionTable 162 .quad 0 // CertificationTable 163 .quad 0 // BaseRelocationTable 164 165 // Section table 166section_table: 167 168 /* 169 * The EFI application loader requires a relocation section 170 * because EFI applications must be relocatable. This is a 171 * dummy section as far as we are concerned. 172 */ 173 .ascii ".reloc" 174 .byte 0 175 .byte 0 // end of 0 padding of section name 176 .long 0 177 .long 0 178 .long 0 // SizeOfRawData 179 .long 0 // PointerToRawData 180 .long 0 // PointerToRelocations 181 .long 0 // PointerToLineNumbers 182 .short 0 // NumberOfRelocations 183 .short 0 // NumberOfLineNumbers 184 .long 0x42100040 // Characteristics (section flags) 185 186 187 .ascii ".text" 188 .byte 0 189 .byte 0 190 .byte 0 // end of 0 padding of section name 191 .long _end - stext // VirtualSize 192 .long __efistub_stext_offset // VirtualAddress 193 .long _edata - stext // SizeOfRawData 194 .long __efistub_stext_offset // PointerToRawData 195 196 .long 0 // PointerToRelocations (0 for executables) 197 .long 0 // PointerToLineNumbers (0 for executables) 198 .short 0 // NumberOfRelocations (0 for executables) 199 .short 0 // NumberOfLineNumbers (0 for executables) 200 .long 0xe0500020 // Characteristics (section flags) 201 202 /* 203 * EFI will load stext onwards at the 4k section alignment 204 * described in the PE/COFF header. To ensure that instruction 205 * sequences using an adrp and a :lo12: immediate will function 206 * correctly at this alignment, we must ensure that stext is 207 * placed at a 4k boundary in the Image to begin with. 208 */ 209 .align 12 210#endif 211 212ENTRY(stext) 213 bl preserve_boot_args 214 bl el2_setup // Drop to EL1, w20=cpu_boot_mode 215 mov x23, xzr // KASLR offset, defaults to 0 216 adrp x24, __PHYS_OFFSET 217 bl set_cpu_boot_mode_flag 218 bl __create_page_tables // x25=TTBR0, x26=TTBR1 219 /* 220 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 221 * details. 222 * On return, the CPU will be ready for the MMU to be turned on and 223 * the TCR will have been set. 224 */ 225 ldr x27, 0f // address to jump to after 226 // MMU has been enabled 227 adr_l lr, __enable_mmu // return (PIC) address 228 b __cpu_setup // initialise processor 229ENDPROC(stext) 230 .align 3 2310: .quad __mmap_switched - (_head - TEXT_OFFSET) + KIMAGE_VADDR 232 233/* 234 * Preserve the arguments passed by the bootloader in x0 .. x3 235 */ 236preserve_boot_args: 237 mov x21, x0 // x21=FDT 238 239 adr_l x0, boot_args // record the contents of 240 stp x21, x1, [x0] // x0 .. x3 at kernel entry 241 stp x2, x3, [x0, #16] 242 243 dmb sy // needed before dc ivac with 244 // MMU off 245 246 add x1, x0, #0x20 // 4 x 8 bytes 247 b __inval_cache_range // tail call 248ENDPROC(preserve_boot_args) 249 250/* 251 * Macro to create a table entry to the next page. 252 * 253 * tbl: page table address 254 * virt: virtual address 255 * shift: #imm page table shift 256 * ptrs: #imm pointers per table page 257 * 258 * Preserves: virt 259 * Corrupts: tmp1, tmp2 260 * Returns: tbl -> next level table page address 261 */ 262 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 263 lsr \tmp1, \virt, #\shift 264 and \tmp1, \tmp1, #\ptrs - 1 // table index 265 add \tmp2, \tbl, #PAGE_SIZE 266 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 267 str \tmp2, [\tbl, \tmp1, lsl #3] 268 add \tbl, \tbl, #PAGE_SIZE // next level table page 269 .endm 270 271/* 272 * Macro to populate the PGD (and possibily PUD) for the corresponding 273 * block entry in the next level (tbl) for the given virtual address. 274 * 275 * Preserves: tbl, next, virt 276 * Corrupts: tmp1, tmp2 277 */ 278 .macro create_pgd_entry, tbl, virt, tmp1, tmp2 279 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 280#if SWAPPER_PGTABLE_LEVELS > 3 281 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2 282#endif 283#if SWAPPER_PGTABLE_LEVELS > 2 284 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 285#endif 286 .endm 287 288/* 289 * Macro to populate block entries in the page table for the start..end 290 * virtual range (inclusive). 291 * 292 * Preserves: tbl, flags 293 * Corrupts: phys, start, end, pstate 294 */ 295 .macro create_block_map, tbl, flags, phys, start, end 296 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT 297 lsr \start, \start, #SWAPPER_BLOCK_SHIFT 298 and \start, \start, #PTRS_PER_PTE - 1 // table index 299 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry 300 lsr \end, \end, #SWAPPER_BLOCK_SHIFT 301 and \end, \end, #PTRS_PER_PTE - 1 // table end index 3029999: str \phys, [\tbl, \start, lsl #3] // store the entry 303 add \start, \start, #1 // next entry 304 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block 305 cmp \start, \end 306 b.ls 9999b 307 .endm 308 309/* 310 * Setup the initial page tables. We only setup the barest amount which is 311 * required to get the kernel running. The following sections are required: 312 * - identity mapping to enable the MMU (low address, TTBR0) 313 * - first few MB of the kernel linear mapping to jump to once the MMU has 314 * been enabled 315 */ 316__create_page_tables: 317 adrp x25, idmap_pg_dir 318 adrp x26, swapper_pg_dir 319 mov x28, lr 320 321 /* 322 * Invalidate the idmap and swapper page tables to avoid potential 323 * dirty cache lines being evicted. 324 */ 325 mov x0, x25 326 add x1, x26, #SWAPPER_DIR_SIZE 327 bl __inval_cache_range 328 329 /* 330 * Clear the idmap and swapper page tables. 331 */ 332 mov x0, x25 333 add x6, x26, #SWAPPER_DIR_SIZE 3341: stp xzr, xzr, [x0], #16 335 stp xzr, xzr, [x0], #16 336 stp xzr, xzr, [x0], #16 337 stp xzr, xzr, [x0], #16 338 cmp x0, x6 339 b.lo 1b 340 341 ldr x7, =SWAPPER_MM_MMUFLAGS 342 343 /* 344 * Create the identity mapping. 345 */ 346 mov x0, x25 // idmap_pg_dir 347 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 348 349#ifndef CONFIG_ARM64_VA_BITS_48 350#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 351#define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) 352 353 /* 354 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be 355 * created that covers system RAM if that is located sufficiently high 356 * in the physical address space. So for the ID map, use an extended 357 * virtual range in that case, by configuring an additional translation 358 * level. 359 * First, we have to verify our assumption that the current value of 360 * VA_BITS was chosen such that all translation levels are fully 361 * utilised, and that lowering T0SZ will always result in an additional 362 * translation level to be configured. 363 */ 364#if VA_BITS != EXTRA_SHIFT 365#error "Mismatch between VA_BITS and page size/number of translation levels" 366#endif 367 368 /* 369 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 370 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 371 * this number conveniently equals the number of leading zeroes in 372 * the physical address of __idmap_text_end. 373 */ 374 adrp x5, __idmap_text_end 375 clz x5, x5 376 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 377 b.ge 1f // .. then skip additional level 378 379 adr_l x6, idmap_t0sz 380 str x5, [x6] 381 dmb sy 382 dc ivac, x6 // Invalidate potentially stale cache line 383 384 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 3851: 386#endif 387 388 create_pgd_entry x0, x3, x5, x6 389 mov x5, x3 // __pa(__idmap_text_start) 390 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 391 create_block_map x0, x7, x3, x5, x6 392 393 /* 394 * Map the kernel image (starting with PHYS_OFFSET). 395 */ 396 mov x0, x26 // swapper_pg_dir 397 ldr x5, =KIMAGE_VADDR 398 add x5, x5, x23 // add KASLR displacement 399 create_pgd_entry x0, x5, x3, x6 400 ldr w6, kernel_img_size 401 add x6, x6, x5 402 mov x3, x24 // phys offset 403 create_block_map x0, x7, x3, x5, x6 404 405 /* 406 * Since the page tables have been populated with non-cacheable 407 * accesses (MMU disabled), invalidate the idmap and swapper page 408 * tables again to remove any speculatively loaded cache lines. 409 */ 410 mov x0, x25 411 add x1, x26, #SWAPPER_DIR_SIZE 412 dmb sy 413 bl __inval_cache_range 414 415 ret x28 416ENDPROC(__create_page_tables) 417 418kernel_img_size: 419 .long _end - (_head - TEXT_OFFSET) 420 .ltorg 421 422/* 423 * The following fragment of code is executed with the MMU enabled. 424 */ 425 .set initial_sp, init_thread_union + THREAD_START_SP 426__mmap_switched: 427 mov x28, lr // preserve LR 428 adr_l x8, vectors // load VBAR_EL1 with virtual 429 msr vbar_el1, x8 // vector table address 430 isb 431 432 // Clear BSS 433 adr_l x0, __bss_start 434 mov x1, xzr 435 adr_l x2, __bss_stop 436 sub x2, x2, x0 437 bl __pi_memset 438 dsb ishst // Make zero page visible to PTW 439 440#ifdef CONFIG_RELOCATABLE 441 442 /* 443 * Iterate over each entry in the relocation table, and apply the 444 * relocations in place. 445 */ 446 adr_l x8, __dynsym_start // start of symbol table 447 adr_l x9, __reloc_start // start of reloc table 448 adr_l x10, __reloc_end // end of reloc table 449 4500: cmp x9, x10 451 b.hs 2f 452 ldp x11, x12, [x9], #24 453 ldr x13, [x9, #-8] 454 cmp w12, #R_AARCH64_RELATIVE 455 b.ne 1f 456 add x13, x13, x23 // relocate 457 str x13, [x11, x23] 458 b 0b 459 4601: cmp w12, #R_AARCH64_ABS64 461 b.ne 0b 462 add x12, x12, x12, lsl #1 // symtab offset: 24x top word 463 add x12, x8, x12, lsr #(32 - 3) // ... shifted into bottom word 464 ldrsh w14, [x12, #6] // Elf64_Sym::st_shndx 465 ldr x15, [x12, #8] // Elf64_Sym::st_value 466 cmp w14, #-0xf // SHN_ABS (0xfff1) ? 467 add x14, x15, x23 // relocate 468 csel x15, x14, x15, ne 469 add x15, x13, x15 470 str x15, [x11, x23] 471 b 0b 472 4732: adr_l x8, kimage_vaddr // make relocated kimage_vaddr 474 dc cvac, x8 // value visible to secondaries 475 dsb sy // with MMU off 476#endif 477 478 adr_l sp, initial_sp, x4 479 mov x4, sp 480 and x4, x4, #~(THREAD_SIZE - 1) 481 msr sp_el0, x4 // Save thread_info 482 str_l x21, __fdt_pointer, x5 // Save FDT pointer 483 484 ldr_l x4, kimage_vaddr // Save the offset between 485 sub x4, x4, x24 // the kernel virtual and 486 str_l x4, kimage_voffset, x5 // physical mappings 487 488 mov x29, #0 489#ifdef CONFIG_KASAN 490 bl kasan_early_init 491#endif 492#ifdef CONFIG_RANDOMIZE_BASE 493 cbnz x23, 0f // already running randomized? 494 mov x0, x21 // pass FDT address in x0 495 bl kaslr_early_init // parse FDT for KASLR options 496 cbz x0, 0f // KASLR disabled? just proceed 497 mov x23, x0 // record KASLR offset 498 ret x28 // we must enable KASLR, return 499 // to __enable_mmu() 5000: 501#endif 502 b start_kernel 503ENDPROC(__mmap_switched) 504 505/* 506 * end early head section, begin head code that is also used for 507 * hotplug and needs to have the same protections as the text region 508 */ 509 .section ".text","ax" 510 511ENTRY(kimage_vaddr) 512 .quad _text - TEXT_OFFSET 513 514/* 515 * If we're fortunate enough to boot at EL2, ensure that the world is 516 * sane before dropping to EL1. 517 * 518 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if 519 * booted in EL1 or EL2 respectively. 520 */ 521ENTRY(el2_setup) 522 mrs x0, CurrentEL 523 cmp x0, #CurrentEL_EL2 524 b.ne 1f 525 mrs x0, sctlr_el2 526CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 527CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 528 msr sctlr_el2, x0 529 b 2f 5301: mrs x0, sctlr_el1 531CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 532CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 533 msr sctlr_el1, x0 534 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 535 isb 536 ret 537 5382: 539#ifdef CONFIG_ARM64_VHE 540 /* 541 * Check for VHE being present. For the rest of the EL2 setup, 542 * x2 being non-zero indicates that we do have VHE, and that the 543 * kernel is intended to run at EL2. 544 */ 545 mrs x2, id_aa64mmfr1_el1 546 ubfx x2, x2, #8, #4 547#else 548 mov x2, xzr 549#endif 550 551 /* Hyp configuration. */ 552 mov x0, #HCR_RW // 64-bit EL1 553 cbz x2, set_hcr 554 orr x0, x0, #HCR_TGE // Enable Host Extensions 555 orr x0, x0, #HCR_E2H 556set_hcr: 557 msr hcr_el2, x0 558 isb 559 560 /* Generic timers. */ 561 mrs x0, cnthctl_el2 562 orr x0, x0, #3 // Enable EL1 physical timers 563 msr cnthctl_el2, x0 564 msr cntvoff_el2, xzr // Clear virtual offset 565 566#ifdef CONFIG_ARM_GIC_V3 567 /* GICv3 system register access */ 568 mrs x0, id_aa64pfr0_el1 569 ubfx x0, x0, #24, #4 570 cmp x0, #1 571 b.ne 3f 572 573 mrs_s x0, ICC_SRE_EL2 574 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 575 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 576 msr_s ICC_SRE_EL2, x0 577 isb // Make sure SRE is now set 578 mrs_s x0, ICC_SRE_EL2 // Read SRE back, 579 tbz x0, #0, 3f // and check that it sticks 580 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 581 5823: 583#endif 584 585 /* Populate ID registers. */ 586 mrs x0, midr_el1 587 mrs x1, mpidr_el1 588 msr vpidr_el2, x0 589 msr vmpidr_el2, x1 590 591 /* 592 * When VHE is not in use, early init of EL2 and EL1 needs to be 593 * done here. 594 * When VHE _is_ in use, EL1 will not be used in the host and 595 * requires no configuration, and all non-hyp-specific EL2 setup 596 * will be done via the _EL1 system register aliases in __cpu_setup. 597 */ 598 cbnz x2, 1f 599 600 /* sctlr_el1 */ 601 mov x0, #0x0800 // Set/clear RES{1,0} bits 602CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems 603CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems 604 msr sctlr_el1, x0 605 606 /* Coprocessor traps. */ 607 mov x0, #0x33ff 608 msr cptr_el2, x0 // Disable copro. traps to EL2 6091: 610 611#ifdef CONFIG_COMPAT 612 msr hstr_el2, xzr // Disable CP15 traps to EL2 613#endif 614 615 /* EL2 debug */ 616 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer 617 sbfx x0, x0, #8, #4 618 cmp x0, #1 619 b.lt 4f // Skip if no PMU present 620 mrs x0, pmcr_el0 // Disable debug access traps 621 ubfx x0, x0, #11, #5 // to EL2 and allow access to 622 msr mdcr_el2, x0 // all PMU counters from EL1 6234: 624 625 /* Stage-2 translation */ 626 msr vttbr_el2, xzr 627 628 cbz x2, install_el2_stub 629 630 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 631 isb 632 ret 633 634install_el2_stub: 635 /* Hypervisor stub */ 636 adrp x0, __hyp_stub_vectors 637 add x0, x0, #:lo12:__hyp_stub_vectors 638 msr vbar_el2, x0 639 640 /* spsr */ 641 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 642 PSR_MODE_EL1h) 643 msr spsr_el2, x0 644 msr elr_el2, lr 645 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 646 eret 647ENDPROC(el2_setup) 648 649/* 650 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 651 * in x20. See arch/arm64/include/asm/virt.h for more info. 652 */ 653ENTRY(set_cpu_boot_mode_flag) 654 adr_l x1, __boot_cpu_mode 655 cmp w20, #BOOT_CPU_MODE_EL2 656 b.ne 1f 657 add x1, x1, #4 6581: str w20, [x1] // This CPU has booted in EL1 659 dmb sy 660 dc ivac, x1 // Invalidate potentially stale cache line 661 ret 662ENDPROC(set_cpu_boot_mode_flag) 663 664/* 665 * We need to find out the CPU boot mode long after boot, so we need to 666 * store it in a writable variable. 667 * 668 * This is not in .bss, because we set it sufficiently early that the boot-time 669 * zeroing of .bss would clobber it. 670 */ 671 .pushsection .data..cacheline_aligned 672 .align L1_CACHE_SHIFT 673ENTRY(__boot_cpu_mode) 674 .long BOOT_CPU_MODE_EL2 675 .long BOOT_CPU_MODE_EL1 676 .popsection 677 678 /* 679 * This provides a "holding pen" for platforms to hold all secondary 680 * cores are held until we're ready for them to initialise. 681 */ 682ENTRY(secondary_holding_pen) 683 bl el2_setup // Drop to EL1, w20=cpu_boot_mode 684 bl set_cpu_boot_mode_flag 685 mrs x0, mpidr_el1 686 ldr x1, =MPIDR_HWID_BITMASK 687 and x0, x0, x1 688 adr_l x3, secondary_holding_pen_release 689pen: ldr x4, [x3] 690 cmp x4, x0 691 b.eq secondary_startup 692 wfe 693 b pen 694ENDPROC(secondary_holding_pen) 695 696 /* 697 * Secondary entry point that jumps straight into the kernel. Only to 698 * be used where CPUs are brought online dynamically by the kernel. 699 */ 700ENTRY(secondary_entry) 701 bl el2_setup // Drop to EL1 702 bl set_cpu_boot_mode_flag 703 b secondary_startup 704ENDPROC(secondary_entry) 705 706ENTRY(secondary_startup) 707 /* 708 * Common entry point for secondary CPUs. 709 */ 710 adrp x25, idmap_pg_dir 711 adrp x26, swapper_pg_dir 712 bl __cpu_setup // initialise processor 713 714 ldr x8, kimage_vaddr 715 ldr w9, 0f 716 sub x27, x8, w9, sxtw // address to jump to after enabling the MMU 717 b __enable_mmu 718ENDPROC(secondary_startup) 7190: .long (_text - TEXT_OFFSET) - __secondary_switched 720 721ENTRY(__secondary_switched) 722 adr_l x5, vectors 723 msr vbar_el1, x5 724 isb 725 726 adr_l x0, secondary_data 727 ldr x0, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 728 mov sp, x0 729 and x0, x0, #~(THREAD_SIZE - 1) 730 msr sp_el0, x0 // save thread_info 731 mov x29, #0 732 b secondary_start_kernel 733ENDPROC(__secondary_switched) 734 735/* 736 * The booting CPU updates the failed status @__early_cpu_boot_status, 737 * with MMU turned off. 738 * 739 * update_early_cpu_boot_status tmp, status 740 * - Corrupts tmp1, tmp2 741 * - Writes 'status' to __early_cpu_boot_status and makes sure 742 * it is committed to memory. 743 */ 744 745 .macro update_early_cpu_boot_status status, tmp1, tmp2 746 mov \tmp2, #\status 747 adr_l \tmp1, __early_cpu_boot_status 748 str \tmp2, [\tmp1] 749 dmb sy 750 dc ivac, \tmp1 // Invalidate potentially stale cache line 751 .endm 752 753 .pushsection .data..cacheline_aligned 754 .align L1_CACHE_SHIFT 755ENTRY(__early_cpu_boot_status) 756 .long 0 757 .popsection 758 759/* 760 * Enable the MMU. 761 * 762 * x0 = SCTLR_EL1 value for turning on the MMU. 763 * x27 = *virtual* address to jump to upon completion 764 * 765 * Other registers depend on the function called upon completion. 766 * 767 * Checks if the selected granule size is supported by the CPU. 768 * If it isn't, park the CPU 769 */ 770 .section ".idmap.text", "ax" 771__enable_mmu: 772 mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value 773 mrs x1, ID_AA64MMFR0_EL1 774 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 775 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED 776 b.ne __no_granule_support 777 update_early_cpu_boot_status 0, x1, x2 778 msr ttbr0_el1, x25 // load TTBR0 779 msr ttbr1_el1, x26 // load TTBR1 780 isb 781 msr sctlr_el1, x0 782 isb 783 /* 784 * Invalidate the local I-cache so that any instructions fetched 785 * speculatively from the PoC are discarded, since they may have 786 * been dynamically patched at the PoU. 787 */ 788 ic iallu 789 dsb nsh 790 isb 791#ifdef CONFIG_RANDOMIZE_BASE 792 mov x19, x0 // preserve new SCTLR_EL1 value 793 blr x27 794 795 /* 796 * If we return here, we have a KASLR displacement in x23 which we need 797 * to take into account by discarding the current kernel mapping and 798 * creating a new one. 799 */ 800 msr sctlr_el1, x22 // disable the MMU 801 isb 802 bl __create_page_tables // recreate kernel mapping 803 804 msr sctlr_el1, x19 // re-enable the MMU 805 isb 806 ic iallu // flush instructions fetched 807 dsb nsh // via old mapping 808 isb 809 add x27, x27, x23 // relocated __mmap_switched 810#endif 811 br x27 812ENDPROC(__enable_mmu) 813 814__no_granule_support: 815 /* Indicate that this CPU can't boot and is stuck in the kernel */ 816 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 8171: 818 wfe 819 wfi 820 b 1b 821ENDPROC(__no_granule_support) 822