xref: /openbmc/linux/arch/arm64/kernel/head.S (revision 4a44a19b) 
1/*
2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
4 *
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors:	Catalin Marinas <catalin.marinas@arm.com>
8 *		Will Deacon <will.deacon@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include <linux/linkage.h>
24#include <linux/init.h>
25#include <linux/irqchip/arm-gic-v3.h>
26
27#include <asm/assembler.h>
28#include <asm/ptrace.h>
29#include <asm/asm-offsets.h>
30#include <asm/cache.h>
31#include <asm/cputype.h>
32#include <asm/memory.h>
33#include <asm/thread_info.h>
34#include <asm/pgtable-hwdef.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/virt.h>
38
39#define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
40
41#if (TEXT_OFFSET & 0xfff) != 0
42#error TEXT_OFFSET must be at least 4KB aligned
43#elif (PAGE_OFFSET & 0x1fffff) != 0
44#error PAGE_OFFSET must be at least 2MB aligned
45#elif TEXT_OFFSET > 0x1fffff
46#error TEXT_OFFSET must be less than 2MB
47#endif
48
49	.macro	pgtbl, ttb0, ttb1, virt_to_phys
50	ldr	\ttb1, =swapper_pg_dir
51	ldr	\ttb0, =idmap_pg_dir
52	add	\ttb1, \ttb1, \virt_to_phys
53	add	\ttb0, \ttb0, \virt_to_phys
54	.endm
55
56#ifdef CONFIG_ARM64_64K_PAGES
57#define BLOCK_SHIFT	PAGE_SHIFT
58#define BLOCK_SIZE	PAGE_SIZE
59#define TABLE_SHIFT	PMD_SHIFT
60#else
61#define BLOCK_SHIFT	SECTION_SHIFT
62#define BLOCK_SIZE	SECTION_SIZE
63#define TABLE_SHIFT	PUD_SHIFT
64#endif
65
66#define KERNEL_START	KERNEL_RAM_VADDR
67#define KERNEL_END	_end
68
69/*
70 * Initial memory map attributes.
71 */
72#ifndef CONFIG_SMP
73#define PTE_FLAGS	PTE_TYPE_PAGE | PTE_AF
74#define PMD_FLAGS	PMD_TYPE_SECT | PMD_SECT_AF
75#else
76#define PTE_FLAGS	PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
77#define PMD_FLAGS	PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
78#endif
79
80#ifdef CONFIG_ARM64_64K_PAGES
81#define MM_MMUFLAGS	PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
82#else
83#define MM_MMUFLAGS	PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
84#endif
85
86/*
87 * Kernel startup entry point.
88 * ---------------------------
89 *
90 * The requirements are:
91 *   MMU = off, D-cache = off, I-cache = on or off,
92 *   x0 = physical address to the FDT blob.
93 *
94 * This code is mostly position independent so you call this at
95 * __pa(PAGE_OFFSET + TEXT_OFFSET).
96 *
97 * Note that the callee-saved registers are used for storing variables
98 * that are useful before the MMU is enabled. The allocations are described
99 * in the entry routines.
100 */
101	__HEAD
102
103	/*
104	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
105	 */
106#ifdef CONFIG_EFI
107efi_head:
108	/*
109	 * This add instruction has no meaningful effect except that
110	 * its opcode forms the magic "MZ" signature required by UEFI.
111	 */
112	add	x13, x18, #0x16
113	b	stext
114#else
115	b	stext				// branch to kernel start, magic
116	.long	0				// reserved
117#endif
118	.quad	_kernel_offset_le		// Image load offset from start of RAM, little-endian
119	.quad	_kernel_size_le			// Effective size of kernel image, little-endian
120	.quad	_kernel_flags_le		// Informative flags, little-endian
121	.quad	0				// reserved
122	.quad	0				// reserved
123	.quad	0				// reserved
124	.byte	0x41				// Magic number, "ARM\x64"
125	.byte	0x52
126	.byte	0x4d
127	.byte	0x64
128#ifdef CONFIG_EFI
129	.long	pe_header - efi_head		// Offset to the PE header.
130#else
131	.word	0				// reserved
132#endif
133
134#ifdef CONFIG_EFI
135	.align 3
136pe_header:
137	.ascii	"PE"
138	.short 	0
139coff_header:
140	.short	0xaa64				// AArch64
141	.short	2				// nr_sections
142	.long	0 				// TimeDateStamp
143	.long	0				// PointerToSymbolTable
144	.long	1				// NumberOfSymbols
145	.short	section_table - optional_header	// SizeOfOptionalHeader
146	.short	0x206				// Characteristics.
147						// IMAGE_FILE_DEBUG_STRIPPED |
148						// IMAGE_FILE_EXECUTABLE_IMAGE |
149						// IMAGE_FILE_LINE_NUMS_STRIPPED
150optional_header:
151	.short	0x20b				// PE32+ format
152	.byte	0x02				// MajorLinkerVersion
153	.byte	0x14				// MinorLinkerVersion
154	.long	_end - stext			// SizeOfCode
155	.long	0				// SizeOfInitializedData
156	.long	0				// SizeOfUninitializedData
157	.long	efi_stub_entry - efi_head	// AddressOfEntryPoint
158	.long	stext - efi_head		// BaseOfCode
159
160extra_header_fields:
161	.quad	0				// ImageBase
162	.long	0x20				// SectionAlignment
163	.long	0x8				// FileAlignment
164	.short	0				// MajorOperatingSystemVersion
165	.short	0				// MinorOperatingSystemVersion
166	.short	0				// MajorImageVersion
167	.short	0				// MinorImageVersion
168	.short	0				// MajorSubsystemVersion
169	.short	0				// MinorSubsystemVersion
170	.long	0				// Win32VersionValue
171
172	.long	_end - efi_head			// SizeOfImage
173
174	// Everything before the kernel image is considered part of the header
175	.long	stext - efi_head		// SizeOfHeaders
176	.long	0				// CheckSum
177	.short	0xa				// Subsystem (EFI application)
178	.short	0				// DllCharacteristics
179	.quad	0				// SizeOfStackReserve
180	.quad	0				// SizeOfStackCommit
181	.quad	0				// SizeOfHeapReserve
182	.quad	0				// SizeOfHeapCommit
183	.long	0				// LoaderFlags
184	.long	0x6				// NumberOfRvaAndSizes
185
186	.quad	0				// ExportTable
187	.quad	0				// ImportTable
188	.quad	0				// ResourceTable
189	.quad	0				// ExceptionTable
190	.quad	0				// CertificationTable
191	.quad	0				// BaseRelocationTable
192
193	// Section table
194section_table:
195
196	/*
197	 * The EFI application loader requires a relocation section
198	 * because EFI applications must be relocatable.  This is a
199	 * dummy section as far as we are concerned.
200	 */
201	.ascii	".reloc"
202	.byte	0
203	.byte	0			// end of 0 padding of section name
204	.long	0
205	.long	0
206	.long	0			// SizeOfRawData
207	.long	0			// PointerToRawData
208	.long	0			// PointerToRelocations
209	.long	0			// PointerToLineNumbers
210	.short	0			// NumberOfRelocations
211	.short	0			// NumberOfLineNumbers
212	.long	0x42100040		// Characteristics (section flags)
213
214
215	.ascii	".text"
216	.byte	0
217	.byte	0
218	.byte	0        		// end of 0 padding of section name
219	.long	_end - stext		// VirtualSize
220	.long	stext - efi_head	// VirtualAddress
221	.long	_edata - stext		// SizeOfRawData
222	.long	stext - efi_head	// PointerToRawData
223
224	.long	0		// PointerToRelocations (0 for executables)
225	.long	0		// PointerToLineNumbers (0 for executables)
226	.short	0		// NumberOfRelocations  (0 for executables)
227	.short	0		// NumberOfLineNumbers  (0 for executables)
228	.long	0xe0500020	// Characteristics (section flags)
229	.align 5
230#endif
231
232ENTRY(stext)
233	mov	x21, x0				// x21=FDT
234	bl	el2_setup			// Drop to EL1, w20=cpu_boot_mode
235	bl	__calc_phys_offset		// x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
236	bl	set_cpu_boot_mode_flag
237	mrs	x22, midr_el1			// x22=cpuid
238	mov	x0, x22
239	bl	lookup_processor_type
240	mov	x23, x0				// x23=current cpu_table
241	cbz	x23, __error_p			// invalid processor (x23=0)?
242	bl	__vet_fdt
243	bl	__create_page_tables		// x25=TTBR0, x26=TTBR1
244	/*
245	 * The following calls CPU specific code in a position independent
246	 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
247	 * cpu_info structure selected by lookup_processor_type above.
248	 * On return, the CPU will be ready for the MMU to be turned on and
249	 * the TCR will have been set.
250	 */
251	ldr	x27, __switch_data		// address to jump to after
252						// MMU has been enabled
253	adr	lr, __enable_mmu		// return (PIC) address
254	ldr	x12, [x23, #CPU_INFO_SETUP]
255	add	x12, x12, x28			// __virt_to_phys
256	br	x12				// initialise processor
257ENDPROC(stext)
258
259/*
260 * If we're fortunate enough to boot at EL2, ensure that the world is
261 * sane before dropping to EL1.
262 *
263 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
264 * booted in EL1 or EL2 respectively.
265 */
266ENTRY(el2_setup)
267	mrs	x0, CurrentEL
268	cmp	x0, #CurrentEL_EL2
269	b.ne	1f
270	mrs	x0, sctlr_el2
271CPU_BE(	orr	x0, x0, #(1 << 25)	)	// Set the EE bit for EL2
272CPU_LE(	bic	x0, x0, #(1 << 25)	)	// Clear the EE bit for EL2
273	msr	sctlr_el2, x0
274	b	2f
2751:	mrs	x0, sctlr_el1
276CPU_BE(	orr	x0, x0, #(3 << 24)	)	// Set the EE and E0E bits for EL1
277CPU_LE(	bic	x0, x0, #(3 << 24)	)	// Clear the EE and E0E bits for EL1
278	msr	sctlr_el1, x0
279	mov	w20, #BOOT_CPU_MODE_EL1		// This cpu booted in EL1
280	isb
281	ret
282
283	/* Hyp configuration. */
2842:	mov	x0, #(1 << 31)			// 64-bit EL1
285	msr	hcr_el2, x0
286
287	/* Generic timers. */
288	mrs	x0, cnthctl_el2
289	orr	x0, x0, #3			// Enable EL1 physical timers
290	msr	cnthctl_el2, x0
291	msr	cntvoff_el2, xzr		// Clear virtual offset
292
293#ifdef CONFIG_ARM_GIC_V3
294	/* GICv3 system register access */
295	mrs	x0, id_aa64pfr0_el1
296	ubfx	x0, x0, #24, #4
297	cmp	x0, #1
298	b.ne	3f
299
300	mrs_s	x0, ICC_SRE_EL2
301	orr	x0, x0, #ICC_SRE_EL2_SRE	// Set ICC_SRE_EL2.SRE==1
302	orr	x0, x0, #ICC_SRE_EL2_ENABLE	// Set ICC_SRE_EL2.Enable==1
303	msr_s	ICC_SRE_EL2, x0
304	isb					// Make sure SRE is now set
305	msr_s	ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults
306
3073:
308#endif
309
310	/* Populate ID registers. */
311	mrs	x0, midr_el1
312	mrs	x1, mpidr_el1
313	msr	vpidr_el2, x0
314	msr	vmpidr_el2, x1
315
316	/* sctlr_el1 */
317	mov	x0, #0x0800			// Set/clear RES{1,0} bits
318CPU_BE(	movk	x0, #0x33d0, lsl #16	)	// Set EE and E0E on BE systems
319CPU_LE(	movk	x0, #0x30d0, lsl #16	)	// Clear EE and E0E on LE systems
320	msr	sctlr_el1, x0
321
322	/* Coprocessor traps. */
323	mov	x0, #0x33ff
324	msr	cptr_el2, x0			// Disable copro. traps to EL2
325
326#ifdef CONFIG_COMPAT
327	msr	hstr_el2, xzr			// Disable CP15 traps to EL2
328#endif
329
330	/* Stage-2 translation */
331	msr	vttbr_el2, xzr
332
333	/* Hypervisor stub */
334	adr	x0, __hyp_stub_vectors
335	msr	vbar_el2, x0
336
337	/* spsr */
338	mov	x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
339		      PSR_MODE_EL1h)
340	msr	spsr_el2, x0
341	msr	elr_el2, lr
342	mov	w20, #BOOT_CPU_MODE_EL2		// This CPU booted in EL2
343	eret
344ENDPROC(el2_setup)
345
346/*
347 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
348 * in x20. See arch/arm64/include/asm/virt.h for more info.
349 */
350ENTRY(set_cpu_boot_mode_flag)
351	ldr	x1, =__boot_cpu_mode		// Compute __boot_cpu_mode
352	add	x1, x1, x28
353	cmp	w20, #BOOT_CPU_MODE_EL2
354	b.ne	1f
355	add	x1, x1, #4
3561:	str	w20, [x1]			// This CPU has booted in EL1
357	dmb	sy
358	dc	ivac, x1			// Invalidate potentially stale cache line
359	ret
360ENDPROC(set_cpu_boot_mode_flag)
361
362/*
363 * We need to find out the CPU boot mode long after boot, so we need to
364 * store it in a writable variable.
365 *
366 * This is not in .bss, because we set it sufficiently early that the boot-time
367 * zeroing of .bss would clobber it.
368 */
369	.pushsection	.data..cacheline_aligned
370ENTRY(__boot_cpu_mode)
371	.align	L1_CACHE_SHIFT
372	.long	BOOT_CPU_MODE_EL2
373	.long	0
374	.popsection
375
376#ifdef CONFIG_SMP
377	.align	3
3781:	.quad	.
379	.quad	secondary_holding_pen_release
380
381	/*
382	 * This provides a "holding pen" for platforms to hold all secondary
383	 * cores are held until we're ready for them to initialise.
384	 */
385ENTRY(secondary_holding_pen)
386	bl	el2_setup			// Drop to EL1, w20=cpu_boot_mode
387	bl	__calc_phys_offset		// x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
388	bl	set_cpu_boot_mode_flag
389	mrs	x0, mpidr_el1
390	ldr     x1, =MPIDR_HWID_BITMASK
391	and	x0, x0, x1
392	adr	x1, 1b
393	ldp	x2, x3, [x1]
394	sub	x1, x1, x2
395	add	x3, x3, x1
396pen:	ldr	x4, [x3]
397	cmp	x4, x0
398	b.eq	secondary_startup
399	wfe
400	b	pen
401ENDPROC(secondary_holding_pen)
402
403	/*
404	 * Secondary entry point that jumps straight into the kernel. Only to
405	 * be used where CPUs are brought online dynamically by the kernel.
406	 */
407ENTRY(secondary_entry)
408	bl	el2_setup			// Drop to EL1
409	bl	__calc_phys_offset		// x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
410	bl	set_cpu_boot_mode_flag
411	b	secondary_startup
412ENDPROC(secondary_entry)
413
414ENTRY(secondary_startup)
415	/*
416	 * Common entry point for secondary CPUs.
417	 */
418	mrs	x22, midr_el1			// x22=cpuid
419	mov	x0, x22
420	bl	lookup_processor_type
421	mov	x23, x0				// x23=current cpu_table
422	cbz	x23, __error_p			// invalid processor (x23=0)?
423
424	pgtbl	x25, x26, x28			// x25=TTBR0, x26=TTBR1
425	ldr	x12, [x23, #CPU_INFO_SETUP]
426	add	x12, x12, x28			// __virt_to_phys
427	blr	x12				// initialise processor
428
429	ldr	x21, =secondary_data
430	ldr	x27, =__secondary_switched	// address to jump to after enabling the MMU
431	b	__enable_mmu
432ENDPROC(secondary_startup)
433
434ENTRY(__secondary_switched)
435	ldr	x0, [x21]			// get secondary_data.stack
436	mov	sp, x0
437	mov	x29, #0
438	b	secondary_start_kernel
439ENDPROC(__secondary_switched)
440#endif	/* CONFIG_SMP */
441
442/*
443 * Setup common bits before finally enabling the MMU. Essentially this is just
444 * loading the page table pointer and vector base registers.
445 *
446 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
447 * the MMU.
448 */
449__enable_mmu:
450	ldr	x5, =vectors
451	msr	vbar_el1, x5
452	msr	ttbr0_el1, x25			// load TTBR0
453	msr	ttbr1_el1, x26			// load TTBR1
454	isb
455	b	__turn_mmu_on
456ENDPROC(__enable_mmu)
457
458/*
459 * Enable the MMU. This completely changes the structure of the visible memory
460 * space. You will not be able to trace execution through this.
461 *
462 *  x0  = system control register
463 *  x27 = *virtual* address to jump to upon completion
464 *
465 * other registers depend on the function called upon completion
466 *
467 * We align the entire function to the smallest power of two larger than it to
468 * ensure it fits within a single block map entry. Otherwise were PHYS_OFFSET
469 * close to the end of a 512MB or 1GB block we might require an additional
470 * table to map the entire function.
471 */
472	.align	4
473__turn_mmu_on:
474	msr	sctlr_el1, x0
475	isb
476	br	x27
477ENDPROC(__turn_mmu_on)
478
479/*
480 * Calculate the start of physical memory.
481 */
482__calc_phys_offset:
483	adr	x0, 1f
484	ldp	x1, x2, [x0]
485	sub	x28, x0, x1			// x28 = PHYS_OFFSET - PAGE_OFFSET
486	add	x24, x2, x28			// x24 = PHYS_OFFSET
487	ret
488ENDPROC(__calc_phys_offset)
489
490	.align 3
4911:	.quad	.
492	.quad	PAGE_OFFSET
493
494/*
495 * Macro to create a table entry to the next page.
496 *
497 *	tbl:	page table address
498 *	virt:	virtual address
499 *	shift:	#imm page table shift
500 *	ptrs:	#imm pointers per table page
501 *
502 * Preserves:	virt
503 * Corrupts:	tmp1, tmp2
504 * Returns:	tbl -> next level table page address
505 */
506	.macro	create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
507	lsr	\tmp1, \virt, #\shift
508	and	\tmp1, \tmp1, #\ptrs - 1	// table index
509	add	\tmp2, \tbl, #PAGE_SIZE
510	orr	\tmp2, \tmp2, #PMD_TYPE_TABLE	// address of next table and entry type
511	str	\tmp2, [\tbl, \tmp1, lsl #3]
512	add	\tbl, \tbl, #PAGE_SIZE		// next level table page
513	.endm
514
515/*
516 * Macro to populate the PGD (and possibily PUD) for the corresponding
517 * block entry in the next level (tbl) for the given virtual address.
518 *
519 * Preserves:	tbl, next, virt
520 * Corrupts:	tmp1, tmp2
521 */
522	.macro	create_pgd_entry, tbl, virt, tmp1, tmp2
523	create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
524#if SWAPPER_PGTABLE_LEVELS == 3
525	create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
526#endif
527	.endm
528
529/*
530 * Macro to populate block entries in the page table for the start..end
531 * virtual range (inclusive).
532 *
533 * Preserves:	tbl, flags
534 * Corrupts:	phys, start, end, pstate
535 */
536	.macro	create_block_map, tbl, flags, phys, start, end
537	lsr	\phys, \phys, #BLOCK_SHIFT
538	lsr	\start, \start, #BLOCK_SHIFT
539	and	\start, \start, #PTRS_PER_PTE - 1	// table index
540	orr	\phys, \flags, \phys, lsl #BLOCK_SHIFT	// table entry
541	lsr	\end, \end, #BLOCK_SHIFT
542	and	\end, \end, #PTRS_PER_PTE - 1		// table end index
5439999:	str	\phys, [\tbl, \start, lsl #3]		// store the entry
544	add	\start, \start, #1			// next entry
545	add	\phys, \phys, #BLOCK_SIZE		// next block
546	cmp	\start, \end
547	b.ls	9999b
548	.endm
549
550/*
551 * Setup the initial page tables. We only setup the barest amount which is
552 * required to get the kernel running. The following sections are required:
553 *   - identity mapping to enable the MMU (low address, TTBR0)
554 *   - first few MB of the kernel linear mapping to jump to once the MMU has
555 *     been enabled, including the FDT blob (TTBR1)
556 *   - pgd entry for fixed mappings (TTBR1)
557 */
558__create_page_tables:
559	pgtbl	x25, x26, x28			// idmap_pg_dir and swapper_pg_dir addresses
560	mov	x27, lr
561
562	/*
563	 * Invalidate the idmap and swapper page tables to avoid potential
564	 * dirty cache lines being evicted.
565	 */
566	mov	x0, x25
567	add	x1, x26, #SWAPPER_DIR_SIZE
568	bl	__inval_cache_range
569
570	/*
571	 * Clear the idmap and swapper page tables.
572	 */
573	mov	x0, x25
574	add	x6, x26, #SWAPPER_DIR_SIZE
5751:	stp	xzr, xzr, [x0], #16
576	stp	xzr, xzr, [x0], #16
577	stp	xzr, xzr, [x0], #16
578	stp	xzr, xzr, [x0], #16
579	cmp	x0, x6
580	b.lo	1b
581
582	ldr	x7, =MM_MMUFLAGS
583
584	/*
585	 * Create the identity mapping.
586	 */
587	mov	x0, x25				// idmap_pg_dir
588	ldr	x3, =KERNEL_START
589	add	x3, x3, x28			// __pa(KERNEL_START)
590	create_pgd_entry x0, x3, x5, x6
591	ldr	x6, =KERNEL_END
592	mov	x5, x3				// __pa(KERNEL_START)
593	add	x6, x6, x28			// __pa(KERNEL_END)
594	create_block_map x0, x7, x3, x5, x6
595
596	/*
597	 * Map the kernel image (starting with PHYS_OFFSET).
598	 */
599	mov	x0, x26				// swapper_pg_dir
600	mov	x5, #PAGE_OFFSET
601	create_pgd_entry x0, x5, x3, x6
602	ldr	x6, =KERNEL_END
603	mov	x3, x24				// phys offset
604	create_block_map x0, x7, x3, x5, x6
605
606	/*
607	 * Map the FDT blob (maximum 2MB; must be within 512MB of
608	 * PHYS_OFFSET).
609	 */
610	mov	x3, x21				// FDT phys address
611	and	x3, x3, #~((1 << 21) - 1)	// 2MB aligned
612	mov	x6, #PAGE_OFFSET
613	sub	x5, x3, x24			// subtract PHYS_OFFSET
614	tst	x5, #~((1 << 29) - 1)		// within 512MB?
615	csel	x21, xzr, x21, ne		// zero the FDT pointer
616	b.ne	1f
617	add	x5, x5, x6			// __va(FDT blob)
618	add	x6, x5, #1 << 21		// 2MB for the FDT blob
619	sub	x6, x6, #1			// inclusive range
620	create_block_map x0, x7, x3, x5, x6
6211:
622	/*
623	 * Since the page tables have been populated with non-cacheable
624	 * accesses (MMU disabled), invalidate the idmap and swapper page
625	 * tables again to remove any speculatively loaded cache lines.
626	 */
627	mov	x0, x25
628	add	x1, x26, #SWAPPER_DIR_SIZE
629	bl	__inval_cache_range
630
631	mov	lr, x27
632	ret
633ENDPROC(__create_page_tables)
634	.ltorg
635
636	.align	3
637	.type	__switch_data, %object
638__switch_data:
639	.quad	__mmap_switched
640	.quad	__bss_start			// x6
641	.quad	__bss_stop			// x7
642	.quad	processor_id			// x4
643	.quad	__fdt_pointer			// x5
644	.quad	memstart_addr			// x6
645	.quad	init_thread_union + THREAD_START_SP // sp
646
647/*
648 * The following fragment of code is executed with the MMU on in MMU mode, and
649 * uses absolute addresses; this is not position independent.
650 */
651__mmap_switched:
652	adr	x3, __switch_data + 8
653
654	ldp	x6, x7, [x3], #16
6551:	cmp	x6, x7
656	b.hs	2f
657	str	xzr, [x6], #8			// Clear BSS
658	b	1b
6592:
660	ldp	x4, x5, [x3], #16
661	ldr	x6, [x3], #8
662	ldr	x16, [x3]
663	mov	sp, x16
664	str	x22, [x4]			// Save processor ID
665	str	x21, [x5]			// Save FDT pointer
666	str	x24, [x6]			// Save PHYS_OFFSET
667	mov	x29, #0
668	b	start_kernel
669ENDPROC(__mmap_switched)
670
671/*
672 * Exception handling. Something went wrong and we can't proceed. We ought to
673 * tell the user, but since we don't have any guarantee that we're even
674 * running on the right architecture, we do virtually nothing.
675 */
676__error_p:
677ENDPROC(__error_p)
678
679__error:
6801:	nop
681	b	1b
682ENDPROC(__error)
683
684/*
685 * This function gets the processor ID in w0 and searches the cpu_table[] for
686 * a match. It returns a pointer to the struct cpu_info it found. The
687 * cpu_table[] must end with an empty (all zeros) structure.
688 *
689 * This routine can be called via C code and it needs to work with the MMU
690 * both disabled and enabled (the offset is calculated automatically).
691 */
692ENTRY(lookup_processor_type)
693	adr	x1, __lookup_processor_type_data
694	ldp	x2, x3, [x1]
695	sub	x1, x1, x2			// get offset between VA and PA
696	add	x3, x3, x1			// convert VA to PA
6971:
698	ldp	w5, w6, [x3]			// load cpu_id_val and cpu_id_mask
699	cbz	w5, 2f				// end of list?
700	and	w6, w6, w0
701	cmp	w5, w6
702	b.eq	3f
703	add	x3, x3, #CPU_INFO_SZ
704	b	1b
7052:
706	mov	x3, #0				// unknown processor
7073:
708	mov	x0, x3
709	ret
710ENDPROC(lookup_processor_type)
711
712	.align	3
713	.type	__lookup_processor_type_data, %object
714__lookup_processor_type_data:
715	.quad	.
716	.quad	cpu_table
717	.size	__lookup_processor_type_data, . - __lookup_processor_type_data
718
719/*
720 * Determine validity of the x21 FDT pointer.
721 * The dtb must be 8-byte aligned and live in the first 512M of memory.
722 */
723__vet_fdt:
724	tst	x21, #0x7
725	b.ne	1f
726	cmp	x21, x24
727	b.lt	1f
728	mov	x0, #(1 << 29)
729	add	x0, x0, x24
730	cmp	x21, x0
731	b.ge	1f
732	ret
7331:
734	mov	x21, #0
735	ret
736ENDPROC(__vet_fdt)
737