1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level CPU initialisation 4 * Based on arch/arm/kernel/head.S 5 * 6 * Copyright (C) 1994-2002 Russell King 7 * Copyright (C) 2003-2012 ARM Ltd. 8 * Authors: Catalin Marinas <catalin.marinas@arm.com> 9 * Will Deacon <will.deacon@arm.com> 10 */ 11 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/pgtable.h> 15 16#include <asm/asm_pointer_auth.h> 17#include <asm/assembler.h> 18#include <asm/boot.h> 19#include <asm/bug.h> 20#include <asm/ptrace.h> 21#include <asm/asm-offsets.h> 22#include <asm/cache.h> 23#include <asm/cputype.h> 24#include <asm/el2_setup.h> 25#include <asm/elf.h> 26#include <asm/image.h> 27#include <asm/kernel-pgtable.h> 28#include <asm/kvm_arm.h> 29#include <asm/memory.h> 30#include <asm/pgtable-hwdef.h> 31#include <asm/page.h> 32#include <asm/scs.h> 33#include <asm/smp.h> 34#include <asm/sysreg.h> 35#include <asm/thread_info.h> 36#include <asm/virt.h> 37 38#include "efi-header.S" 39 40#define __PHYS_OFFSET KERNEL_START 41 42#if (PAGE_OFFSET & 0x1fffff) != 0 43#error PAGE_OFFSET must be at least 2MB aligned 44#endif 45 46/* 47 * Kernel startup entry point. 48 * --------------------------- 49 * 50 * The requirements are: 51 * MMU = off, D-cache = off, I-cache = on or off, 52 * x0 = physical address to the FDT blob. 53 * 54 * This code is mostly position independent so you call this at 55 * __pa(PAGE_OFFSET). 56 * 57 * Note that the callee-saved registers are used for storing variables 58 * that are useful before the MMU is enabled. The allocations are described 59 * in the entry routines. 60 */ 61 __HEAD 62 /* 63 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 64 */ 65 efi_signature_nop // special NOP to identity as PE/COFF executable 66 b primary_entry // branch to kernel start, magic 67 .quad 0 // Image load offset from start of RAM, little-endian 68 le64sym _kernel_size_le // Effective size of kernel image, little-endian 69 le64sym _kernel_flags_le // Informative flags, little-endian 70 .quad 0 // reserved 71 .quad 0 // reserved 72 .quad 0 // reserved 73 .ascii ARM64_IMAGE_MAGIC // Magic number 74 .long .Lpe_header_offset // Offset to the PE header. 75 76 __EFI_PE_HEADER 77 78 __INIT 79 80 /* 81 * The following callee saved general purpose registers are used on the 82 * primary lowlevel boot path: 83 * 84 * Register Scope Purpose 85 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0 86 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset 87 * x28 __create_page_tables() callee preserved temp register 88 * x19/x20 __primary_switch() callee preserved temp registers 89 * x24 __primary_switch() .. relocate_kernel() current RELR displacement 90 */ 91SYM_CODE_START(primary_entry) 92 bl preserve_boot_args 93 bl init_kernel_el // w0=cpu_boot_mode 94 adrp x23, __PHYS_OFFSET 95 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 96 bl set_cpu_boot_mode_flag 97 bl __create_page_tables 98 /* 99 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 100 * details. 101 * On return, the CPU will be ready for the MMU to be turned on and 102 * the TCR will have been set. 103 */ 104 bl __cpu_setup // initialise processor 105 b __primary_switch 106SYM_CODE_END(primary_entry) 107 108/* 109 * Preserve the arguments passed by the bootloader in x0 .. x3 110 */ 111SYM_CODE_START_LOCAL(preserve_boot_args) 112 mov x21, x0 // x21=FDT 113 114 adr_l x0, boot_args // record the contents of 115 stp x21, x1, [x0] // x0 .. x3 at kernel entry 116 stp x2, x3, [x0, #16] 117 118 dmb sy // needed before dc ivac with 119 // MMU off 120 121 add x1, x0, #0x20 // 4 x 8 bytes 122 b dcache_inval_poc // tail call 123SYM_CODE_END(preserve_boot_args) 124 125/* 126 * Macro to create a table entry to the next page. 127 * 128 * tbl: page table address 129 * virt: virtual address 130 * shift: #imm page table shift 131 * ptrs: #imm pointers per table page 132 * 133 * Preserves: virt 134 * Corrupts: ptrs, tmp1, tmp2 135 * Returns: tbl -> next level table page address 136 */ 137 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 138 add \tmp1, \tbl, #PAGE_SIZE 139 phys_to_pte \tmp2, \tmp1 140 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 141 lsr \tmp1, \virt, #\shift 142 sub \ptrs, \ptrs, #1 143 and \tmp1, \tmp1, \ptrs // table index 144 str \tmp2, [\tbl, \tmp1, lsl #3] 145 add \tbl, \tbl, #PAGE_SIZE // next level table page 146 .endm 147 148/* 149 * Macro to populate page table entries, these entries can be pointers to the next level 150 * or last level entries pointing to physical memory. 151 * 152 * tbl: page table address 153 * rtbl: pointer to page table or physical memory 154 * index: start index to write 155 * eindex: end index to write - [index, eindex] written to 156 * flags: flags for pagetable entry to or in 157 * inc: increment to rtbl between each entry 158 * tmp1: temporary variable 159 * 160 * Preserves: tbl, eindex, flags, inc 161 * Corrupts: index, tmp1 162 * Returns: rtbl 163 */ 164 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 165.Lpe\@: phys_to_pte \tmp1, \rtbl 166 orr \tmp1, \tmp1, \flags // tmp1 = table entry 167 str \tmp1, [\tbl, \index, lsl #3] 168 add \rtbl, \rtbl, \inc // rtbl = pa next level 169 add \index, \index, #1 170 cmp \index, \eindex 171 b.ls .Lpe\@ 172 .endm 173 174/* 175 * Compute indices of table entries from virtual address range. If multiple entries 176 * were needed in the previous page table level then the next page table level is assumed 177 * to be composed of multiple pages. (This effectively scales the end index). 178 * 179 * vstart: virtual address of start of range 180 * vend: virtual address of end of range 181 * shift: shift used to transform virtual address into index 182 * ptrs: number of entries in page table 183 * istart: index in table corresponding to vstart 184 * iend: index in table corresponding to vend 185 * count: On entry: how many extra entries were required in previous level, scales 186 * our end index. 187 * On exit: returns how many extra entries required for next page table level 188 * 189 * Preserves: vstart, vend, shift, ptrs 190 * Returns: istart, iend, count 191 */ 192 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count 193 lsr \iend, \vend, \shift 194 mov \istart, \ptrs 195 sub \istart, \istart, #1 196 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) 197 mov \istart, \ptrs 198 mul \istart, \istart, \count 199 add \iend, \iend, \istart // iend += count * ptrs 200 // our entries span multiple tables 201 202 lsr \istart, \vstart, \shift 203 mov \count, \ptrs 204 sub \count, \count, #1 205 and \istart, \istart, \count 206 207 sub \count, \iend, \istart 208 .endm 209 210/* 211 * Map memory for specified virtual address range. Each level of page table needed supports 212 * multiple entries. If a level requires n entries the next page table level is assumed to be 213 * formed from n pages. 214 * 215 * tbl: location of page table 216 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 217 * vstart: start address to map 218 * vend: end address to map - we map [vstart, vend] 219 * flags: flags to use to map last level entries 220 * phys: physical address corresponding to vstart - physical memory is contiguous 221 * pgds: the number of pgd entries 222 * 223 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 224 * Preserves: vstart, vend, flags 225 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv 226 */ 227 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv 228 add \rtbl, \tbl, #PAGE_SIZE 229 mov \sv, \rtbl 230 mov \count, #0 231 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count 232 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 233 mov \tbl, \sv 234 mov \sv, \rtbl 235 236#if SWAPPER_PGTABLE_LEVELS > 3 237 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count 238 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 239 mov \tbl, \sv 240 mov \sv, \rtbl 241#endif 242 243#if SWAPPER_PGTABLE_LEVELS > 2 244 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count 245 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 246 mov \tbl, \sv 247#endif 248 249 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count 250 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 251 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 252 .endm 253 254/* 255 * Setup the initial page tables. We only setup the barest amount which is 256 * required to get the kernel running. The following sections are required: 257 * - identity mapping to enable the MMU (low address, TTBR0) 258 * - first few MB of the kernel linear mapping to jump to once the MMU has 259 * been enabled 260 */ 261SYM_FUNC_START_LOCAL(__create_page_tables) 262 mov x28, lr 263 264 /* 265 * Invalidate the init page tables to avoid potential dirty cache lines 266 * being evicted. Other page tables are allocated in rodata as part of 267 * the kernel image, and thus are clean to the PoC per the boot 268 * protocol. 269 */ 270 adrp x0, init_pg_dir 271 adrp x1, init_pg_end 272 bl dcache_inval_poc 273 274 /* 275 * Clear the init page tables. 276 */ 277 adrp x0, init_pg_dir 278 adrp x1, init_pg_end 279 sub x1, x1, x0 2801: stp xzr, xzr, [x0], #16 281 stp xzr, xzr, [x0], #16 282 stp xzr, xzr, [x0], #16 283 stp xzr, xzr, [x0], #16 284 subs x1, x1, #64 285 b.ne 1b 286 287 mov x7, SWAPPER_MM_MMUFLAGS 288 289 /* 290 * Create the identity mapping. 291 */ 292 adrp x0, idmap_pg_dir 293 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 294 295#ifdef CONFIG_ARM64_VA_BITS_52 296 mrs_s x6, SYS_ID_AA64MMFR2_EL1 297 and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 298 mov x5, #52 299 cbnz x6, 1f 300#endif 301 mov x5, #VA_BITS_MIN 3021: 303 adr_l x6, vabits_actual 304 str x5, [x6] 305 dmb sy 306 dc ivac, x6 // Invalidate potentially stale cache line 307 308 /* 309 * VA_BITS may be too small to allow for an ID mapping to be created 310 * that covers system RAM if that is located sufficiently high in the 311 * physical address space. So for the ID map, use an extended virtual 312 * range in that case, and configure an additional translation level 313 * if needed. 314 * 315 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 316 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 317 * this number conveniently equals the number of leading zeroes in 318 * the physical address of __idmap_text_end. 319 */ 320 adrp x5, __idmap_text_end 321 clz x5, x5 322 cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough? 323 b.ge 1f // .. then skip VA range extension 324 325 adr_l x6, idmap_t0sz 326 str x5, [x6] 327 dmb sy 328 dc ivac, x6 // Invalidate potentially stale cache line 329 330#if (VA_BITS < 48) 331#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 332#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) 333 334 /* 335 * If VA_BITS < 48, we have to configure an additional table level. 336 * First, we have to verify our assumption that the current value of 337 * VA_BITS was chosen such that all translation levels are fully 338 * utilised, and that lowering T0SZ will always result in an additional 339 * translation level to be configured. 340 */ 341#if VA_BITS != EXTRA_SHIFT 342#error "Mismatch between VA_BITS and page size/number of translation levels" 343#endif 344 345 mov x4, EXTRA_PTRS 346 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 347#else 348 /* 349 * If VA_BITS == 48, we don't have to configure an additional 350 * translation level, but the top-level table has more entries. 351 */ 352 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) 353 str_l x4, idmap_ptrs_per_pgd, x5 354#endif 3551: 356 ldr_l x4, idmap_ptrs_per_pgd 357 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 358 359 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 360 361 /* 362 * Map the kernel image (starting with PHYS_OFFSET). 363 */ 364 adrp x0, init_pg_dir 365 mov_q x5, KIMAGE_VADDR // compile time __va(_text) 366 add x5, x5, x23 // add KASLR displacement 367 mov x4, PTRS_PER_PGD 368 adrp x6, _end // runtime __pa(_end) 369 adrp x3, _text // runtime __pa(_text) 370 sub x6, x6, x3 // _end - _text 371 add x6, x6, x5 // runtime __va(_end) 372 373 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14 374 375 /* 376 * Since the page tables have been populated with non-cacheable 377 * accesses (MMU disabled), invalidate those tables again to 378 * remove any speculatively loaded cache lines. 379 */ 380 dmb sy 381 382 adrp x0, idmap_pg_dir 383 adrp x1, idmap_pg_end 384 bl dcache_inval_poc 385 386 adrp x0, init_pg_dir 387 adrp x1, init_pg_end 388 bl dcache_inval_poc 389 390 ret x28 391SYM_FUNC_END(__create_page_tables) 392 393 /* 394 * Initialize CPU registers with task-specific and cpu-specific context. 395 * 396 * Create a final frame record at task_pt_regs(current)->stackframe, so 397 * that the unwinder can identify the final frame record of any task by 398 * its location in the task stack. We reserve the entire pt_regs space 399 * for consistency with user tasks and kthreads. 400 */ 401 .macro init_cpu_task tsk, tmp1, tmp2 402 msr sp_el0, \tsk 403 404 ldr \tmp1, [\tsk, #TSK_STACK] 405 add sp, \tmp1, #THREAD_SIZE 406 sub sp, sp, #PT_REGS_SIZE 407 408 stp xzr, xzr, [sp, #S_STACKFRAME] 409 add x29, sp, #S_STACKFRAME 410 411 scs_load \tsk 412 413 adr_l \tmp1, __per_cpu_offset 414 ldr w\tmp2, [\tsk, #TSK_CPU] 415 ldr \tmp1, [\tmp1, \tmp2, lsl #3] 416 set_this_cpu_offset \tmp1 417 .endm 418 419/* 420 * The following fragment of code is executed with the MMU enabled. 421 * 422 * x0 = __PHYS_OFFSET 423 */ 424SYM_FUNC_START_LOCAL(__primary_switched) 425 adr_l x4, init_task 426 init_cpu_task x4, x5, x6 427 428 adr_l x8, vectors // load VBAR_EL1 with virtual 429 msr vbar_el1, x8 // vector table address 430 isb 431 432 stp x29, x30, [sp, #-16]! 433 mov x29, sp 434 435 str_l x21, __fdt_pointer, x5 // Save FDT pointer 436 437 ldr_l x4, kimage_vaddr // Save the offset between 438 sub x4, x4, x0 // the kernel virtual and 439 str_l x4, kimage_voffset, x5 // physical mappings 440 441 // Clear BSS 442 adr_l x0, __bss_start 443 mov x1, xzr 444 adr_l x2, __bss_stop 445 sub x2, x2, x0 446 bl __pi_memset 447 dsb ishst // Make zero page visible to PTW 448 449#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 450 bl kasan_early_init 451#endif 452 mov x0, x21 // pass FDT address in x0 453 bl early_fdt_map // Try mapping the FDT early 454 bl init_feature_override // Parse cpu feature overrides 455#ifdef CONFIG_RANDOMIZE_BASE 456 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 457 b.ne 0f 458 bl kaslr_early_init // parse FDT for KASLR options 459 cbz x0, 0f // KASLR disabled? just proceed 460 orr x23, x23, x0 // record KASLR offset 461 ldp x29, x30, [sp], #16 // we must enable KASLR, return 462 ret // to __primary_switch() 4630: 464#endif 465 bl switch_to_vhe // Prefer VHE if possible 466 ldp x29, x30, [sp], #16 467 bl start_kernel 468 ASM_BUG() 469SYM_FUNC_END(__primary_switched) 470 471 .pushsection ".rodata", "a" 472SYM_DATA_START(kimage_vaddr) 473 .quad _text 474SYM_DATA_END(kimage_vaddr) 475EXPORT_SYMBOL(kimage_vaddr) 476 .popsection 477 478/* 479 * end early head section, begin head code that is also used for 480 * hotplug and needs to have the same protections as the text region 481 */ 482 .section ".idmap.text","awx" 483 484/* 485 * Starting from EL2 or EL1, configure the CPU to execute at the highest 486 * reachable EL supported by the kernel in a chosen default state. If dropping 487 * from EL2 to EL1, configure EL2 before configuring EL1. 488 * 489 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if 490 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET. 491 * 492 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 493 * booted in EL1 or EL2 respectively. 494 */ 495SYM_FUNC_START(init_kernel_el) 496 mrs x0, CurrentEL 497 cmp x0, #CurrentEL_EL2 498 b.eq init_el2 499 500SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) 501 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 502 msr sctlr_el1, x0 503 isb 504 mov_q x0, INIT_PSTATE_EL1 505 msr spsr_el1, x0 506 msr elr_el1, lr 507 mov w0, #BOOT_CPU_MODE_EL1 508 eret 509 510SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) 511 mov_q x0, HCR_HOST_NVHE_FLAGS 512 msr hcr_el2, x0 513 isb 514 515 init_el2_state 516 517 /* Hypervisor stub */ 518 adr_l x0, __hyp_stub_vectors 519 msr vbar_el2, x0 520 isb 521 522 /* 523 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, 524 * making it impossible to start in nVHE mode. Is that 525 * compliant with the architecture? Absolutely not! 526 */ 527 mrs x0, hcr_el2 528 and x0, x0, #HCR_E2H 529 cbz x0, 1f 530 531 /* Switching to VHE requires a sane SCTLR_EL1 as a start */ 532 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 533 msr_s SYS_SCTLR_EL12, x0 534 535 /* 536 * Force an eret into a helper "function", and let it return 537 * to our original caller... This makes sure that we have 538 * initialised the basic PSTATE state. 539 */ 540 mov x0, #INIT_PSTATE_EL2 541 msr spsr_el1, x0 542 adr x0, __cpu_stick_to_vhe 543 msr elr_el1, x0 544 eret 545 5461: 547 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 548 msr sctlr_el1, x0 549 550 msr elr_el2, lr 551 mov w0, #BOOT_CPU_MODE_EL2 552 eret 553 554__cpu_stick_to_vhe: 555 mov x0, #HVC_VHE_RESTART 556 hvc #0 557 mov x0, #BOOT_CPU_MODE_EL2 558 ret 559SYM_FUNC_END(init_kernel_el) 560 561/* 562 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 563 * in w0. See arch/arm64/include/asm/virt.h for more info. 564 */ 565SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag) 566 adr_l x1, __boot_cpu_mode 567 cmp w0, #BOOT_CPU_MODE_EL2 568 b.ne 1f 569 add x1, x1, #4 5701: str w0, [x1] // Save CPU boot mode 571 dmb sy 572 dc ivac, x1 // Invalidate potentially stale cache line 573 ret 574SYM_FUNC_END(set_cpu_boot_mode_flag) 575 576/* 577 * These values are written with the MMU off, but read with the MMU on. 578 * Writers will invalidate the corresponding address, discarding up to a 579 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 580 * sufficient alignment that the CWG doesn't overlap another section. 581 */ 582 .pushsection ".mmuoff.data.write", "aw" 583/* 584 * We need to find out the CPU boot mode long after boot, so we need to 585 * store it in a writable variable. 586 * 587 * This is not in .bss, because we set it sufficiently early that the boot-time 588 * zeroing of .bss would clobber it. 589 */ 590SYM_DATA_START(__boot_cpu_mode) 591 .long BOOT_CPU_MODE_EL2 592 .long BOOT_CPU_MODE_EL1 593SYM_DATA_END(__boot_cpu_mode) 594/* 595 * The booting CPU updates the failed status @__early_cpu_boot_status, 596 * with MMU turned off. 597 */ 598SYM_DATA_START(__early_cpu_boot_status) 599 .quad 0 600SYM_DATA_END(__early_cpu_boot_status) 601 602 .popsection 603 604 /* 605 * This provides a "holding pen" for platforms to hold all secondary 606 * cores are held until we're ready for them to initialise. 607 */ 608SYM_FUNC_START(secondary_holding_pen) 609 bl init_kernel_el // w0=cpu_boot_mode 610 bl set_cpu_boot_mode_flag 611 mrs x0, mpidr_el1 612 mov_q x1, MPIDR_HWID_BITMASK 613 and x0, x0, x1 614 adr_l x3, secondary_holding_pen_release 615pen: ldr x4, [x3] 616 cmp x4, x0 617 b.eq secondary_startup 618 wfe 619 b pen 620SYM_FUNC_END(secondary_holding_pen) 621 622 /* 623 * Secondary entry point that jumps straight into the kernel. Only to 624 * be used where CPUs are brought online dynamically by the kernel. 625 */ 626SYM_FUNC_START(secondary_entry) 627 bl init_kernel_el // w0=cpu_boot_mode 628 bl set_cpu_boot_mode_flag 629 b secondary_startup 630SYM_FUNC_END(secondary_entry) 631 632SYM_FUNC_START_LOCAL(secondary_startup) 633 /* 634 * Common entry point for secondary CPUs. 635 */ 636 bl switch_to_vhe 637 bl __cpu_secondary_check52bitva 638 bl __cpu_setup // initialise processor 639 adrp x1, swapper_pg_dir 640 bl __enable_mmu 641 ldr x8, =__secondary_switched 642 br x8 643SYM_FUNC_END(secondary_startup) 644 645SYM_FUNC_START_LOCAL(__secondary_switched) 646 adr_l x5, vectors 647 msr vbar_el1, x5 648 isb 649 650 adr_l x0, secondary_data 651 ldr x2, [x0, #CPU_BOOT_TASK] 652 cbz x2, __secondary_too_slow 653 654 init_cpu_task x2, x1, x3 655 656#ifdef CONFIG_ARM64_PTR_AUTH 657 ptrauth_keys_init_cpu x2, x3, x4, x5 658#endif 659 660 bl secondary_start_kernel 661 ASM_BUG() 662SYM_FUNC_END(__secondary_switched) 663 664SYM_FUNC_START_LOCAL(__secondary_too_slow) 665 wfe 666 wfi 667 b __secondary_too_slow 668SYM_FUNC_END(__secondary_too_slow) 669 670/* 671 * The booting CPU updates the failed status @__early_cpu_boot_status, 672 * with MMU turned off. 673 * 674 * update_early_cpu_boot_status tmp, status 675 * - Corrupts tmp1, tmp2 676 * - Writes 'status' to __early_cpu_boot_status and makes sure 677 * it is committed to memory. 678 */ 679 680 .macro update_early_cpu_boot_status status, tmp1, tmp2 681 mov \tmp2, #\status 682 adr_l \tmp1, __early_cpu_boot_status 683 str \tmp2, [\tmp1] 684 dmb sy 685 dc ivac, \tmp1 // Invalidate potentially stale cache line 686 .endm 687 688/* 689 * Enable the MMU. 690 * 691 * x0 = SCTLR_EL1 value for turning on the MMU. 692 * x1 = TTBR1_EL1 value 693 * 694 * Returns to the caller via x30/lr. This requires the caller to be covered 695 * by the .idmap.text section. 696 * 697 * Checks if the selected granule size is supported by the CPU. 698 * If it isn't, park the CPU 699 */ 700SYM_FUNC_START(__enable_mmu) 701 mrs x2, ID_AA64MMFR0_EL1 702 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 703 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN 704 b.lt __no_granule_support 705 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 706 b.gt __no_granule_support 707 update_early_cpu_boot_status 0, x2, x3 708 adrp x2, idmap_pg_dir 709 phys_to_ttbr x1, x1 710 phys_to_ttbr x2, x2 711 msr ttbr0_el1, x2 // load TTBR0 712 offset_ttbr1 x1, x3 713 msr ttbr1_el1, x1 // load TTBR1 714 isb 715 716 set_sctlr_el1 x0 717 718 ret 719SYM_FUNC_END(__enable_mmu) 720 721SYM_FUNC_START(__cpu_secondary_check52bitva) 722#ifdef CONFIG_ARM64_VA_BITS_52 723 ldr_l x0, vabits_actual 724 cmp x0, #52 725 b.ne 2f 726 727 mrs_s x0, SYS_ID_AA64MMFR2_EL1 728 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 729 cbnz x0, 2f 730 731 update_early_cpu_boot_status \ 732 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 7331: wfe 734 wfi 735 b 1b 736 737#endif 7382: ret 739SYM_FUNC_END(__cpu_secondary_check52bitva) 740 741SYM_FUNC_START_LOCAL(__no_granule_support) 742 /* Indicate that this CPU can't boot and is stuck in the kernel */ 743 update_early_cpu_boot_status \ 744 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 7451: 746 wfe 747 wfi 748 b 1b 749SYM_FUNC_END(__no_granule_support) 750 751#ifdef CONFIG_RELOCATABLE 752SYM_FUNC_START_LOCAL(__relocate_kernel) 753 /* 754 * Iterate over each entry in the relocation table, and apply the 755 * relocations in place. 756 */ 757 ldr w9, =__rela_offset // offset to reloc table 758 ldr w10, =__rela_size // size of reloc table 759 760 mov_q x11, KIMAGE_VADDR // default virtual offset 761 add x11, x11, x23 // actual virtual offset 762 add x9, x9, x11 // __va(.rela) 763 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 764 7650: cmp x9, x10 766 b.hs 1f 767 ldp x12, x13, [x9], #24 768 ldr x14, [x9, #-8] 769 cmp w13, #R_AARCH64_RELATIVE 770 b.ne 0b 771 add x14, x14, x23 // relocate 772 str x14, [x12, x23] 773 b 0b 774 7751: 776#ifdef CONFIG_RELR 777 /* 778 * Apply RELR relocations. 779 * 780 * RELR is a compressed format for storing relative relocations. The 781 * encoded sequence of entries looks like: 782 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] 783 * 784 * i.e. start with an address, followed by any number of bitmaps. The 785 * address entry encodes 1 relocation. The subsequent bitmap entries 786 * encode up to 63 relocations each, at subsequent offsets following 787 * the last address entry. 788 * 789 * The bitmap entries must have 1 in the least significant bit. The 790 * assumption here is that an address cannot have 1 in lsb. Odd 791 * addresses are not supported. Any odd addresses are stored in the RELA 792 * section, which is handled above. 793 * 794 * Excluding the least significant bit in the bitmap, each non-zero 795 * bit in the bitmap represents a relocation to be applied to 796 * a corresponding machine word that follows the base address 797 * word. The second least significant bit represents the machine 798 * word immediately following the initial address, and each bit 799 * that follows represents the next word, in linear order. As such, 800 * a single bitmap can encode up to 63 relocations in a 64-bit object. 801 * 802 * In this implementation we store the address of the next RELR table 803 * entry in x9, the address being relocated by the current address or 804 * bitmap entry in x13 and the address being relocated by the current 805 * bit in x14. 806 * 807 * Because addends are stored in place in the binary, RELR relocations 808 * cannot be applied idempotently. We use x24 to keep track of the 809 * currently applied displacement so that we can correctly relocate if 810 * __relocate_kernel is called twice with non-zero displacements (i.e. 811 * if there is both a physical misalignment and a KASLR displacement). 812 */ 813 ldr w9, =__relr_offset // offset to reloc table 814 ldr w10, =__relr_size // size of reloc table 815 add x9, x9, x11 // __va(.relr) 816 add x10, x9, x10 // __va(.relr) + sizeof(.relr) 817 818 sub x15, x23, x24 // delta from previous offset 819 cbz x15, 7f // nothing to do if unchanged 820 mov x24, x23 // save new offset 821 8222: cmp x9, x10 823 b.hs 7f 824 ldr x11, [x9], #8 825 tbnz x11, #0, 3f // branch to handle bitmaps 826 add x13, x11, x23 827 ldr x12, [x13] // relocate address entry 828 add x12, x12, x15 829 str x12, [x13], #8 // adjust to start of bitmap 830 b 2b 831 8323: mov x14, x13 8334: lsr x11, x11, #1 834 cbz x11, 6f 835 tbz x11, #0, 5f // skip bit if not set 836 ldr x12, [x14] // relocate bit 837 add x12, x12, x15 838 str x12, [x14] 839 8405: add x14, x14, #8 // move to next bit's address 841 b 4b 842 8436: /* 844 * Move to the next bitmap's address. 8 is the word size, and 63 is the 845 * number of significant bits in a bitmap entry. 846 */ 847 add x13, x13, #(8 * 63) 848 b 2b 849 8507: 851#endif 852 ret 853 854SYM_FUNC_END(__relocate_kernel) 855#endif 856 857SYM_FUNC_START_LOCAL(__primary_switch) 858#ifdef CONFIG_RANDOMIZE_BASE 859 mov x19, x0 // preserve new SCTLR_EL1 value 860 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 861#endif 862 863 adrp x1, init_pg_dir 864 bl __enable_mmu 865#ifdef CONFIG_RELOCATABLE 866#ifdef CONFIG_RELR 867 mov x24, #0 // no RELR displacement yet 868#endif 869 bl __relocate_kernel 870#ifdef CONFIG_RANDOMIZE_BASE 871 ldr x8, =__primary_switched 872 adrp x0, __PHYS_OFFSET 873 blr x8 874 875 /* 876 * If we return here, we have a KASLR displacement in x23 which we need 877 * to take into account by discarding the current kernel mapping and 878 * creating a new one. 879 */ 880 pre_disable_mmu_workaround 881 msr sctlr_el1, x20 // disable the MMU 882 isb 883 bl __create_page_tables // recreate kernel mapping 884 885 tlbi vmalle1 // Remove any stale TLB entries 886 dsb nsh 887 isb 888 889 set_sctlr_el1 x19 // re-enable the MMU 890 891 bl __relocate_kernel 892#endif 893#endif 894 ldr x8, =__primary_switched 895 adrp x0, __PHYS_OFFSET 896 br x8 897SYM_FUNC_END(__primary_switch) 898