1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <linux/irqchip/arm-gic-v3.h> 26 27#include <asm/assembler.h> 28#include <asm/boot.h> 29#include <asm/ptrace.h> 30#include <asm/asm-offsets.h> 31#include <asm/cache.h> 32#include <asm/cputype.h> 33#include <asm/elf.h> 34#include <asm/kernel-pgtable.h> 35#include <asm/kvm_arm.h> 36#include <asm/memory.h> 37#include <asm/pgtable-hwdef.h> 38#include <asm/pgtable.h> 39#include <asm/page.h> 40#include <asm/smp.h> 41#include <asm/sysreg.h> 42#include <asm/thread_info.h> 43#include <asm/virt.h> 44 45#include "efi-header.S" 46 47#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) 48 49#if (TEXT_OFFSET & 0xfff) != 0 50#error TEXT_OFFSET must be at least 4KB aligned 51#elif (PAGE_OFFSET & 0x1fffff) != 0 52#error PAGE_OFFSET must be at least 2MB aligned 53#elif TEXT_OFFSET > 0x1fffff 54#error TEXT_OFFSET must be less than 2MB 55#endif 56 57/* 58 * Kernel startup entry point. 59 * --------------------------- 60 * 61 * The requirements are: 62 * MMU = off, D-cache = off, I-cache = on or off, 63 * x0 = physical address to the FDT blob. 64 * 65 * This code is mostly position independent so you call this at 66 * __pa(PAGE_OFFSET + TEXT_OFFSET). 67 * 68 * Note that the callee-saved registers are used for storing variables 69 * that are useful before the MMU is enabled. The allocations are described 70 * in the entry routines. 71 */ 72 __HEAD 73_head: 74 /* 75 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 76 */ 77#ifdef CONFIG_EFI 78 /* 79 * This add instruction has no meaningful effect except that 80 * its opcode forms the magic "MZ" signature required by UEFI. 81 */ 82 add x13, x18, #0x16 83 b stext 84#else 85 b stext // branch to kernel start, magic 86 .long 0 // reserved 87#endif 88 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian 89 le64sym _kernel_size_le // Effective size of kernel image, little-endian 90 le64sym _kernel_flags_le // Informative flags, little-endian 91 .quad 0 // reserved 92 .quad 0 // reserved 93 .quad 0 // reserved 94 .ascii "ARM\x64" // Magic number 95#ifdef CONFIG_EFI 96 .long pe_header - _head // Offset to the PE header. 97 98pe_header: 99 __EFI_PE_HEADER 100#else 101 .long 0 // reserved 102#endif 103 104 __INIT 105 106 /* 107 * The following callee saved general purpose registers are used on the 108 * primary lowlevel boot path: 109 * 110 * Register Scope Purpose 111 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0 112 * x23 stext() .. start_kernel() physical misalignment/KASLR offset 113 * x28 __create_page_tables() callee preserved temp register 114 * x19/x20 __primary_switch() callee preserved temp registers 115 */ 116ENTRY(stext) 117 bl preserve_boot_args 118 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 119 adrp x23, __PHYS_OFFSET 120 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 121 bl set_cpu_boot_mode_flag 122 bl __create_page_tables 123 /* 124 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 125 * details. 126 * On return, the CPU will be ready for the MMU to be turned on and 127 * the TCR will have been set. 128 */ 129 bl __cpu_setup // initialise processor 130 b __primary_switch 131ENDPROC(stext) 132 133/* 134 * Preserve the arguments passed by the bootloader in x0 .. x3 135 */ 136preserve_boot_args: 137 mov x21, x0 // x21=FDT 138 139 adr_l x0, boot_args // record the contents of 140 stp x21, x1, [x0] // x0 .. x3 at kernel entry 141 stp x2, x3, [x0, #16] 142 143 dmb sy // needed before dc ivac with 144 // MMU off 145 146 mov x1, #0x20 // 4 x 8 bytes 147 b __inval_dcache_area // tail call 148ENDPROC(preserve_boot_args) 149 150/* 151 * Macro to create a table entry to the next page. 152 * 153 * tbl: page table address 154 * virt: virtual address 155 * shift: #imm page table shift 156 * ptrs: #imm pointers per table page 157 * 158 * Preserves: virt 159 * Corrupts: tmp1, tmp2 160 * Returns: tbl -> next level table page address 161 */ 162 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 163 lsr \tmp1, \virt, #\shift 164 and \tmp1, \tmp1, #\ptrs - 1 // table index 165 add \tmp2, \tbl, #PAGE_SIZE 166 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 167 str \tmp2, [\tbl, \tmp1, lsl #3] 168 add \tbl, \tbl, #PAGE_SIZE // next level table page 169 .endm 170 171/* 172 * Macro to populate the PGD (and possibily PUD) for the corresponding 173 * block entry in the next level (tbl) for the given virtual address. 174 * 175 * Preserves: tbl, next, virt 176 * Corrupts: tmp1, tmp2 177 */ 178 .macro create_pgd_entry, tbl, virt, tmp1, tmp2 179 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 180#if SWAPPER_PGTABLE_LEVELS > 3 181 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2 182#endif 183#if SWAPPER_PGTABLE_LEVELS > 2 184 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 185#endif 186 .endm 187 188/* 189 * Macro to populate block entries in the page table for the start..end 190 * virtual range (inclusive). 191 * 192 * Preserves: tbl, flags 193 * Corrupts: phys, start, end, pstate 194 */ 195 .macro create_block_map, tbl, flags, phys, start, end 196 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT 197 lsr \start, \start, #SWAPPER_BLOCK_SHIFT 198 and \start, \start, #PTRS_PER_PTE - 1 // table index 199 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry 200 lsr \end, \end, #SWAPPER_BLOCK_SHIFT 201 and \end, \end, #PTRS_PER_PTE - 1 // table end index 2029999: str \phys, [\tbl, \start, lsl #3] // store the entry 203 add \start, \start, #1 // next entry 204 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block 205 cmp \start, \end 206 b.ls 9999b 207 .endm 208 209/* 210 * Setup the initial page tables. We only setup the barest amount which is 211 * required to get the kernel running. The following sections are required: 212 * - identity mapping to enable the MMU (low address, TTBR0) 213 * - first few MB of the kernel linear mapping to jump to once the MMU has 214 * been enabled 215 */ 216__create_page_tables: 217 mov x28, lr 218 219 /* 220 * Invalidate the idmap and swapper page tables to avoid potential 221 * dirty cache lines being evicted. 222 */ 223 adrp x0, idmap_pg_dir 224 ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) 225 bl __inval_dcache_area 226 227 /* 228 * Clear the idmap and swapper page tables. 229 */ 230 adrp x0, idmap_pg_dir 231 ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) 2321: stp xzr, xzr, [x0], #16 233 stp xzr, xzr, [x0], #16 234 stp xzr, xzr, [x0], #16 235 stp xzr, xzr, [x0], #16 236 subs x1, x1, #64 237 b.ne 1b 238 239 mov x7, SWAPPER_MM_MMUFLAGS 240 241 /* 242 * Create the identity mapping. 243 */ 244 adrp x0, idmap_pg_dir 245 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 246 247#ifndef CONFIG_ARM64_VA_BITS_48 248#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 249#define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) 250 251 /* 252 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be 253 * created that covers system RAM if that is located sufficiently high 254 * in the physical address space. So for the ID map, use an extended 255 * virtual range in that case, by configuring an additional translation 256 * level. 257 * First, we have to verify our assumption that the current value of 258 * VA_BITS was chosen such that all translation levels are fully 259 * utilised, and that lowering T0SZ will always result in an additional 260 * translation level to be configured. 261 */ 262#if VA_BITS != EXTRA_SHIFT 263#error "Mismatch between VA_BITS and page size/number of translation levels" 264#endif 265 266 /* 267 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 268 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 269 * this number conveniently equals the number of leading zeroes in 270 * the physical address of __idmap_text_end. 271 */ 272 adrp x5, __idmap_text_end 273 clz x5, x5 274 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 275 b.ge 1f // .. then skip additional level 276 277 adr_l x6, idmap_t0sz 278 str x5, [x6] 279 dmb sy 280 dc ivac, x6 // Invalidate potentially stale cache line 281 282 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 2831: 284#endif 285 286 create_pgd_entry x0, x3, x5, x6 287 mov x5, x3 // __pa(__idmap_text_start) 288 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 289 create_block_map x0, x7, x3, x5, x6 290 291 /* 292 * Map the kernel image (starting with PHYS_OFFSET). 293 */ 294 adrp x0, swapper_pg_dir 295 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) 296 add x5, x5, x23 // add KASLR displacement 297 create_pgd_entry x0, x5, x3, x6 298 adrp x6, _end // runtime __pa(_end) 299 adrp x3, _text // runtime __pa(_text) 300 sub x6, x6, x3 // _end - _text 301 add x6, x6, x5 // runtime __va(_end) 302 create_block_map x0, x7, x3, x5, x6 303 304 /* 305 * Since the page tables have been populated with non-cacheable 306 * accesses (MMU disabled), invalidate the idmap and swapper page 307 * tables again to remove any speculatively loaded cache lines. 308 */ 309 adrp x0, idmap_pg_dir 310 ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) 311 dmb sy 312 bl __inval_dcache_area 313 314 ret x28 315ENDPROC(__create_page_tables) 316 .ltorg 317 318/* 319 * The following fragment of code is executed with the MMU enabled. 320 * 321 * x0 = __PHYS_OFFSET 322 */ 323__primary_switched: 324 adrp x4, init_thread_union 325 add sp, x4, #THREAD_SIZE 326 adr_l x5, init_task 327 msr sp_el0, x5 // Save thread_info 328 329 adr_l x8, vectors // load VBAR_EL1 with virtual 330 msr vbar_el1, x8 // vector table address 331 isb 332 333 stp xzr, x30, [sp, #-16]! 334 mov x29, sp 335 336 str_l x21, __fdt_pointer, x5 // Save FDT pointer 337 338 ldr_l x4, kimage_vaddr // Save the offset between 339 sub x4, x4, x0 // the kernel virtual and 340 str_l x4, kimage_voffset, x5 // physical mappings 341 342 // Clear BSS 343 adr_l x0, __bss_start 344 mov x1, xzr 345 adr_l x2, __bss_stop 346 sub x2, x2, x0 347 bl __pi_memset 348 dsb ishst // Make zero page visible to PTW 349 350#ifdef CONFIG_KASAN 351 bl kasan_early_init 352#endif 353#ifdef CONFIG_RANDOMIZE_BASE 354 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 355 b.ne 0f 356 mov x0, x21 // pass FDT address in x0 357 bl kaslr_early_init // parse FDT for KASLR options 358 cbz x0, 0f // KASLR disabled? just proceed 359 orr x23, x23, x0 // record KASLR offset 360 ldp x29, x30, [sp], #16 // we must enable KASLR, return 361 ret // to __primary_switch() 3620: 363#endif 364 add sp, sp, #16 365 mov x29, #0 366 mov x30, #0 367 b start_kernel 368ENDPROC(__primary_switched) 369 370/* 371 * end early head section, begin head code that is also used for 372 * hotplug and needs to have the same protections as the text region 373 */ 374 .section ".idmap.text","ax" 375 376ENTRY(kimage_vaddr) 377 .quad _text - TEXT_OFFSET 378 379/* 380 * If we're fortunate enough to boot at EL2, ensure that the world is 381 * sane before dropping to EL1. 382 * 383 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 384 * booted in EL1 or EL2 respectively. 385 */ 386ENTRY(el2_setup) 387 mrs x0, CurrentEL 388 cmp x0, #CurrentEL_EL2 389 b.eq 1f 390 mrs x0, sctlr_el1 391CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 392CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 393 msr sctlr_el1, x0 394 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 395 isb 396 ret 397 3981: mrs x0, sctlr_el2 399CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 400CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 401 msr sctlr_el2, x0 402 403#ifdef CONFIG_ARM64_VHE 404 /* 405 * Check for VHE being present. For the rest of the EL2 setup, 406 * x2 being non-zero indicates that we do have VHE, and that the 407 * kernel is intended to run at EL2. 408 */ 409 mrs x2, id_aa64mmfr1_el1 410 ubfx x2, x2, #8, #4 411#else 412 mov x2, xzr 413#endif 414 415 /* Hyp configuration. */ 416 mov x0, #HCR_RW // 64-bit EL1 417 cbz x2, set_hcr 418 orr x0, x0, #HCR_TGE // Enable Host Extensions 419 orr x0, x0, #HCR_E2H 420set_hcr: 421 msr hcr_el2, x0 422 isb 423 424 /* 425 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 426 * This is not necessary for VHE, since the host kernel runs in EL2, 427 * and EL0 accesses are configured in the later stage of boot process. 428 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 429 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 430 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 431 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 432 * EL2. 433 */ 434 cbnz x2, 1f 435 mrs x0, cnthctl_el2 436 orr x0, x0, #3 // Enable EL1 physical timers 437 msr cnthctl_el2, x0 4381: 439 msr cntvoff_el2, xzr // Clear virtual offset 440 441#ifdef CONFIG_ARM_GIC_V3 442 /* GICv3 system register access */ 443 mrs x0, id_aa64pfr0_el1 444 ubfx x0, x0, #24, #4 445 cmp x0, #1 446 b.ne 3f 447 448 mrs_s x0, SYS_ICC_SRE_EL2 449 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 450 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 451 msr_s SYS_ICC_SRE_EL2, x0 452 isb // Make sure SRE is now set 453 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 454 tbz x0, #0, 3f // and check that it sticks 455 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 456 4573: 458#endif 459 460 /* Populate ID registers. */ 461 mrs x0, midr_el1 462 mrs x1, mpidr_el1 463 msr vpidr_el2, x0 464 msr vmpidr_el2, x1 465 466#ifdef CONFIG_COMPAT 467 msr hstr_el2, xzr // Disable CP15 traps to EL2 468#endif 469 470 /* EL2 debug */ 471 mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer 472 sbfx x0, x1, #8, #4 473 cmp x0, #1 474 b.lt 4f // Skip if no PMU present 475 mrs x0, pmcr_el0 // Disable debug access traps 476 ubfx x0, x0, #11, #5 // to EL2 and allow access to 4774: 478 csel x3, xzr, x0, lt // all PMU counters from EL1 479 480 /* Statistical profiling */ 481 ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer 482 cbz x0, 6f // Skip if SPE not present 483 cbnz x2, 5f // VHE? 484 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 485 orr x3, x3, x1 // If we don't have VHE, then 486 b 6f // use EL1&0 translation. 4875: // For VHE, use EL2 translation 488 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 4896: 490 msr mdcr_el2, x3 // Configure debug traps 491 492 /* Stage-2 translation */ 493 msr vttbr_el2, xzr 494 495 cbz x2, install_el2_stub 496 497 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 498 isb 499 ret 500 501install_el2_stub: 502 /* 503 * When VHE is not in use, early init of EL2 and EL1 needs to be 504 * done here. 505 * When VHE _is_ in use, EL1 will not be used in the host and 506 * requires no configuration, and all non-hyp-specific EL2 setup 507 * will be done via the _EL1 system register aliases in __cpu_setup. 508 */ 509 /* sctlr_el1 */ 510 mov x0, #0x0800 // Set/clear RES{1,0} bits 511CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems 512CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems 513 msr sctlr_el1, x0 514 515 /* Coprocessor traps. */ 516 mov x0, #0x33ff 517 msr cptr_el2, x0 // Disable copro. traps to EL2 518 519 /* Hypervisor stub */ 520 adr_l x0, __hyp_stub_vectors 521 msr vbar_el2, x0 522 523 /* spsr */ 524 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 525 PSR_MODE_EL1h) 526 msr spsr_el2, x0 527 msr elr_el2, lr 528 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 529 eret 530ENDPROC(el2_setup) 531 532/* 533 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 534 * in w0. See arch/arm64/include/asm/virt.h for more info. 535 */ 536set_cpu_boot_mode_flag: 537 adr_l x1, __boot_cpu_mode 538 cmp w0, #BOOT_CPU_MODE_EL2 539 b.ne 1f 540 add x1, x1, #4 5411: str w0, [x1] // This CPU has booted in EL1 542 dmb sy 543 dc ivac, x1 // Invalidate potentially stale cache line 544 ret 545ENDPROC(set_cpu_boot_mode_flag) 546 547/* 548 * These values are written with the MMU off, but read with the MMU on. 549 * Writers will invalidate the corresponding address, discarding up to a 550 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 551 * sufficient alignment that the CWG doesn't overlap another section. 552 */ 553 .pushsection ".mmuoff.data.write", "aw" 554/* 555 * We need to find out the CPU boot mode long after boot, so we need to 556 * store it in a writable variable. 557 * 558 * This is not in .bss, because we set it sufficiently early that the boot-time 559 * zeroing of .bss would clobber it. 560 */ 561ENTRY(__boot_cpu_mode) 562 .long BOOT_CPU_MODE_EL2 563 .long BOOT_CPU_MODE_EL1 564/* 565 * The booting CPU updates the failed status @__early_cpu_boot_status, 566 * with MMU turned off. 567 */ 568ENTRY(__early_cpu_boot_status) 569 .long 0 570 571 .popsection 572 573 /* 574 * This provides a "holding pen" for platforms to hold all secondary 575 * cores are held until we're ready for them to initialise. 576 */ 577ENTRY(secondary_holding_pen) 578 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 579 bl set_cpu_boot_mode_flag 580 mrs x0, mpidr_el1 581 mov_q x1, MPIDR_HWID_BITMASK 582 and x0, x0, x1 583 adr_l x3, secondary_holding_pen_release 584pen: ldr x4, [x3] 585 cmp x4, x0 586 b.eq secondary_startup 587 wfe 588 b pen 589ENDPROC(secondary_holding_pen) 590 591 /* 592 * Secondary entry point that jumps straight into the kernel. Only to 593 * be used where CPUs are brought online dynamically by the kernel. 594 */ 595ENTRY(secondary_entry) 596 bl el2_setup // Drop to EL1 597 bl set_cpu_boot_mode_flag 598 b secondary_startup 599ENDPROC(secondary_entry) 600 601secondary_startup: 602 /* 603 * Common entry point for secondary CPUs. 604 */ 605 bl __cpu_setup // initialise processor 606 bl __enable_mmu 607 ldr x8, =__secondary_switched 608 br x8 609ENDPROC(secondary_startup) 610 611__secondary_switched: 612 adr_l x5, vectors 613 msr vbar_el1, x5 614 isb 615 616 adr_l x0, secondary_data 617 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 618 mov sp, x1 619 ldr x2, [x0, #CPU_BOOT_TASK] 620 msr sp_el0, x2 621 mov x29, #0 622 mov x30, #0 623 b secondary_start_kernel 624ENDPROC(__secondary_switched) 625 626/* 627 * The booting CPU updates the failed status @__early_cpu_boot_status, 628 * with MMU turned off. 629 * 630 * update_early_cpu_boot_status tmp, status 631 * - Corrupts tmp1, tmp2 632 * - Writes 'status' to __early_cpu_boot_status and makes sure 633 * it is committed to memory. 634 */ 635 636 .macro update_early_cpu_boot_status status, tmp1, tmp2 637 mov \tmp2, #\status 638 adr_l \tmp1, __early_cpu_boot_status 639 str \tmp2, [\tmp1] 640 dmb sy 641 dc ivac, \tmp1 // Invalidate potentially stale cache line 642 .endm 643 644/* 645 * Enable the MMU. 646 * 647 * x0 = SCTLR_EL1 value for turning on the MMU. 648 * 649 * Returns to the caller via x30/lr. This requires the caller to be covered 650 * by the .idmap.text section. 651 * 652 * Checks if the selected granule size is supported by the CPU. 653 * If it isn't, park the CPU 654 */ 655ENTRY(__enable_mmu) 656 mrs x1, ID_AA64MMFR0_EL1 657 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 658 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED 659 b.ne __no_granule_support 660 update_early_cpu_boot_status 0, x1, x2 661 adrp x1, idmap_pg_dir 662 adrp x2, swapper_pg_dir 663 msr ttbr0_el1, x1 // load TTBR0 664 msr ttbr1_el1, x2 // load TTBR1 665 isb 666 msr sctlr_el1, x0 667 isb 668 /* 669 * Invalidate the local I-cache so that any instructions fetched 670 * speculatively from the PoC are discarded, since they may have 671 * been dynamically patched at the PoU. 672 */ 673 ic iallu 674 dsb nsh 675 isb 676 ret 677ENDPROC(__enable_mmu) 678 679__no_granule_support: 680 /* Indicate that this CPU can't boot and is stuck in the kernel */ 681 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 6821: 683 wfe 684 wfi 685 b 1b 686ENDPROC(__no_granule_support) 687 688#ifdef CONFIG_RELOCATABLE 689__relocate_kernel: 690 /* 691 * Iterate over each entry in the relocation table, and apply the 692 * relocations in place. 693 */ 694 ldr w9, =__rela_offset // offset to reloc table 695 ldr w10, =__rela_size // size of reloc table 696 697 mov_q x11, KIMAGE_VADDR // default virtual offset 698 add x11, x11, x23 // actual virtual offset 699 add x9, x9, x11 // __va(.rela) 700 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 701 7020: cmp x9, x10 703 b.hs 1f 704 ldp x11, x12, [x9], #24 705 ldr x13, [x9, #-8] 706 cmp w12, #R_AARCH64_RELATIVE 707 b.ne 0b 708 add x13, x13, x23 // relocate 709 str x13, [x11, x23] 710 b 0b 7111: ret 712ENDPROC(__relocate_kernel) 713#endif 714 715__primary_switch: 716#ifdef CONFIG_RANDOMIZE_BASE 717 mov x19, x0 // preserve new SCTLR_EL1 value 718 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 719#endif 720 721 bl __enable_mmu 722#ifdef CONFIG_RELOCATABLE 723 bl __relocate_kernel 724#ifdef CONFIG_RANDOMIZE_BASE 725 ldr x8, =__primary_switched 726 adrp x0, __PHYS_OFFSET 727 blr x8 728 729 /* 730 * If we return here, we have a KASLR displacement in x23 which we need 731 * to take into account by discarding the current kernel mapping and 732 * creating a new one. 733 */ 734 msr sctlr_el1, x20 // disable the MMU 735 isb 736 bl __create_page_tables // recreate kernel mapping 737 738 tlbi vmalle1 // Remove any stale TLB entries 739 dsb nsh 740 741 msr sctlr_el1, x19 // re-enable the MMU 742 isb 743 ic iallu // flush instructions fetched 744 dsb nsh // via old mapping 745 isb 746 747 bl __relocate_kernel 748#endif 749#endif 750 ldr x8, =__primary_switched 751 adrp x0, __PHYS_OFFSET 752 br x8 753ENDPROC(__primary_switch) 754