1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level CPU initialisation 4 * Based on arch/arm/kernel/head.S 5 * 6 * Copyright (C) 1994-2002 Russell King 7 * Copyright (C) 2003-2012 ARM Ltd. 8 * Authors: Catalin Marinas <catalin.marinas@arm.com> 9 * Will Deacon <will.deacon@arm.com> 10 */ 11 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/pgtable.h> 15 16#include <asm/asm_pointer_auth.h> 17#include <asm/assembler.h> 18#include <asm/boot.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/cache.h> 22#include <asm/cputype.h> 23#include <asm/el2_setup.h> 24#include <asm/elf.h> 25#include <asm/image.h> 26#include <asm/kernel-pgtable.h> 27#include <asm/kvm_arm.h> 28#include <asm/memory.h> 29#include <asm/pgtable-hwdef.h> 30#include <asm/page.h> 31#include <asm/scs.h> 32#include <asm/smp.h> 33#include <asm/sysreg.h> 34#include <asm/thread_info.h> 35#include <asm/virt.h> 36 37#include "efi-header.S" 38 39#define __PHYS_OFFSET KERNEL_START 40 41#if (PAGE_OFFSET & 0x1fffff) != 0 42#error PAGE_OFFSET must be at least 2MB aligned 43#endif 44 45/* 46 * Kernel startup entry point. 47 * --------------------------- 48 * 49 * The requirements are: 50 * MMU = off, D-cache = off, I-cache = on or off, 51 * x0 = physical address to the FDT blob. 52 * 53 * This code is mostly position independent so you call this at 54 * __pa(PAGE_OFFSET). 55 * 56 * Note that the callee-saved registers are used for storing variables 57 * that are useful before the MMU is enabled. The allocations are described 58 * in the entry routines. 59 */ 60 __HEAD 61 /* 62 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 63 */ 64 efi_signature_nop // special NOP to identity as PE/COFF executable 65 b primary_entry // branch to kernel start, magic 66 .quad 0 // Image load offset from start of RAM, little-endian 67 le64sym _kernel_size_le // Effective size of kernel image, little-endian 68 le64sym _kernel_flags_le // Informative flags, little-endian 69 .quad 0 // reserved 70 .quad 0 // reserved 71 .quad 0 // reserved 72 .ascii ARM64_IMAGE_MAGIC // Magic number 73 .long .Lpe_header_offset // Offset to the PE header. 74 75 __EFI_PE_HEADER 76 77 __INIT 78 79 /* 80 * The following callee saved general purpose registers are used on the 81 * primary lowlevel boot path: 82 * 83 * Register Scope Purpose 84 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0 85 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset 86 * x28 __create_page_tables() callee preserved temp register 87 * x19/x20 __primary_switch() callee preserved temp registers 88 * x24 __primary_switch() .. relocate_kernel() current RELR displacement 89 */ 90SYM_CODE_START(primary_entry) 91 bl preserve_boot_args 92 bl init_kernel_el // w0=cpu_boot_mode 93 adrp x23, __PHYS_OFFSET 94 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 95 bl set_cpu_boot_mode_flag 96 bl __create_page_tables 97 /* 98 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 99 * details. 100 * On return, the CPU will be ready for the MMU to be turned on and 101 * the TCR will have been set. 102 */ 103 bl __cpu_setup // initialise processor 104 b __primary_switch 105SYM_CODE_END(primary_entry) 106 107/* 108 * Preserve the arguments passed by the bootloader in x0 .. x3 109 */ 110SYM_CODE_START_LOCAL(preserve_boot_args) 111 mov x21, x0 // x21=FDT 112 113 adr_l x0, boot_args // record the contents of 114 stp x21, x1, [x0] // x0 .. x3 at kernel entry 115 stp x2, x3, [x0, #16] 116 117 dmb sy // needed before dc ivac with 118 // MMU off 119 120 mov x1, #0x20 // 4 x 8 bytes 121 b __inval_dcache_area // tail call 122SYM_CODE_END(preserve_boot_args) 123 124/* 125 * Macro to create a table entry to the next page. 126 * 127 * tbl: page table address 128 * virt: virtual address 129 * shift: #imm page table shift 130 * ptrs: #imm pointers per table page 131 * 132 * Preserves: virt 133 * Corrupts: ptrs, tmp1, tmp2 134 * Returns: tbl -> next level table page address 135 */ 136 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 137 add \tmp1, \tbl, #PAGE_SIZE 138 phys_to_pte \tmp2, \tmp1 139 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 140 lsr \tmp1, \virt, #\shift 141 sub \ptrs, \ptrs, #1 142 and \tmp1, \tmp1, \ptrs // table index 143 str \tmp2, [\tbl, \tmp1, lsl #3] 144 add \tbl, \tbl, #PAGE_SIZE // next level table page 145 .endm 146 147/* 148 * Macro to populate page table entries, these entries can be pointers to the next level 149 * or last level entries pointing to physical memory. 150 * 151 * tbl: page table address 152 * rtbl: pointer to page table or physical memory 153 * index: start index to write 154 * eindex: end index to write - [index, eindex] written to 155 * flags: flags for pagetable entry to or in 156 * inc: increment to rtbl between each entry 157 * tmp1: temporary variable 158 * 159 * Preserves: tbl, eindex, flags, inc 160 * Corrupts: index, tmp1 161 * Returns: rtbl 162 */ 163 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 164.Lpe\@: phys_to_pte \tmp1, \rtbl 165 orr \tmp1, \tmp1, \flags // tmp1 = table entry 166 str \tmp1, [\tbl, \index, lsl #3] 167 add \rtbl, \rtbl, \inc // rtbl = pa next level 168 add \index, \index, #1 169 cmp \index, \eindex 170 b.ls .Lpe\@ 171 .endm 172 173/* 174 * Compute indices of table entries from virtual address range. If multiple entries 175 * were needed in the previous page table level then the next page table level is assumed 176 * to be composed of multiple pages. (This effectively scales the end index). 177 * 178 * vstart: virtual address of start of range 179 * vend: virtual address of end of range 180 * shift: shift used to transform virtual address into index 181 * ptrs: number of entries in page table 182 * istart: index in table corresponding to vstart 183 * iend: index in table corresponding to vend 184 * count: On entry: how many extra entries were required in previous level, scales 185 * our end index. 186 * On exit: returns how many extra entries required for next page table level 187 * 188 * Preserves: vstart, vend, shift, ptrs 189 * Returns: istart, iend, count 190 */ 191 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count 192 lsr \iend, \vend, \shift 193 mov \istart, \ptrs 194 sub \istart, \istart, #1 195 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) 196 mov \istart, \ptrs 197 mul \istart, \istart, \count 198 add \iend, \iend, \istart // iend += (count - 1) * ptrs 199 // our entries span multiple tables 200 201 lsr \istart, \vstart, \shift 202 mov \count, \ptrs 203 sub \count, \count, #1 204 and \istart, \istart, \count 205 206 sub \count, \iend, \istart 207 .endm 208 209/* 210 * Map memory for specified virtual address range. Each level of page table needed supports 211 * multiple entries. If a level requires n entries the next page table level is assumed to be 212 * formed from n pages. 213 * 214 * tbl: location of page table 215 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 216 * vstart: start address to map 217 * vend: end address to map - we map [vstart, vend] 218 * flags: flags to use to map last level entries 219 * phys: physical address corresponding to vstart - physical memory is contiguous 220 * pgds: the number of pgd entries 221 * 222 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 223 * Preserves: vstart, vend, flags 224 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv 225 */ 226 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv 227 add \rtbl, \tbl, #PAGE_SIZE 228 mov \sv, \rtbl 229 mov \count, #0 230 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count 231 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 232 mov \tbl, \sv 233 mov \sv, \rtbl 234 235#if SWAPPER_PGTABLE_LEVELS > 3 236 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count 237 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 238 mov \tbl, \sv 239 mov \sv, \rtbl 240#endif 241 242#if SWAPPER_PGTABLE_LEVELS > 2 243 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count 244 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 245 mov \tbl, \sv 246#endif 247 248 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count 249 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 250 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 251 .endm 252 253/* 254 * Setup the initial page tables. We only setup the barest amount which is 255 * required to get the kernel running. The following sections are required: 256 * - identity mapping to enable the MMU (low address, TTBR0) 257 * - first few MB of the kernel linear mapping to jump to once the MMU has 258 * been enabled 259 */ 260SYM_FUNC_START_LOCAL(__create_page_tables) 261 mov x28, lr 262 263 /* 264 * Invalidate the init page tables to avoid potential dirty cache lines 265 * being evicted. Other page tables are allocated in rodata as part of 266 * the kernel image, and thus are clean to the PoC per the boot 267 * protocol. 268 */ 269 adrp x0, init_pg_dir 270 adrp x1, init_pg_end 271 sub x1, x1, x0 272 bl __inval_dcache_area 273 274 /* 275 * Clear the init page tables. 276 */ 277 adrp x0, init_pg_dir 278 adrp x1, init_pg_end 279 sub x1, x1, x0 2801: stp xzr, xzr, [x0], #16 281 stp xzr, xzr, [x0], #16 282 stp xzr, xzr, [x0], #16 283 stp xzr, xzr, [x0], #16 284 subs x1, x1, #64 285 b.ne 1b 286 287 mov x7, SWAPPER_MM_MMUFLAGS 288 289 /* 290 * Create the identity mapping. 291 */ 292 adrp x0, idmap_pg_dir 293 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 294 295#ifdef CONFIG_ARM64_VA_BITS_52 296 mrs_s x6, SYS_ID_AA64MMFR2_EL1 297 and x6, x6, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 298 mov x5, #52 299 cbnz x6, 1f 300#endif 301 mov x5, #VA_BITS_MIN 3021: 303 adr_l x6, vabits_actual 304 str x5, [x6] 305 dmb sy 306 dc ivac, x6 // Invalidate potentially stale cache line 307 308 /* 309 * VA_BITS may be too small to allow for an ID mapping to be created 310 * that covers system RAM if that is located sufficiently high in the 311 * physical address space. So for the ID map, use an extended virtual 312 * range in that case, and configure an additional translation level 313 * if needed. 314 * 315 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 316 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 317 * this number conveniently equals the number of leading zeroes in 318 * the physical address of __idmap_text_end. 319 */ 320 adrp x5, __idmap_text_end 321 clz x5, x5 322 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 323 b.ge 1f // .. then skip VA range extension 324 325 adr_l x6, idmap_t0sz 326 str x5, [x6] 327 dmb sy 328 dc ivac, x6 // Invalidate potentially stale cache line 329 330#if (VA_BITS < 48) 331#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 332#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) 333 334 /* 335 * If VA_BITS < 48, we have to configure an additional table level. 336 * First, we have to verify our assumption that the current value of 337 * VA_BITS was chosen such that all translation levels are fully 338 * utilised, and that lowering T0SZ will always result in an additional 339 * translation level to be configured. 340 */ 341#if VA_BITS != EXTRA_SHIFT 342#error "Mismatch between VA_BITS and page size/number of translation levels" 343#endif 344 345 mov x4, EXTRA_PTRS 346 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 347#else 348 /* 349 * If VA_BITS == 48, we don't have to configure an additional 350 * translation level, but the top-level table has more entries. 351 */ 352 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) 353 str_l x4, idmap_ptrs_per_pgd, x5 354#endif 3551: 356 ldr_l x4, idmap_ptrs_per_pgd 357 mov x5, x3 // __pa(__idmap_text_start) 358 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 359 360 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 361 362 /* 363 * Map the kernel image (starting with PHYS_OFFSET). 364 */ 365 adrp x0, init_pg_dir 366 mov_q x5, KIMAGE_VADDR // compile time __va(_text) 367 add x5, x5, x23 // add KASLR displacement 368 mov x4, PTRS_PER_PGD 369 adrp x6, _end // runtime __pa(_end) 370 adrp x3, _text // runtime __pa(_text) 371 sub x6, x6, x3 // _end - _text 372 add x6, x6, x5 // runtime __va(_end) 373 374 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14 375 376 /* 377 * Since the page tables have been populated with non-cacheable 378 * accesses (MMU disabled), invalidate those tables again to 379 * remove any speculatively loaded cache lines. 380 */ 381 dmb sy 382 383 adrp x0, idmap_pg_dir 384 adrp x1, idmap_pg_end 385 sub x1, x1, x0 386 bl __inval_dcache_area 387 388 adrp x0, init_pg_dir 389 adrp x1, init_pg_end 390 sub x1, x1, x0 391 bl __inval_dcache_area 392 393 ret x28 394SYM_FUNC_END(__create_page_tables) 395 396/* 397 * The following fragment of code is executed with the MMU enabled. 398 * 399 * x0 = __PHYS_OFFSET 400 */ 401SYM_FUNC_START_LOCAL(__primary_switched) 402 adrp x4, init_thread_union 403 add sp, x4, #THREAD_SIZE 404 adr_l x5, init_task 405 msr sp_el0, x5 // Save thread_info 406 407#ifdef CONFIG_ARM64_PTR_AUTH 408 __ptrauth_keys_init_cpu x5, x6, x7, x8 409#endif 410 411 adr_l x8, vectors // load VBAR_EL1 with virtual 412 msr vbar_el1, x8 // vector table address 413 isb 414 415 stp xzr, x30, [sp, #-16]! 416 mov x29, sp 417 418#ifdef CONFIG_SHADOW_CALL_STACK 419 adr_l scs_sp, init_shadow_call_stack // Set shadow call stack 420#endif 421 422 str_l x21, __fdt_pointer, x5 // Save FDT pointer 423 424 ldr_l x4, kimage_vaddr // Save the offset between 425 sub x4, x4, x0 // the kernel virtual and 426 str_l x4, kimage_voffset, x5 // physical mappings 427 428 // Clear BSS 429 adr_l x0, __bss_start 430 mov x1, xzr 431 adr_l x2, __bss_stop 432 sub x2, x2, x0 433 bl __pi_memset 434 dsb ishst // Make zero page visible to PTW 435 436#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 437 bl kasan_early_init 438#endif 439#ifdef CONFIG_RANDOMIZE_BASE 440 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 441 b.ne 0f 442 mov x0, x21 // pass FDT address in x0 443 bl kaslr_early_init // parse FDT for KASLR options 444 cbz x0, 0f // KASLR disabled? just proceed 445 orr x23, x23, x0 // record KASLR offset 446 ldp x29, x30, [sp], #16 // we must enable KASLR, return 447 ret // to __primary_switch() 4480: 449#endif 450 add sp, sp, #16 451 mov x29, #0 452 mov x30, #0 453 b start_kernel 454SYM_FUNC_END(__primary_switched) 455 456 .pushsection ".rodata", "a" 457SYM_DATA_START(kimage_vaddr) 458 .quad _text 459SYM_DATA_END(kimage_vaddr) 460EXPORT_SYMBOL(kimage_vaddr) 461 .popsection 462 463/* 464 * end early head section, begin head code that is also used for 465 * hotplug and needs to have the same protections as the text region 466 */ 467 .section ".idmap.text","awx" 468 469/* 470 * Starting from EL2 or EL1, configure the CPU to execute at the highest 471 * reachable EL supported by the kernel in a chosen default state. If dropping 472 * from EL2 to EL1, configure EL2 before configuring EL1. 473 * 474 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if 475 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET. 476 * 477 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 478 * booted in EL1 or EL2 respectively. 479 */ 480SYM_FUNC_START(init_kernel_el) 481 mrs x0, CurrentEL 482 cmp x0, #CurrentEL_EL2 483 b.eq init_el2 484 485SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) 486 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 487 msr sctlr_el1, x0 488 isb 489 mov_q x0, INIT_PSTATE_EL1 490 msr spsr_el1, x0 491 msr elr_el1, lr 492 mov w0, #BOOT_CPU_MODE_EL1 493 eret 494 495SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) 496#ifdef CONFIG_ARM64_VHE 497 /* 498 * Check for VHE being present. x2 being non-zero indicates that we 499 * do have VHE, and that the kernel is intended to run at EL2. 500 */ 501 mrs x2, id_aa64mmfr1_el1 502 ubfx x2, x2, #ID_AA64MMFR1_VHE_SHIFT, #4 503#else 504 mov x2, xzr 505#endif 506 cbz x2, init_el2_nvhe 507 508 /* 509 * When VHE _is_ in use, EL1 will not be used in the host and 510 * requires no configuration, and all non-hyp-specific EL2 setup 511 * will be done via the _EL1 system register aliases in __cpu_setup. 512 */ 513 mov_q x0, HCR_HOST_VHE_FLAGS 514 msr hcr_el2, x0 515 isb 516 517 init_el2_state vhe 518 519 isb 520 521 mov_q x0, INIT_PSTATE_EL2 522 msr spsr_el2, x0 523 msr elr_el2, lr 524 mov w0, #BOOT_CPU_MODE_EL2 525 eret 526 527SYM_INNER_LABEL(init_el2_nvhe, SYM_L_LOCAL) 528 /* 529 * When VHE is not in use, early init of EL2 and EL1 needs to be 530 * done here. 531 */ 532 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 533 msr sctlr_el1, x0 534 535 mov_q x0, HCR_HOST_NVHE_FLAGS 536 msr hcr_el2, x0 537 isb 538 539 init_el2_state nvhe 540 541 /* Hypervisor stub */ 542 adr_l x0, __hyp_stub_vectors 543 msr vbar_el2, x0 544 isb 545 546 msr elr_el2, lr 547 mov w0, #BOOT_CPU_MODE_EL2 548 eret 549SYM_FUNC_END(init_kernel_el) 550 551/* 552 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 553 * in w0. See arch/arm64/include/asm/virt.h for more info. 554 */ 555SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag) 556 adr_l x1, __boot_cpu_mode 557 cmp w0, #BOOT_CPU_MODE_EL2 558 b.ne 1f 559 add x1, x1, #4 5601: str w0, [x1] // This CPU has booted in EL1 561 dmb sy 562 dc ivac, x1 // Invalidate potentially stale cache line 563 ret 564SYM_FUNC_END(set_cpu_boot_mode_flag) 565 566/* 567 * These values are written with the MMU off, but read with the MMU on. 568 * Writers will invalidate the corresponding address, discarding up to a 569 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 570 * sufficient alignment that the CWG doesn't overlap another section. 571 */ 572 .pushsection ".mmuoff.data.write", "aw" 573/* 574 * We need to find out the CPU boot mode long after boot, so we need to 575 * store it in a writable variable. 576 * 577 * This is not in .bss, because we set it sufficiently early that the boot-time 578 * zeroing of .bss would clobber it. 579 */ 580SYM_DATA_START(__boot_cpu_mode) 581 .long BOOT_CPU_MODE_EL2 582 .long BOOT_CPU_MODE_EL1 583SYM_DATA_END(__boot_cpu_mode) 584/* 585 * The booting CPU updates the failed status @__early_cpu_boot_status, 586 * with MMU turned off. 587 */ 588SYM_DATA_START(__early_cpu_boot_status) 589 .quad 0 590SYM_DATA_END(__early_cpu_boot_status) 591 592 .popsection 593 594 /* 595 * This provides a "holding pen" for platforms to hold all secondary 596 * cores are held until we're ready for them to initialise. 597 */ 598SYM_FUNC_START(secondary_holding_pen) 599 bl init_kernel_el // w0=cpu_boot_mode 600 bl set_cpu_boot_mode_flag 601 mrs x0, mpidr_el1 602 mov_q x1, MPIDR_HWID_BITMASK 603 and x0, x0, x1 604 adr_l x3, secondary_holding_pen_release 605pen: ldr x4, [x3] 606 cmp x4, x0 607 b.eq secondary_startup 608 wfe 609 b pen 610SYM_FUNC_END(secondary_holding_pen) 611 612 /* 613 * Secondary entry point that jumps straight into the kernel. Only to 614 * be used where CPUs are brought online dynamically by the kernel. 615 */ 616SYM_FUNC_START(secondary_entry) 617 bl init_kernel_el // w0=cpu_boot_mode 618 bl set_cpu_boot_mode_flag 619 b secondary_startup 620SYM_FUNC_END(secondary_entry) 621 622SYM_FUNC_START_LOCAL(secondary_startup) 623 /* 624 * Common entry point for secondary CPUs. 625 */ 626 bl __cpu_secondary_check52bitva 627 bl __cpu_setup // initialise processor 628 adrp x1, swapper_pg_dir 629 bl __enable_mmu 630 ldr x8, =__secondary_switched 631 br x8 632SYM_FUNC_END(secondary_startup) 633 634SYM_FUNC_START_LOCAL(__secondary_switched) 635 adr_l x5, vectors 636 msr vbar_el1, x5 637 isb 638 639 adr_l x0, secondary_data 640 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 641 cbz x1, __secondary_too_slow 642 mov sp, x1 643 ldr x2, [x0, #CPU_BOOT_TASK] 644 cbz x2, __secondary_too_slow 645 msr sp_el0, x2 646 scs_load x2, x3 647 mov x29, #0 648 mov x30, #0 649 650#ifdef CONFIG_ARM64_PTR_AUTH 651 ptrauth_keys_init_cpu x2, x3, x4, x5 652#endif 653 654 b secondary_start_kernel 655SYM_FUNC_END(__secondary_switched) 656 657SYM_FUNC_START_LOCAL(__secondary_too_slow) 658 wfe 659 wfi 660 b __secondary_too_slow 661SYM_FUNC_END(__secondary_too_slow) 662 663/* 664 * The booting CPU updates the failed status @__early_cpu_boot_status, 665 * with MMU turned off. 666 * 667 * update_early_cpu_boot_status tmp, status 668 * - Corrupts tmp1, tmp2 669 * - Writes 'status' to __early_cpu_boot_status and makes sure 670 * it is committed to memory. 671 */ 672 673 .macro update_early_cpu_boot_status status, tmp1, tmp2 674 mov \tmp2, #\status 675 adr_l \tmp1, __early_cpu_boot_status 676 str \tmp2, [\tmp1] 677 dmb sy 678 dc ivac, \tmp1 // Invalidate potentially stale cache line 679 .endm 680 681/* 682 * Enable the MMU. 683 * 684 * x0 = SCTLR_EL1 value for turning on the MMU. 685 * x1 = TTBR1_EL1 value 686 * 687 * Returns to the caller via x30/lr. This requires the caller to be covered 688 * by the .idmap.text section. 689 * 690 * Checks if the selected granule size is supported by the CPU. 691 * If it isn't, park the CPU 692 */ 693SYM_FUNC_START(__enable_mmu) 694 mrs x2, ID_AA64MMFR0_EL1 695 ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 696 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED 697 b.ne __no_granule_support 698 update_early_cpu_boot_status 0, x2, x3 699 adrp x2, idmap_pg_dir 700 phys_to_ttbr x1, x1 701 phys_to_ttbr x2, x2 702 msr ttbr0_el1, x2 // load TTBR0 703 offset_ttbr1 x1, x3 704 msr ttbr1_el1, x1 // load TTBR1 705 isb 706 msr sctlr_el1, x0 707 isb 708 /* 709 * Invalidate the local I-cache so that any instructions fetched 710 * speculatively from the PoC are discarded, since they may have 711 * been dynamically patched at the PoU. 712 */ 713 ic iallu 714 dsb nsh 715 isb 716 ret 717SYM_FUNC_END(__enable_mmu) 718 719SYM_FUNC_START(__cpu_secondary_check52bitva) 720#ifdef CONFIG_ARM64_VA_BITS_52 721 ldr_l x0, vabits_actual 722 cmp x0, #52 723 b.ne 2f 724 725 mrs_s x0, SYS_ID_AA64MMFR2_EL1 726 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 727 cbnz x0, 2f 728 729 update_early_cpu_boot_status \ 730 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 7311: wfe 732 wfi 733 b 1b 734 735#endif 7362: ret 737SYM_FUNC_END(__cpu_secondary_check52bitva) 738 739SYM_FUNC_START_LOCAL(__no_granule_support) 740 /* Indicate that this CPU can't boot and is stuck in the kernel */ 741 update_early_cpu_boot_status \ 742 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 7431: 744 wfe 745 wfi 746 b 1b 747SYM_FUNC_END(__no_granule_support) 748 749#ifdef CONFIG_RELOCATABLE 750SYM_FUNC_START_LOCAL(__relocate_kernel) 751 /* 752 * Iterate over each entry in the relocation table, and apply the 753 * relocations in place. 754 */ 755 ldr w9, =__rela_offset // offset to reloc table 756 ldr w10, =__rela_size // size of reloc table 757 758 mov_q x11, KIMAGE_VADDR // default virtual offset 759 add x11, x11, x23 // actual virtual offset 760 add x9, x9, x11 // __va(.rela) 761 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 762 7630: cmp x9, x10 764 b.hs 1f 765 ldp x12, x13, [x9], #24 766 ldr x14, [x9, #-8] 767 cmp w13, #R_AARCH64_RELATIVE 768 b.ne 0b 769 add x14, x14, x23 // relocate 770 str x14, [x12, x23] 771 b 0b 772 7731: 774#ifdef CONFIG_RELR 775 /* 776 * Apply RELR relocations. 777 * 778 * RELR is a compressed format for storing relative relocations. The 779 * encoded sequence of entries looks like: 780 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] 781 * 782 * i.e. start with an address, followed by any number of bitmaps. The 783 * address entry encodes 1 relocation. The subsequent bitmap entries 784 * encode up to 63 relocations each, at subsequent offsets following 785 * the last address entry. 786 * 787 * The bitmap entries must have 1 in the least significant bit. The 788 * assumption here is that an address cannot have 1 in lsb. Odd 789 * addresses are not supported. Any odd addresses are stored in the RELA 790 * section, which is handled above. 791 * 792 * Excluding the least significant bit in the bitmap, each non-zero 793 * bit in the bitmap represents a relocation to be applied to 794 * a corresponding machine word that follows the base address 795 * word. The second least significant bit represents the machine 796 * word immediately following the initial address, and each bit 797 * that follows represents the next word, in linear order. As such, 798 * a single bitmap can encode up to 63 relocations in a 64-bit object. 799 * 800 * In this implementation we store the address of the next RELR table 801 * entry in x9, the address being relocated by the current address or 802 * bitmap entry in x13 and the address being relocated by the current 803 * bit in x14. 804 * 805 * Because addends are stored in place in the binary, RELR relocations 806 * cannot be applied idempotently. We use x24 to keep track of the 807 * currently applied displacement so that we can correctly relocate if 808 * __relocate_kernel is called twice with non-zero displacements (i.e. 809 * if there is both a physical misalignment and a KASLR displacement). 810 */ 811 ldr w9, =__relr_offset // offset to reloc table 812 ldr w10, =__relr_size // size of reloc table 813 add x9, x9, x11 // __va(.relr) 814 add x10, x9, x10 // __va(.relr) + sizeof(.relr) 815 816 sub x15, x23, x24 // delta from previous offset 817 cbz x15, 7f // nothing to do if unchanged 818 mov x24, x23 // save new offset 819 8202: cmp x9, x10 821 b.hs 7f 822 ldr x11, [x9], #8 823 tbnz x11, #0, 3f // branch to handle bitmaps 824 add x13, x11, x23 825 ldr x12, [x13] // relocate address entry 826 add x12, x12, x15 827 str x12, [x13], #8 // adjust to start of bitmap 828 b 2b 829 8303: mov x14, x13 8314: lsr x11, x11, #1 832 cbz x11, 6f 833 tbz x11, #0, 5f // skip bit if not set 834 ldr x12, [x14] // relocate bit 835 add x12, x12, x15 836 str x12, [x14] 837 8385: add x14, x14, #8 // move to next bit's address 839 b 4b 840 8416: /* 842 * Move to the next bitmap's address. 8 is the word size, and 63 is the 843 * number of significant bits in a bitmap entry. 844 */ 845 add x13, x13, #(8 * 63) 846 b 2b 847 8487: 849#endif 850 ret 851 852SYM_FUNC_END(__relocate_kernel) 853#endif 854 855SYM_FUNC_START_LOCAL(__primary_switch) 856#ifdef CONFIG_RANDOMIZE_BASE 857 mov x19, x0 // preserve new SCTLR_EL1 value 858 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 859#endif 860 861 adrp x1, init_pg_dir 862 bl __enable_mmu 863#ifdef CONFIG_RELOCATABLE 864#ifdef CONFIG_RELR 865 mov x24, #0 // no RELR displacement yet 866#endif 867 bl __relocate_kernel 868#ifdef CONFIG_RANDOMIZE_BASE 869 ldr x8, =__primary_switched 870 adrp x0, __PHYS_OFFSET 871 blr x8 872 873 /* 874 * If we return here, we have a KASLR displacement in x23 which we need 875 * to take into account by discarding the current kernel mapping and 876 * creating a new one. 877 */ 878 pre_disable_mmu_workaround 879 msr sctlr_el1, x20 // disable the MMU 880 isb 881 bl __create_page_tables // recreate kernel mapping 882 883 tlbi vmalle1 // Remove any stale TLB entries 884 dsb nsh 885 886 msr sctlr_el1, x19 // re-enable the MMU 887 isb 888 ic iallu // flush instructions fetched 889 dsb nsh // via old mapping 890 isb 891 892 bl __relocate_kernel 893#endif 894#endif 895 ldr x8, =__primary_switched 896 adrp x0, __PHYS_OFFSET 897 br x8 898SYM_FUNC_END(__primary_switch) 899