1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FP/SIMD context switching and fault handling 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/bottom_half.h> 12 #include <linux/bug.h> 13 #include <linux/cache.h> 14 #include <linux/compat.h> 15 #include <linux/compiler.h> 16 #include <linux/cpu.h> 17 #include <linux/cpu_pm.h> 18 #include <linux/ctype.h> 19 #include <linux/kernel.h> 20 #include <linux/linkage.h> 21 #include <linux/irqflags.h> 22 #include <linux/init.h> 23 #include <linux/percpu.h> 24 #include <linux/prctl.h> 25 #include <linux/preempt.h> 26 #include <linux/ptrace.h> 27 #include <linux/sched/signal.h> 28 #include <linux/sched/task_stack.h> 29 #include <linux/signal.h> 30 #include <linux/slab.h> 31 #include <linux/stddef.h> 32 #include <linux/sysctl.h> 33 #include <linux/swab.h> 34 35 #include <asm/esr.h> 36 #include <asm/exception.h> 37 #include <asm/fpsimd.h> 38 #include <asm/cpufeature.h> 39 #include <asm/cputype.h> 40 #include <asm/neon.h> 41 #include <asm/processor.h> 42 #include <asm/simd.h> 43 #include <asm/sigcontext.h> 44 #include <asm/sysreg.h> 45 #include <asm/traps.h> 46 #include <asm/virt.h> 47 48 #define FPEXC_IOF (1 << 0) 49 #define FPEXC_DZF (1 << 1) 50 #define FPEXC_OFF (1 << 2) 51 #define FPEXC_UFF (1 << 3) 52 #define FPEXC_IXF (1 << 4) 53 #define FPEXC_IDF (1 << 7) 54 55 /* 56 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.) 57 * 58 * In order to reduce the number of times the FPSIMD state is needlessly saved 59 * and restored, we need to keep track of two things: 60 * (a) for each task, we need to remember which CPU was the last one to have 61 * the task's FPSIMD state loaded into its FPSIMD registers; 62 * (b) for each CPU, we need to remember which task's userland FPSIMD state has 63 * been loaded into its FPSIMD registers most recently, or whether it has 64 * been used to perform kernel mode NEON in the meantime. 65 * 66 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to 67 * the id of the current CPU every time the state is loaded onto a CPU. For (b), 68 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the 69 * address of the userland FPSIMD state of the task that was loaded onto the CPU 70 * the most recently, or NULL if kernel mode NEON has been performed after that. 71 * 72 * With this in place, we no longer have to restore the next FPSIMD state right 73 * when switching between tasks. Instead, we can defer this check to userland 74 * resume, at which time we verify whether the CPU's fpsimd_last_state and the 75 * task's fpsimd_cpu are still mutually in sync. If this is the case, we 76 * can omit the FPSIMD restore. 77 * 78 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to 79 * indicate whether or not the userland FPSIMD state of the current task is 80 * present in the registers. The flag is set unless the FPSIMD registers of this 81 * CPU currently contain the most recent userland FPSIMD state of the current 82 * task. If the task is behaving as a VMM, then this is will be managed by 83 * KVM which will clear it to indicate that the vcpu FPSIMD state is currently 84 * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware 85 * softirq kicks in. Upon vcpu_put(), KVM will save the vcpu FP state and 86 * flag the register state as invalid. 87 * 88 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may 89 * save the task's FPSIMD context back to task_struct from softirq context. 90 * To prevent this from racing with the manipulation of the task's FPSIMD state 91 * from task context and thereby corrupting the state, it is necessary to 92 * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE 93 * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to 94 * run but prevent them to use FPSIMD. 95 * 96 * For a certain task, the sequence may look something like this: 97 * - the task gets scheduled in; if both the task's fpsimd_cpu field 98 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu 99 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is 100 * cleared, otherwise it is set; 101 * 102 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's 103 * userland FPSIMD state is copied from memory to the registers, the task's 104 * fpsimd_cpu field is set to the id of the current CPU, the current 105 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the 106 * TIF_FOREIGN_FPSTATE flag is cleared; 107 * 108 * - the task executes an ordinary syscall; upon return to userland, the 109 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is 110 * restored; 111 * 112 * - the task executes a syscall which executes some NEON instructions; this is 113 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD 114 * register contents to memory, clears the fpsimd_last_state per-cpu variable 115 * and sets the TIF_FOREIGN_FPSTATE flag; 116 * 117 * - the task gets preempted after kernel_neon_end() is called; as we have not 118 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so 119 * whatever is in the FPSIMD registers is not saved to memory, but discarded. 120 */ 121 122 static DEFINE_PER_CPU(struct cpu_fp_state, fpsimd_last_state); 123 124 __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = { 125 #ifdef CONFIG_ARM64_SVE 126 [ARM64_VEC_SVE] = { 127 .type = ARM64_VEC_SVE, 128 .name = "SVE", 129 .min_vl = SVE_VL_MIN, 130 .max_vl = SVE_VL_MIN, 131 .max_virtualisable_vl = SVE_VL_MIN, 132 }, 133 #endif 134 #ifdef CONFIG_ARM64_SME 135 [ARM64_VEC_SME] = { 136 .type = ARM64_VEC_SME, 137 .name = "SME", 138 }, 139 #endif 140 }; 141 142 static unsigned int vec_vl_inherit_flag(enum vec_type type) 143 { 144 switch (type) { 145 case ARM64_VEC_SVE: 146 return TIF_SVE_VL_INHERIT; 147 case ARM64_VEC_SME: 148 return TIF_SME_VL_INHERIT; 149 default: 150 WARN_ON_ONCE(1); 151 return 0; 152 } 153 } 154 155 struct vl_config { 156 int __default_vl; /* Default VL for tasks */ 157 }; 158 159 static struct vl_config vl_config[ARM64_VEC_MAX]; 160 161 static inline int get_default_vl(enum vec_type type) 162 { 163 return READ_ONCE(vl_config[type].__default_vl); 164 } 165 166 #ifdef CONFIG_ARM64_SVE 167 168 static inline int get_sve_default_vl(void) 169 { 170 return get_default_vl(ARM64_VEC_SVE); 171 } 172 173 static inline void set_default_vl(enum vec_type type, int val) 174 { 175 WRITE_ONCE(vl_config[type].__default_vl, val); 176 } 177 178 static inline void set_sve_default_vl(int val) 179 { 180 set_default_vl(ARM64_VEC_SVE, val); 181 } 182 183 static void __percpu *efi_sve_state; 184 185 #else /* ! CONFIG_ARM64_SVE */ 186 187 /* Dummy declaration for code that will be optimised out: */ 188 extern void __percpu *efi_sve_state; 189 190 #endif /* ! CONFIG_ARM64_SVE */ 191 192 #ifdef CONFIG_ARM64_SME 193 194 static int get_sme_default_vl(void) 195 { 196 return get_default_vl(ARM64_VEC_SME); 197 } 198 199 static void set_sme_default_vl(int val) 200 { 201 set_default_vl(ARM64_VEC_SME, val); 202 } 203 204 static void sme_free(struct task_struct *); 205 206 #else 207 208 static inline void sme_free(struct task_struct *t) { } 209 210 #endif 211 212 DEFINE_PER_CPU(bool, fpsimd_context_busy); 213 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy); 214 215 static void fpsimd_bind_task_to_cpu(void); 216 217 static void __get_cpu_fpsimd_context(void) 218 { 219 bool busy = __this_cpu_xchg(fpsimd_context_busy, true); 220 221 WARN_ON(busy); 222 } 223 224 /* 225 * Claim ownership of the CPU FPSIMD context for use by the calling context. 226 * 227 * The caller may freely manipulate the FPSIMD context metadata until 228 * put_cpu_fpsimd_context() is called. 229 * 230 * The double-underscore version must only be called if you know the task 231 * can't be preempted. 232 * 233 * On RT kernels local_bh_disable() is not sufficient because it only 234 * serializes soft interrupt related sections via a local lock, but stays 235 * preemptible. Disabling preemption is the right choice here as bottom 236 * half processing is always in thread context on RT kernels so it 237 * implicitly prevents bottom half processing as well. 238 */ 239 static void get_cpu_fpsimd_context(void) 240 { 241 if (!IS_ENABLED(CONFIG_PREEMPT_RT)) 242 local_bh_disable(); 243 else 244 preempt_disable(); 245 __get_cpu_fpsimd_context(); 246 } 247 248 static void __put_cpu_fpsimd_context(void) 249 { 250 bool busy = __this_cpu_xchg(fpsimd_context_busy, false); 251 252 WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */ 253 } 254 255 /* 256 * Release the CPU FPSIMD context. 257 * 258 * Must be called from a context in which get_cpu_fpsimd_context() was 259 * previously called, with no call to put_cpu_fpsimd_context() in the 260 * meantime. 261 */ 262 static void put_cpu_fpsimd_context(void) 263 { 264 __put_cpu_fpsimd_context(); 265 if (!IS_ENABLED(CONFIG_PREEMPT_RT)) 266 local_bh_enable(); 267 else 268 preempt_enable(); 269 } 270 271 static bool have_cpu_fpsimd_context(void) 272 { 273 return !preemptible() && __this_cpu_read(fpsimd_context_busy); 274 } 275 276 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type) 277 { 278 return task->thread.vl[type]; 279 } 280 281 void task_set_vl(struct task_struct *task, enum vec_type type, 282 unsigned long vl) 283 { 284 task->thread.vl[type] = vl; 285 } 286 287 unsigned int task_get_vl_onexec(const struct task_struct *task, 288 enum vec_type type) 289 { 290 return task->thread.vl_onexec[type]; 291 } 292 293 void task_set_vl_onexec(struct task_struct *task, enum vec_type type, 294 unsigned long vl) 295 { 296 task->thread.vl_onexec[type] = vl; 297 } 298 299 /* 300 * TIF_SME controls whether a task can use SME without trapping while 301 * in userspace, when TIF_SME is set then we must have storage 302 * alocated in sve_state and za_state to store the contents of both ZA 303 * and the SVE registers for both streaming and non-streaming modes. 304 * 305 * If both SVCR.ZA and SVCR.SM are disabled then at any point we 306 * may disable TIF_SME and reenable traps. 307 */ 308 309 310 /* 311 * TIF_SVE controls whether a task can use SVE without trapping while 312 * in userspace, and also (together with TIF_SME) the way a task's 313 * FPSIMD/SVE state is stored in thread_struct. 314 * 315 * The kernel uses this flag to track whether a user task is actively 316 * using SVE, and therefore whether full SVE register state needs to 317 * be tracked. If not, the cheaper FPSIMD context handling code can 318 * be used instead of the more costly SVE equivalents. 319 * 320 * * TIF_SVE or SVCR.SM set: 321 * 322 * The task can execute SVE instructions while in userspace without 323 * trapping to the kernel. 324 * 325 * During any syscall, the kernel may optionally clear TIF_SVE and 326 * discard the vector state except for the FPSIMD subset. 327 * 328 * * TIF_SVE clear: 329 * 330 * An attempt by the user task to execute an SVE instruction causes 331 * do_sve_acc() to be called, which does some preparation and then 332 * sets TIF_SVE. 333 * 334 * During any syscall, the kernel may optionally clear TIF_SVE and 335 * discard the vector state except for the FPSIMD subset. 336 * 337 * The data will be stored in one of two formats: 338 * 339 * * FPSIMD only - FP_STATE_FPSIMD: 340 * 341 * When the FPSIMD only state stored task->thread.fp_type is set to 342 * FP_STATE_FPSIMD, the FPSIMD registers V0-V31 are encoded in 343 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are 344 * logically zero but not stored anywhere; P0-P15 and FFR are not 345 * stored and have unspecified values from userspace's point of 346 * view. For hygiene purposes, the kernel zeroes them on next use, 347 * but userspace is discouraged from relying on this. 348 * 349 * task->thread.sve_state does not need to be non-NULL, valid or any 350 * particular size: it must not be dereferenced and any data stored 351 * there should be considered stale and not referenced. 352 * 353 * * SVE state - FP_STATE_SVE: 354 * 355 * When the full SVE state is stored task->thread.fp_type is set to 356 * FP_STATE_SVE and Z0-Z31 (incorporating Vn in bits[127:0] or the 357 * corresponding Zn), P0-P15 and FFR are encoded in in 358 * task->thread.sve_state, formatted appropriately for vector 359 * length task->thread.sve_vl or, if SVCR.SM is set, 360 * task->thread.sme_vl. The storage for the vector registers in 361 * task->thread.uw.fpsimd_state should be ignored. 362 * 363 * task->thread.sve_state must point to a valid buffer at least 364 * sve_state_size(task) bytes in size. The data stored in 365 * task->thread.uw.fpsimd_state.vregs should be considered stale 366 * and not referenced. 367 * 368 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state 369 * irrespective of whether TIF_SVE is clear or set, since these are 370 * not vector length dependent. 371 */ 372 373 /* 374 * Update current's FPSIMD/SVE registers from thread_struct. 375 * 376 * This function should be called only when the FPSIMD/SVE state in 377 * thread_struct is known to be up to date, when preparing to enter 378 * userspace. 379 */ 380 static void task_fpsimd_load(void) 381 { 382 bool restore_sve_regs = false; 383 bool restore_ffr; 384 385 WARN_ON(!system_supports_fpsimd()); 386 WARN_ON(!have_cpu_fpsimd_context()); 387 388 if (system_supports_sve()) { 389 switch (current->thread.fp_type) { 390 case FP_STATE_FPSIMD: 391 /* Stop tracking SVE for this task until next use. */ 392 if (test_and_clear_thread_flag(TIF_SVE)) 393 sve_user_disable(); 394 break; 395 case FP_STATE_SVE: 396 if (!thread_sm_enabled(¤t->thread) && 397 !WARN_ON_ONCE(!test_and_set_thread_flag(TIF_SVE))) 398 sve_user_enable(); 399 400 if (test_thread_flag(TIF_SVE)) 401 sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1); 402 403 restore_sve_regs = true; 404 restore_ffr = true; 405 break; 406 default: 407 /* 408 * This indicates either a bug in 409 * fpsimd_save() or memory corruption, we 410 * should always record an explicit format 411 * when we save. We always at least have the 412 * memory allocated for FPSMID registers so 413 * try that and hope for the best. 414 */ 415 WARN_ON_ONCE(1); 416 clear_thread_flag(TIF_SVE); 417 break; 418 } 419 } 420 421 /* Restore SME, override SVE register configuration if needed */ 422 if (system_supports_sme()) { 423 unsigned long sme_vl = task_get_sme_vl(current); 424 425 /* Ensure VL is set up for restoring data */ 426 if (test_thread_flag(TIF_SME)) 427 sme_set_vq(sve_vq_from_vl(sme_vl) - 1); 428 429 write_sysreg_s(current->thread.svcr, SYS_SVCR); 430 431 if (thread_za_enabled(¤t->thread)) 432 za_load_state(current->thread.za_state); 433 434 if (thread_sm_enabled(¤t->thread)) 435 restore_ffr = system_supports_fa64(); 436 } 437 438 if (restore_sve_regs) { 439 WARN_ON_ONCE(current->thread.fp_type != FP_STATE_SVE); 440 sve_load_state(sve_pffr(¤t->thread), 441 ¤t->thread.uw.fpsimd_state.fpsr, 442 restore_ffr); 443 } else { 444 WARN_ON_ONCE(current->thread.fp_type != FP_STATE_FPSIMD); 445 fpsimd_load_state(¤t->thread.uw.fpsimd_state); 446 } 447 } 448 449 /* 450 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to 451 * date with respect to the CPU registers. Note carefully that the 452 * current context is the context last bound to the CPU stored in 453 * last, if KVM is involved this may be the guest VM context rather 454 * than the host thread for the VM pointed to by current. This means 455 * that we must always reference the state storage via last rather 456 * than via current, if we are saving KVM state then it will have 457 * ensured that the type of registers to save is set in last->to_save. 458 */ 459 static void fpsimd_save(void) 460 { 461 struct cpu_fp_state const *last = 462 this_cpu_ptr(&fpsimd_last_state); 463 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */ 464 bool save_sve_regs = false; 465 bool save_ffr; 466 unsigned int vl; 467 468 WARN_ON(!system_supports_fpsimd()); 469 WARN_ON(!have_cpu_fpsimd_context()); 470 471 if (test_thread_flag(TIF_FOREIGN_FPSTATE)) 472 return; 473 474 /* 475 * If a task is in a syscall the ABI allows us to only 476 * preserve the state shared with FPSIMD so don't bother 477 * saving the full SVE state in that case. 478 */ 479 if ((last->to_save == FP_STATE_CURRENT && test_thread_flag(TIF_SVE) && 480 !in_syscall(current_pt_regs())) || 481 last->to_save == FP_STATE_SVE) { 482 save_sve_regs = true; 483 save_ffr = true; 484 vl = last->sve_vl; 485 } 486 487 if (system_supports_sme()) { 488 u64 *svcr = last->svcr; 489 490 *svcr = read_sysreg_s(SYS_SVCR); 491 492 if (*svcr & SVCR_ZA_MASK) 493 za_save_state(last->za_state); 494 495 /* If we are in streaming mode override regular SVE. */ 496 if (*svcr & SVCR_SM_MASK) { 497 save_sve_regs = true; 498 save_ffr = system_supports_fa64(); 499 vl = last->sme_vl; 500 } 501 } 502 503 if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) { 504 /* Get the configured VL from RDVL, will account for SM */ 505 if (WARN_ON(sve_get_vl() != vl)) { 506 /* 507 * Can't save the user regs, so current would 508 * re-enter user with corrupt state. 509 * There's no way to recover, so kill it: 510 */ 511 force_signal_inject(SIGKILL, SI_KERNEL, 0, 0); 512 return; 513 } 514 515 sve_save_state((char *)last->sve_state + 516 sve_ffr_offset(vl), 517 &last->st->fpsr, save_ffr); 518 *last->fp_type = FP_STATE_SVE; 519 } else { 520 fpsimd_save_state(last->st); 521 *last->fp_type = FP_STATE_FPSIMD; 522 } 523 } 524 525 /* 526 * All vector length selection from userspace comes through here. 527 * We're on a slow path, so some sanity-checks are included. 528 * If things go wrong there's a bug somewhere, but try to fall back to a 529 * safe choice. 530 */ 531 static unsigned int find_supported_vector_length(enum vec_type type, 532 unsigned int vl) 533 { 534 struct vl_info *info = &vl_info[type]; 535 int bit; 536 int max_vl = info->max_vl; 537 538 if (WARN_ON(!sve_vl_valid(vl))) 539 vl = info->min_vl; 540 541 if (WARN_ON(!sve_vl_valid(max_vl))) 542 max_vl = info->min_vl; 543 544 if (vl > max_vl) 545 vl = max_vl; 546 if (vl < info->min_vl) 547 vl = info->min_vl; 548 549 bit = find_next_bit(info->vq_map, SVE_VQ_MAX, 550 __vq_to_bit(sve_vq_from_vl(vl))); 551 return sve_vl_from_vq(__bit_to_vq(bit)); 552 } 553 554 #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL) 555 556 static int vec_proc_do_default_vl(struct ctl_table *table, int write, 557 void *buffer, size_t *lenp, loff_t *ppos) 558 { 559 struct vl_info *info = table->extra1; 560 enum vec_type type = info->type; 561 int ret; 562 int vl = get_default_vl(type); 563 struct ctl_table tmp_table = { 564 .data = &vl, 565 .maxlen = sizeof(vl), 566 }; 567 568 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos); 569 if (ret || !write) 570 return ret; 571 572 /* Writing -1 has the special meaning "set to max": */ 573 if (vl == -1) 574 vl = info->max_vl; 575 576 if (!sve_vl_valid(vl)) 577 return -EINVAL; 578 579 set_default_vl(type, find_supported_vector_length(type, vl)); 580 return 0; 581 } 582 583 static struct ctl_table sve_default_vl_table[] = { 584 { 585 .procname = "sve_default_vector_length", 586 .mode = 0644, 587 .proc_handler = vec_proc_do_default_vl, 588 .extra1 = &vl_info[ARM64_VEC_SVE], 589 }, 590 { } 591 }; 592 593 static int __init sve_sysctl_init(void) 594 { 595 if (system_supports_sve()) 596 if (!register_sysctl("abi", sve_default_vl_table)) 597 return -EINVAL; 598 599 return 0; 600 } 601 602 #else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 603 static int __init sve_sysctl_init(void) { return 0; } 604 #endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 605 606 #if defined(CONFIG_ARM64_SME) && defined(CONFIG_SYSCTL) 607 static struct ctl_table sme_default_vl_table[] = { 608 { 609 .procname = "sme_default_vector_length", 610 .mode = 0644, 611 .proc_handler = vec_proc_do_default_vl, 612 .extra1 = &vl_info[ARM64_VEC_SME], 613 }, 614 { } 615 }; 616 617 static int __init sme_sysctl_init(void) 618 { 619 if (system_supports_sme()) 620 if (!register_sysctl("abi", sme_default_vl_table)) 621 return -EINVAL; 622 623 return 0; 624 } 625 626 #else /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */ 627 static int __init sme_sysctl_init(void) { return 0; } 628 #endif /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */ 629 630 #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ 631 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) 632 633 #ifdef CONFIG_CPU_BIG_ENDIAN 634 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 635 { 636 u64 a = swab64(x); 637 u64 b = swab64(x >> 64); 638 639 return ((__uint128_t)a << 64) | b; 640 } 641 #else 642 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 643 { 644 return x; 645 } 646 #endif 647 648 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) 649 650 static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst, 651 unsigned int vq) 652 { 653 unsigned int i; 654 __uint128_t *p; 655 656 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 657 p = (__uint128_t *)ZREG(sst, vq, i); 658 *p = arm64_cpu_to_le128(fst->vregs[i]); 659 } 660 } 661 662 /* 663 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to 664 * task->thread.sve_state. 665 * 666 * Task can be a non-runnable task, or current. In the latter case, 667 * the caller must have ownership of the cpu FPSIMD context before calling 668 * this function. 669 * task->thread.sve_state must point to at least sve_state_size(task) 670 * bytes of allocated kernel memory. 671 * task->thread.uw.fpsimd_state must be up to date before calling this 672 * function. 673 */ 674 static void fpsimd_to_sve(struct task_struct *task) 675 { 676 unsigned int vq; 677 void *sst = task->thread.sve_state; 678 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 679 680 if (!system_supports_sve()) 681 return; 682 683 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); 684 __fpsimd_to_sve(sst, fst, vq); 685 } 686 687 /* 688 * Transfer the SVE state in task->thread.sve_state to 689 * task->thread.uw.fpsimd_state. 690 * 691 * Task can be a non-runnable task, or current. In the latter case, 692 * the caller must have ownership of the cpu FPSIMD context before calling 693 * this function. 694 * task->thread.sve_state must point to at least sve_state_size(task) 695 * bytes of allocated kernel memory. 696 * task->thread.sve_state must be up to date before calling this function. 697 */ 698 static void sve_to_fpsimd(struct task_struct *task) 699 { 700 unsigned int vq, vl; 701 void const *sst = task->thread.sve_state; 702 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state; 703 unsigned int i; 704 __uint128_t const *p; 705 706 if (!system_supports_sve()) 707 return; 708 709 vl = thread_get_cur_vl(&task->thread); 710 vq = sve_vq_from_vl(vl); 711 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 712 p = (__uint128_t const *)ZREG(sst, vq, i); 713 fst->vregs[i] = arm64_le128_to_cpu(*p); 714 } 715 } 716 717 #ifdef CONFIG_ARM64_SVE 718 /* 719 * Call __sve_free() directly only if you know task can't be scheduled 720 * or preempted. 721 */ 722 static void __sve_free(struct task_struct *task) 723 { 724 kfree(task->thread.sve_state); 725 task->thread.sve_state = NULL; 726 } 727 728 static void sve_free(struct task_struct *task) 729 { 730 WARN_ON(test_tsk_thread_flag(task, TIF_SVE)); 731 732 __sve_free(task); 733 } 734 735 /* 736 * Return how many bytes of memory are required to store the full SVE 737 * state for task, given task's currently configured vector length. 738 */ 739 size_t sve_state_size(struct task_struct const *task) 740 { 741 unsigned int vl = 0; 742 743 if (system_supports_sve()) 744 vl = task_get_sve_vl(task); 745 if (system_supports_sme()) 746 vl = max(vl, task_get_sme_vl(task)); 747 748 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)); 749 } 750 751 /* 752 * Ensure that task->thread.sve_state is allocated and sufficiently large. 753 * 754 * This function should be used only in preparation for replacing 755 * task->thread.sve_state with new data. The memory is always zeroed 756 * here to prevent stale data from showing through: this is done in 757 * the interest of testability and predictability: except in the 758 * do_sve_acc() case, there is no ABI requirement to hide stale data 759 * written previously be task. 760 */ 761 void sve_alloc(struct task_struct *task, bool flush) 762 { 763 if (task->thread.sve_state) { 764 if (flush) 765 memset(task->thread.sve_state, 0, 766 sve_state_size(task)); 767 return; 768 } 769 770 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */ 771 task->thread.sve_state = 772 kzalloc(sve_state_size(task), GFP_KERNEL); 773 } 774 775 776 /* 777 * Force the FPSIMD state shared with SVE to be updated in the SVE state 778 * even if the SVE state is the current active state. 779 * 780 * This should only be called by ptrace. task must be non-runnable. 781 * task->thread.sve_state must point to at least sve_state_size(task) 782 * bytes of allocated kernel memory. 783 */ 784 void fpsimd_force_sync_to_sve(struct task_struct *task) 785 { 786 fpsimd_to_sve(task); 787 } 788 789 /* 790 * Ensure that task->thread.sve_state is up to date with respect to 791 * the user task, irrespective of when SVE is in use or not. 792 * 793 * This should only be called by ptrace. task must be non-runnable. 794 * task->thread.sve_state must point to at least sve_state_size(task) 795 * bytes of allocated kernel memory. 796 */ 797 void fpsimd_sync_to_sve(struct task_struct *task) 798 { 799 if (!test_tsk_thread_flag(task, TIF_SVE) && 800 !thread_sm_enabled(&task->thread)) 801 fpsimd_to_sve(task); 802 } 803 804 /* 805 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to 806 * the user task, irrespective of whether SVE is in use or not. 807 * 808 * This should only be called by ptrace. task must be non-runnable. 809 * task->thread.sve_state must point to at least sve_state_size(task) 810 * bytes of allocated kernel memory. 811 */ 812 void sve_sync_to_fpsimd(struct task_struct *task) 813 { 814 if (task->thread.fp_type == FP_STATE_SVE) 815 sve_to_fpsimd(task); 816 } 817 818 /* 819 * Ensure that task->thread.sve_state is up to date with respect to 820 * the task->thread.uw.fpsimd_state. 821 * 822 * This should only be called by ptrace to merge new FPSIMD register 823 * values into a task for which SVE is currently active. 824 * task must be non-runnable. 825 * task->thread.sve_state must point to at least sve_state_size(task) 826 * bytes of allocated kernel memory. 827 * task->thread.uw.fpsimd_state must already have been initialised with 828 * the new FPSIMD register values to be merged in. 829 */ 830 void sve_sync_from_fpsimd_zeropad(struct task_struct *task) 831 { 832 unsigned int vq; 833 void *sst = task->thread.sve_state; 834 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 835 836 if (!test_tsk_thread_flag(task, TIF_SVE)) 837 return; 838 839 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); 840 841 memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); 842 __fpsimd_to_sve(sst, fst, vq); 843 } 844 845 int vec_set_vector_length(struct task_struct *task, enum vec_type type, 846 unsigned long vl, unsigned long flags) 847 { 848 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | 849 PR_SVE_SET_VL_ONEXEC)) 850 return -EINVAL; 851 852 if (!sve_vl_valid(vl)) 853 return -EINVAL; 854 855 /* 856 * Clamp to the maximum vector length that VL-agnostic code 857 * can work with. A flag may be assigned in the future to 858 * allow setting of larger vector lengths without confusing 859 * older software. 860 */ 861 if (vl > VL_ARCH_MAX) 862 vl = VL_ARCH_MAX; 863 864 vl = find_supported_vector_length(type, vl); 865 866 if (flags & (PR_SVE_VL_INHERIT | 867 PR_SVE_SET_VL_ONEXEC)) 868 task_set_vl_onexec(task, type, vl); 869 else 870 /* Reset VL to system default on next exec: */ 871 task_set_vl_onexec(task, type, 0); 872 873 /* Only actually set the VL if not deferred: */ 874 if (flags & PR_SVE_SET_VL_ONEXEC) 875 goto out; 876 877 if (vl == task_get_vl(task, type)) 878 goto out; 879 880 /* 881 * To ensure the FPSIMD bits of the SVE vector registers are preserved, 882 * write any live register state back to task_struct, and convert to a 883 * regular FPSIMD thread. 884 */ 885 if (task == current) { 886 get_cpu_fpsimd_context(); 887 888 fpsimd_save(); 889 } 890 891 fpsimd_flush_task_state(task); 892 if (test_and_clear_tsk_thread_flag(task, TIF_SVE) || 893 thread_sm_enabled(&task->thread)) { 894 sve_to_fpsimd(task); 895 task->thread.fp_type = FP_STATE_FPSIMD; 896 } 897 898 if (system_supports_sme() && type == ARM64_VEC_SME) { 899 task->thread.svcr &= ~(SVCR_SM_MASK | 900 SVCR_ZA_MASK); 901 clear_thread_flag(TIF_SME); 902 } 903 904 if (task == current) 905 put_cpu_fpsimd_context(); 906 907 /* 908 * Force reallocation of task SVE and SME state to the correct 909 * size on next use: 910 */ 911 sve_free(task); 912 if (system_supports_sme() && type == ARM64_VEC_SME) 913 sme_free(task); 914 915 task_set_vl(task, type, vl); 916 917 out: 918 update_tsk_thread_flag(task, vec_vl_inherit_flag(type), 919 flags & PR_SVE_VL_INHERIT); 920 921 return 0; 922 } 923 924 /* 925 * Encode the current vector length and flags for return. 926 * This is only required for prctl(): ptrace has separate fields. 927 * SVE and SME use the same bits for _ONEXEC and _INHERIT. 928 * 929 * flags are as for vec_set_vector_length(). 930 */ 931 static int vec_prctl_status(enum vec_type type, unsigned long flags) 932 { 933 int ret; 934 935 if (flags & PR_SVE_SET_VL_ONEXEC) 936 ret = task_get_vl_onexec(current, type); 937 else 938 ret = task_get_vl(current, type); 939 940 if (test_thread_flag(vec_vl_inherit_flag(type))) 941 ret |= PR_SVE_VL_INHERIT; 942 943 return ret; 944 } 945 946 /* PR_SVE_SET_VL */ 947 int sve_set_current_vl(unsigned long arg) 948 { 949 unsigned long vl, flags; 950 int ret; 951 952 vl = arg & PR_SVE_VL_LEN_MASK; 953 flags = arg & ~vl; 954 955 if (!system_supports_sve() || is_compat_task()) 956 return -EINVAL; 957 958 ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags); 959 if (ret) 960 return ret; 961 962 return vec_prctl_status(ARM64_VEC_SVE, flags); 963 } 964 965 /* PR_SVE_GET_VL */ 966 int sve_get_current_vl(void) 967 { 968 if (!system_supports_sve() || is_compat_task()) 969 return -EINVAL; 970 971 return vec_prctl_status(ARM64_VEC_SVE, 0); 972 } 973 974 #ifdef CONFIG_ARM64_SME 975 /* PR_SME_SET_VL */ 976 int sme_set_current_vl(unsigned long arg) 977 { 978 unsigned long vl, flags; 979 int ret; 980 981 vl = arg & PR_SME_VL_LEN_MASK; 982 flags = arg & ~vl; 983 984 if (!system_supports_sme() || is_compat_task()) 985 return -EINVAL; 986 987 ret = vec_set_vector_length(current, ARM64_VEC_SME, vl, flags); 988 if (ret) 989 return ret; 990 991 return vec_prctl_status(ARM64_VEC_SME, flags); 992 } 993 994 /* PR_SME_GET_VL */ 995 int sme_get_current_vl(void) 996 { 997 if (!system_supports_sme() || is_compat_task()) 998 return -EINVAL; 999 1000 return vec_prctl_status(ARM64_VEC_SME, 0); 1001 } 1002 #endif /* CONFIG_ARM64_SME */ 1003 1004 static void vec_probe_vqs(struct vl_info *info, 1005 DECLARE_BITMAP(map, SVE_VQ_MAX)) 1006 { 1007 unsigned int vq, vl; 1008 1009 bitmap_zero(map, SVE_VQ_MAX); 1010 1011 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) { 1012 write_vl(info->type, vq - 1); /* self-syncing */ 1013 1014 switch (info->type) { 1015 case ARM64_VEC_SVE: 1016 vl = sve_get_vl(); 1017 break; 1018 case ARM64_VEC_SME: 1019 vl = sme_get_vl(); 1020 break; 1021 default: 1022 vl = 0; 1023 break; 1024 } 1025 1026 /* Minimum VL identified? */ 1027 if (sve_vq_from_vl(vl) > vq) 1028 break; 1029 1030 vq = sve_vq_from_vl(vl); /* skip intervening lengths */ 1031 set_bit(__vq_to_bit(vq), map); 1032 } 1033 } 1034 1035 /* 1036 * Initialise the set of known supported VQs for the boot CPU. 1037 * This is called during kernel boot, before secondary CPUs are brought up. 1038 */ 1039 void __init vec_init_vq_map(enum vec_type type) 1040 { 1041 struct vl_info *info = &vl_info[type]; 1042 vec_probe_vqs(info, info->vq_map); 1043 bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX); 1044 } 1045 1046 /* 1047 * If we haven't committed to the set of supported VQs yet, filter out 1048 * those not supported by the current CPU. 1049 * This function is called during the bring-up of early secondary CPUs only. 1050 */ 1051 void vec_update_vq_map(enum vec_type type) 1052 { 1053 struct vl_info *info = &vl_info[type]; 1054 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1055 1056 vec_probe_vqs(info, tmp_map); 1057 bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX); 1058 bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map, 1059 SVE_VQ_MAX); 1060 } 1061 1062 /* 1063 * Check whether the current CPU supports all VQs in the committed set. 1064 * This function is called during the bring-up of late secondary CPUs only. 1065 */ 1066 int vec_verify_vq_map(enum vec_type type) 1067 { 1068 struct vl_info *info = &vl_info[type]; 1069 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1070 unsigned long b; 1071 1072 vec_probe_vqs(info, tmp_map); 1073 1074 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 1075 if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) { 1076 pr_warn("%s: cpu%d: Required vector length(s) missing\n", 1077 info->name, smp_processor_id()); 1078 return -EINVAL; 1079 } 1080 1081 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) 1082 return 0; 1083 1084 /* 1085 * For KVM, it is necessary to ensure that this CPU doesn't 1086 * support any vector length that guests may have probed as 1087 * unsupported. 1088 */ 1089 1090 /* Recover the set of supported VQs: */ 1091 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 1092 /* Find VQs supported that are not globally supported: */ 1093 bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX); 1094 1095 /* Find the lowest such VQ, if any: */ 1096 b = find_last_bit(tmp_map, SVE_VQ_MAX); 1097 if (b >= SVE_VQ_MAX) 1098 return 0; /* no mismatches */ 1099 1100 /* 1101 * Mismatches above sve_max_virtualisable_vl are fine, since 1102 * no guest is allowed to configure ZCR_EL2.LEN to exceed this: 1103 */ 1104 if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) { 1105 pr_warn("%s: cpu%d: Unsupported vector length(s) present\n", 1106 info->name, smp_processor_id()); 1107 return -EINVAL; 1108 } 1109 1110 return 0; 1111 } 1112 1113 static void __init sve_efi_setup(void) 1114 { 1115 int max_vl = 0; 1116 int i; 1117 1118 if (!IS_ENABLED(CONFIG_EFI)) 1119 return; 1120 1121 for (i = 0; i < ARRAY_SIZE(vl_info); i++) 1122 max_vl = max(vl_info[i].max_vl, max_vl); 1123 1124 /* 1125 * alloc_percpu() warns and prints a backtrace if this goes wrong. 1126 * This is evidence of a crippled system and we are returning void, 1127 * so no attempt is made to handle this situation here. 1128 */ 1129 if (!sve_vl_valid(max_vl)) 1130 goto fail; 1131 1132 efi_sve_state = __alloc_percpu( 1133 SVE_SIG_REGS_SIZE(sve_vq_from_vl(max_vl)), SVE_VQ_BYTES); 1134 if (!efi_sve_state) 1135 goto fail; 1136 1137 return; 1138 1139 fail: 1140 panic("Cannot allocate percpu memory for EFI SVE save/restore"); 1141 } 1142 1143 /* 1144 * Enable SVE for EL1. 1145 * Intended for use by the cpufeatures code during CPU boot. 1146 */ 1147 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1148 { 1149 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); 1150 isb(); 1151 } 1152 1153 /* 1154 * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE 1155 * vector length. 1156 * 1157 * Use only if SVE is present. 1158 * This function clobbers the SVE vector length. 1159 */ 1160 u64 read_zcr_features(void) 1161 { 1162 u64 zcr; 1163 unsigned int vq_max; 1164 1165 /* 1166 * Set the maximum possible VL, and write zeroes to all other 1167 * bits to see if they stick. 1168 */ 1169 sve_kernel_enable(NULL); 1170 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); 1171 1172 zcr = read_sysreg_s(SYS_ZCR_EL1); 1173 zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ 1174 vq_max = sve_vq_from_vl(sve_get_vl()); 1175 zcr |= vq_max - 1; /* set LEN field to maximum effective value */ 1176 1177 return zcr; 1178 } 1179 1180 void __init sve_setup(void) 1181 { 1182 struct vl_info *info = &vl_info[ARM64_VEC_SVE]; 1183 u64 zcr; 1184 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1185 unsigned long b; 1186 1187 if (!system_supports_sve()) 1188 return; 1189 1190 /* 1191 * The SVE architecture mandates support for 128-bit vectors, 1192 * so sve_vq_map must have at least SVE_VQ_MIN set. 1193 * If something went wrong, at least try to patch it up: 1194 */ 1195 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map))) 1196 set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map); 1197 1198 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 1199 info->max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1); 1200 1201 /* 1202 * Sanity-check that the max VL we determined through CPU features 1203 * corresponds properly to sve_vq_map. If not, do our best: 1204 */ 1205 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SVE, 1206 info->max_vl))) 1207 info->max_vl = find_supported_vector_length(ARM64_VEC_SVE, 1208 info->max_vl); 1209 1210 /* 1211 * For the default VL, pick the maximum supported value <= 64. 1212 * VL == 64 is guaranteed not to grow the signal frame. 1213 */ 1214 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64)); 1215 1216 bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map, 1217 SVE_VQ_MAX); 1218 1219 b = find_last_bit(tmp_map, SVE_VQ_MAX); 1220 if (b >= SVE_VQ_MAX) 1221 /* No non-virtualisable VLs found */ 1222 info->max_virtualisable_vl = SVE_VQ_MAX; 1223 else if (WARN_ON(b == SVE_VQ_MAX - 1)) 1224 /* No virtualisable VLs? This is architecturally forbidden. */ 1225 info->max_virtualisable_vl = SVE_VQ_MIN; 1226 else /* b + 1 < SVE_VQ_MAX */ 1227 info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1)); 1228 1229 if (info->max_virtualisable_vl > info->max_vl) 1230 info->max_virtualisable_vl = info->max_vl; 1231 1232 pr_info("%s: maximum available vector length %u bytes per vector\n", 1233 info->name, info->max_vl); 1234 pr_info("%s: default vector length %u bytes per vector\n", 1235 info->name, get_sve_default_vl()); 1236 1237 /* KVM decides whether to support mismatched systems. Just warn here: */ 1238 if (sve_max_virtualisable_vl() < sve_max_vl()) 1239 pr_warn("%s: unvirtualisable vector lengths present\n", 1240 info->name); 1241 1242 sve_efi_setup(); 1243 } 1244 1245 /* 1246 * Called from the put_task_struct() path, which cannot get here 1247 * unless dead_task is really dead and not schedulable. 1248 */ 1249 void fpsimd_release_task(struct task_struct *dead_task) 1250 { 1251 __sve_free(dead_task); 1252 sme_free(dead_task); 1253 } 1254 1255 #endif /* CONFIG_ARM64_SVE */ 1256 1257 #ifdef CONFIG_ARM64_SME 1258 1259 /* 1260 * Ensure that task->thread.za_state is allocated and sufficiently large. 1261 * 1262 * This function should be used only in preparation for replacing 1263 * task->thread.za_state with new data. The memory is always zeroed 1264 * here to prevent stale data from showing through: this is done in 1265 * the interest of testability and predictability, the architecture 1266 * guarantees that when ZA is enabled it will be zeroed. 1267 */ 1268 void sme_alloc(struct task_struct *task) 1269 { 1270 if (task->thread.za_state) { 1271 memset(task->thread.za_state, 0, za_state_size(task)); 1272 return; 1273 } 1274 1275 /* This could potentially be up to 64K. */ 1276 task->thread.za_state = 1277 kzalloc(za_state_size(task), GFP_KERNEL); 1278 } 1279 1280 static void sme_free(struct task_struct *task) 1281 { 1282 kfree(task->thread.za_state); 1283 task->thread.za_state = NULL; 1284 } 1285 1286 void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1287 { 1288 /* Set priority for all PEs to architecturally defined minimum */ 1289 write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK, 1290 SYS_SMPRI_EL1); 1291 1292 /* Allow SME in kernel */ 1293 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1); 1294 isb(); 1295 1296 /* Allow EL0 to access TPIDR2 */ 1297 write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1); 1298 isb(); 1299 } 1300 1301 /* 1302 * This must be called after sme_kernel_enable(), we rely on the 1303 * feature table being sorted to ensure this. 1304 */ 1305 void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1306 { 1307 /* Allow use of FA64 */ 1308 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK, 1309 SYS_SMCR_EL1); 1310 } 1311 1312 /* 1313 * Read the pseudo-SMCR used by cpufeatures to identify the supported 1314 * vector length. 1315 * 1316 * Use only if SME is present. 1317 * This function clobbers the SME vector length. 1318 */ 1319 u64 read_smcr_features(void) 1320 { 1321 u64 smcr; 1322 unsigned int vq_max; 1323 1324 sme_kernel_enable(NULL); 1325 1326 /* 1327 * Set the maximum possible VL. 1328 */ 1329 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK, 1330 SYS_SMCR_EL1); 1331 1332 smcr = read_sysreg_s(SYS_SMCR_EL1); 1333 smcr &= ~(u64)SMCR_ELx_LEN_MASK; /* Only the LEN field */ 1334 vq_max = sve_vq_from_vl(sme_get_vl()); 1335 smcr |= vq_max - 1; /* set LEN field to maximum effective value */ 1336 1337 return smcr; 1338 } 1339 1340 void __init sme_setup(void) 1341 { 1342 struct vl_info *info = &vl_info[ARM64_VEC_SME]; 1343 u64 smcr; 1344 int min_bit; 1345 1346 if (!system_supports_sme()) 1347 return; 1348 1349 /* 1350 * SME doesn't require any particular vector length be 1351 * supported but it does require at least one. We should have 1352 * disabled the feature entirely while bringing up CPUs but 1353 * let's double check here. 1354 */ 1355 WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX)); 1356 1357 min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX); 1358 info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit)); 1359 1360 smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 1361 info->max_vl = sve_vl_from_vq((smcr & SMCR_ELx_LEN_MASK) + 1); 1362 1363 /* 1364 * Sanity-check that the max VL we determined through CPU features 1365 * corresponds properly to sme_vq_map. If not, do our best: 1366 */ 1367 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SME, 1368 info->max_vl))) 1369 info->max_vl = find_supported_vector_length(ARM64_VEC_SME, 1370 info->max_vl); 1371 1372 WARN_ON(info->min_vl > info->max_vl); 1373 1374 /* 1375 * For the default VL, pick the maximum supported value <= 32 1376 * (256 bits) if there is one since this is guaranteed not to 1377 * grow the signal frame when in streaming mode, otherwise the 1378 * minimum available VL will be used. 1379 */ 1380 set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32)); 1381 1382 pr_info("SME: minimum available vector length %u bytes per vector\n", 1383 info->min_vl); 1384 pr_info("SME: maximum available vector length %u bytes per vector\n", 1385 info->max_vl); 1386 pr_info("SME: default vector length %u bytes per vector\n", 1387 get_sme_default_vl()); 1388 } 1389 1390 #endif /* CONFIG_ARM64_SME */ 1391 1392 static void sve_init_regs(void) 1393 { 1394 /* 1395 * Convert the FPSIMD state to SVE, zeroing all the state that 1396 * is not shared with FPSIMD. If (as is likely) the current 1397 * state is live in the registers then do this there and 1398 * update our metadata for the current task including 1399 * disabling the trap, otherwise update our in-memory copy. 1400 * We are guaranteed to not be in streaming mode, we can only 1401 * take a SVE trap when not in streaming mode and we can't be 1402 * in streaming mode when taking a SME trap. 1403 */ 1404 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 1405 unsigned long vq_minus_one = 1406 sve_vq_from_vl(task_get_sve_vl(current)) - 1; 1407 sve_set_vq(vq_minus_one); 1408 sve_flush_live(true, vq_minus_one); 1409 fpsimd_bind_task_to_cpu(); 1410 } else { 1411 fpsimd_to_sve(current); 1412 current->thread.fp_type = FP_STATE_SVE; 1413 } 1414 } 1415 1416 /* 1417 * Trapped SVE access 1418 * 1419 * Storage is allocated for the full SVE state, the current FPSIMD 1420 * register contents are migrated across, and the access trap is 1421 * disabled. 1422 * 1423 * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state() 1424 * would have disabled the SVE access trap for userspace during 1425 * ret_to_user, making an SVE access trap impossible in that case. 1426 */ 1427 void do_sve_acc(unsigned long esr, struct pt_regs *regs) 1428 { 1429 /* Even if we chose not to use SVE, the hardware could still trap: */ 1430 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) { 1431 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1432 return; 1433 } 1434 1435 sve_alloc(current, true); 1436 if (!current->thread.sve_state) { 1437 force_sig(SIGKILL); 1438 return; 1439 } 1440 1441 get_cpu_fpsimd_context(); 1442 1443 if (test_and_set_thread_flag(TIF_SVE)) 1444 WARN_ON(1); /* SVE access shouldn't have trapped */ 1445 1446 /* 1447 * Even if the task can have used streaming mode we can only 1448 * generate SVE access traps in normal SVE mode and 1449 * transitioning out of streaming mode may discard any 1450 * streaming mode state. Always clear the high bits to avoid 1451 * any potential errors tracking what is properly initialised. 1452 */ 1453 sve_init_regs(); 1454 1455 put_cpu_fpsimd_context(); 1456 } 1457 1458 /* 1459 * Trapped SME access 1460 * 1461 * Storage is allocated for the full SVE and SME state, the current 1462 * FPSIMD register contents are migrated to SVE if SVE is not already 1463 * active, and the access trap is disabled. 1464 * 1465 * TIF_SME should be clear on entry: otherwise, fpsimd_restore_current_state() 1466 * would have disabled the SME access trap for userspace during 1467 * ret_to_user, making an SVE access trap impossible in that case. 1468 */ 1469 void do_sme_acc(unsigned long esr, struct pt_regs *regs) 1470 { 1471 /* Even if we chose not to use SME, the hardware could still trap: */ 1472 if (unlikely(!system_supports_sme()) || WARN_ON(is_compat_task())) { 1473 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1474 return; 1475 } 1476 1477 /* 1478 * If this not a trap due to SME being disabled then something 1479 * is being used in the wrong mode, report as SIGILL. 1480 */ 1481 if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) { 1482 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1483 return; 1484 } 1485 1486 sve_alloc(current, false); 1487 sme_alloc(current); 1488 if (!current->thread.sve_state || !current->thread.za_state) { 1489 force_sig(SIGKILL); 1490 return; 1491 } 1492 1493 get_cpu_fpsimd_context(); 1494 1495 /* With TIF_SME userspace shouldn't generate any traps */ 1496 if (test_and_set_thread_flag(TIF_SME)) 1497 WARN_ON(1); 1498 1499 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 1500 unsigned long vq_minus_one = 1501 sve_vq_from_vl(task_get_sme_vl(current)) - 1; 1502 sme_set_vq(vq_minus_one); 1503 1504 fpsimd_bind_task_to_cpu(); 1505 } 1506 1507 put_cpu_fpsimd_context(); 1508 } 1509 1510 /* 1511 * Trapped FP/ASIMD access. 1512 */ 1513 void do_fpsimd_acc(unsigned long esr, struct pt_regs *regs) 1514 { 1515 /* TODO: implement lazy context saving/restoring */ 1516 WARN_ON(1); 1517 } 1518 1519 /* 1520 * Raise a SIGFPE for the current process. 1521 */ 1522 void do_fpsimd_exc(unsigned long esr, struct pt_regs *regs) 1523 { 1524 unsigned int si_code = FPE_FLTUNK; 1525 1526 if (esr & ESR_ELx_FP_EXC_TFV) { 1527 if (esr & FPEXC_IOF) 1528 si_code = FPE_FLTINV; 1529 else if (esr & FPEXC_DZF) 1530 si_code = FPE_FLTDIV; 1531 else if (esr & FPEXC_OFF) 1532 si_code = FPE_FLTOVF; 1533 else if (esr & FPEXC_UFF) 1534 si_code = FPE_FLTUND; 1535 else if (esr & FPEXC_IXF) 1536 si_code = FPE_FLTRES; 1537 } 1538 1539 send_sig_fault(SIGFPE, si_code, 1540 (void __user *)instruction_pointer(regs), 1541 current); 1542 } 1543 1544 void fpsimd_thread_switch(struct task_struct *next) 1545 { 1546 bool wrong_task, wrong_cpu; 1547 1548 if (!system_supports_fpsimd()) 1549 return; 1550 1551 __get_cpu_fpsimd_context(); 1552 1553 /* Save unsaved fpsimd state, if any: */ 1554 fpsimd_save(); 1555 1556 /* 1557 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's 1558 * state. For kernel threads, FPSIMD registers are never loaded 1559 * and wrong_task and wrong_cpu will always be true. 1560 */ 1561 wrong_task = __this_cpu_read(fpsimd_last_state.st) != 1562 &next->thread.uw.fpsimd_state; 1563 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id(); 1564 1565 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE, 1566 wrong_task || wrong_cpu); 1567 1568 __put_cpu_fpsimd_context(); 1569 } 1570 1571 static void fpsimd_flush_thread_vl(enum vec_type type) 1572 { 1573 int vl, supported_vl; 1574 1575 /* 1576 * Reset the task vector length as required. This is where we 1577 * ensure that all user tasks have a valid vector length 1578 * configured: no kernel task can become a user task without 1579 * an exec and hence a call to this function. By the time the 1580 * first call to this function is made, all early hardware 1581 * probing is complete, so __sve_default_vl should be valid. 1582 * If a bug causes this to go wrong, we make some noise and 1583 * try to fudge thread.sve_vl to a safe value here. 1584 */ 1585 vl = task_get_vl_onexec(current, type); 1586 if (!vl) 1587 vl = get_default_vl(type); 1588 1589 if (WARN_ON(!sve_vl_valid(vl))) 1590 vl = vl_info[type].min_vl; 1591 1592 supported_vl = find_supported_vector_length(type, vl); 1593 if (WARN_ON(supported_vl != vl)) 1594 vl = supported_vl; 1595 1596 task_set_vl(current, type, vl); 1597 1598 /* 1599 * If the task is not set to inherit, ensure that the vector 1600 * length will be reset by a subsequent exec: 1601 */ 1602 if (!test_thread_flag(vec_vl_inherit_flag(type))) 1603 task_set_vl_onexec(current, type, 0); 1604 } 1605 1606 void fpsimd_flush_thread(void) 1607 { 1608 void *sve_state = NULL; 1609 void *za_state = NULL; 1610 1611 if (!system_supports_fpsimd()) 1612 return; 1613 1614 get_cpu_fpsimd_context(); 1615 1616 fpsimd_flush_task_state(current); 1617 memset(¤t->thread.uw.fpsimd_state, 0, 1618 sizeof(current->thread.uw.fpsimd_state)); 1619 1620 if (system_supports_sve()) { 1621 clear_thread_flag(TIF_SVE); 1622 1623 /* Defer kfree() while in atomic context */ 1624 sve_state = current->thread.sve_state; 1625 current->thread.sve_state = NULL; 1626 1627 fpsimd_flush_thread_vl(ARM64_VEC_SVE); 1628 } 1629 1630 if (system_supports_sme()) { 1631 clear_thread_flag(TIF_SME); 1632 1633 /* Defer kfree() while in atomic context */ 1634 za_state = current->thread.za_state; 1635 current->thread.za_state = NULL; 1636 1637 fpsimd_flush_thread_vl(ARM64_VEC_SME); 1638 current->thread.svcr = 0; 1639 } 1640 1641 current->thread.fp_type = FP_STATE_FPSIMD; 1642 1643 put_cpu_fpsimd_context(); 1644 kfree(sve_state); 1645 kfree(za_state); 1646 } 1647 1648 /* 1649 * Save the userland FPSIMD state of 'current' to memory, but only if the state 1650 * currently held in the registers does in fact belong to 'current' 1651 */ 1652 void fpsimd_preserve_current_state(void) 1653 { 1654 if (!system_supports_fpsimd()) 1655 return; 1656 1657 get_cpu_fpsimd_context(); 1658 fpsimd_save(); 1659 put_cpu_fpsimd_context(); 1660 } 1661 1662 /* 1663 * Like fpsimd_preserve_current_state(), but ensure that 1664 * current->thread.uw.fpsimd_state is updated so that it can be copied to 1665 * the signal frame. 1666 */ 1667 void fpsimd_signal_preserve_current_state(void) 1668 { 1669 fpsimd_preserve_current_state(); 1670 if (test_thread_flag(TIF_SVE)) 1671 sve_to_fpsimd(current); 1672 } 1673 1674 /* 1675 * Called by KVM when entering the guest. 1676 */ 1677 void fpsimd_kvm_prepare(void) 1678 { 1679 if (!system_supports_sve()) 1680 return; 1681 1682 /* 1683 * KVM does not save host SVE state since we can only enter 1684 * the guest from a syscall so the ABI means that only the 1685 * non-saved SVE state needs to be saved. If we have left 1686 * SVE enabled for performance reasons then update the task 1687 * state to be FPSIMD only. 1688 */ 1689 get_cpu_fpsimd_context(); 1690 1691 if (test_and_clear_thread_flag(TIF_SVE)) { 1692 sve_to_fpsimd(current); 1693 current->thread.fp_type = FP_STATE_FPSIMD; 1694 } 1695 1696 put_cpu_fpsimd_context(); 1697 } 1698 1699 /* 1700 * Associate current's FPSIMD context with this cpu 1701 * The caller must have ownership of the cpu FPSIMD context before calling 1702 * this function. 1703 */ 1704 static void fpsimd_bind_task_to_cpu(void) 1705 { 1706 struct cpu_fp_state *last = this_cpu_ptr(&fpsimd_last_state); 1707 1708 WARN_ON(!system_supports_fpsimd()); 1709 last->st = ¤t->thread.uw.fpsimd_state; 1710 last->sve_state = current->thread.sve_state; 1711 last->za_state = current->thread.za_state; 1712 last->sve_vl = task_get_sve_vl(current); 1713 last->sme_vl = task_get_sme_vl(current); 1714 last->svcr = ¤t->thread.svcr; 1715 last->fp_type = ¤t->thread.fp_type; 1716 last->to_save = FP_STATE_CURRENT; 1717 current->thread.fpsimd_cpu = smp_processor_id(); 1718 1719 /* 1720 * Toggle SVE and SME trapping for userspace if needed, these 1721 * are serialsied by ret_to_user(). 1722 */ 1723 if (system_supports_sme()) { 1724 if (test_thread_flag(TIF_SME)) 1725 sme_user_enable(); 1726 else 1727 sme_user_disable(); 1728 } 1729 1730 if (system_supports_sve()) { 1731 if (test_thread_flag(TIF_SVE)) 1732 sve_user_enable(); 1733 else 1734 sve_user_disable(); 1735 } 1736 } 1737 1738 void fpsimd_bind_state_to_cpu(struct cpu_fp_state *state) 1739 { 1740 struct cpu_fp_state *last = this_cpu_ptr(&fpsimd_last_state); 1741 1742 WARN_ON(!system_supports_fpsimd()); 1743 WARN_ON(!in_softirq() && !irqs_disabled()); 1744 1745 *last = *state; 1746 } 1747 1748 /* 1749 * Load the userland FPSIMD state of 'current' from memory, but only if the 1750 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD 1751 * state of 'current'. This is called when we are preparing to return to 1752 * userspace to ensure that userspace sees a good register state. 1753 */ 1754 void fpsimd_restore_current_state(void) 1755 { 1756 /* 1757 * For the tasks that were created before we detected the absence of 1758 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(), 1759 * e.g, init. This could be then inherited by the children processes. 1760 * If we later detect that the system doesn't support FP/SIMD, 1761 * we must clear the flag for all the tasks to indicate that the 1762 * FPSTATE is clean (as we can't have one) to avoid looping for ever in 1763 * do_notify_resume(). 1764 */ 1765 if (!system_supports_fpsimd()) { 1766 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1767 return; 1768 } 1769 1770 get_cpu_fpsimd_context(); 1771 1772 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { 1773 task_fpsimd_load(); 1774 fpsimd_bind_task_to_cpu(); 1775 } 1776 1777 put_cpu_fpsimd_context(); 1778 } 1779 1780 /* 1781 * Load an updated userland FPSIMD state for 'current' from memory and set the 1782 * flag that indicates that the FPSIMD register contents are the most recent 1783 * FPSIMD state of 'current'. This is used by the signal code to restore the 1784 * register state when returning from a signal handler in FPSIMD only cases, 1785 * any SVE context will be discarded. 1786 */ 1787 void fpsimd_update_current_state(struct user_fpsimd_state const *state) 1788 { 1789 if (WARN_ON(!system_supports_fpsimd())) 1790 return; 1791 1792 get_cpu_fpsimd_context(); 1793 1794 current->thread.uw.fpsimd_state = *state; 1795 if (test_thread_flag(TIF_SVE)) 1796 fpsimd_to_sve(current); 1797 1798 task_fpsimd_load(); 1799 fpsimd_bind_task_to_cpu(); 1800 1801 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1802 1803 put_cpu_fpsimd_context(); 1804 } 1805 1806 /* 1807 * Invalidate live CPU copies of task t's FPSIMD state 1808 * 1809 * This function may be called with preemption enabled. The barrier() 1810 * ensures that the assignment to fpsimd_cpu is visible to any 1811 * preemption/softirq that could race with set_tsk_thread_flag(), so 1812 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared. 1813 * 1814 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any 1815 * subsequent code. 1816 */ 1817 void fpsimd_flush_task_state(struct task_struct *t) 1818 { 1819 t->thread.fpsimd_cpu = NR_CPUS; 1820 /* 1821 * If we don't support fpsimd, bail out after we have 1822 * reset the fpsimd_cpu for this task and clear the 1823 * FPSTATE. 1824 */ 1825 if (!system_supports_fpsimd()) 1826 return; 1827 barrier(); 1828 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE); 1829 1830 barrier(); 1831 } 1832 1833 /* 1834 * Invalidate any task's FPSIMD state that is present on this cpu. 1835 * The FPSIMD context should be acquired with get_cpu_fpsimd_context() 1836 * before calling this function. 1837 */ 1838 static void fpsimd_flush_cpu_state(void) 1839 { 1840 WARN_ON(!system_supports_fpsimd()); 1841 __this_cpu_write(fpsimd_last_state.st, NULL); 1842 1843 /* 1844 * Leaving streaming mode enabled will cause issues for any kernel 1845 * NEON and leaving streaming mode or ZA enabled may increase power 1846 * consumption. 1847 */ 1848 if (system_supports_sme()) 1849 sme_smstop(); 1850 1851 set_thread_flag(TIF_FOREIGN_FPSTATE); 1852 } 1853 1854 /* 1855 * Save the FPSIMD state to memory and invalidate cpu view. 1856 * This function must be called with preemption disabled. 1857 */ 1858 void fpsimd_save_and_flush_cpu_state(void) 1859 { 1860 if (!system_supports_fpsimd()) 1861 return; 1862 WARN_ON(preemptible()); 1863 __get_cpu_fpsimd_context(); 1864 fpsimd_save(); 1865 fpsimd_flush_cpu_state(); 1866 __put_cpu_fpsimd_context(); 1867 } 1868 1869 #ifdef CONFIG_KERNEL_MODE_NEON 1870 1871 /* 1872 * Kernel-side NEON support functions 1873 */ 1874 1875 /* 1876 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling 1877 * context 1878 * 1879 * Must not be called unless may_use_simd() returns true. 1880 * Task context in the FPSIMD registers is saved back to memory as necessary. 1881 * 1882 * A matching call to kernel_neon_end() must be made before returning from the 1883 * calling context. 1884 * 1885 * The caller may freely use the FPSIMD registers until kernel_neon_end() is 1886 * called. 1887 */ 1888 void kernel_neon_begin(void) 1889 { 1890 if (WARN_ON(!system_supports_fpsimd())) 1891 return; 1892 1893 BUG_ON(!may_use_simd()); 1894 1895 get_cpu_fpsimd_context(); 1896 1897 /* Save unsaved fpsimd state, if any: */ 1898 fpsimd_save(); 1899 1900 /* Invalidate any task state remaining in the fpsimd regs: */ 1901 fpsimd_flush_cpu_state(); 1902 } 1903 EXPORT_SYMBOL_GPL(kernel_neon_begin); 1904 1905 /* 1906 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task 1907 * 1908 * Must be called from a context in which kernel_neon_begin() was previously 1909 * called, with no call to kernel_neon_end() in the meantime. 1910 * 1911 * The caller must not use the FPSIMD registers after this function is called, 1912 * unless kernel_neon_begin() is called again in the meantime. 1913 */ 1914 void kernel_neon_end(void) 1915 { 1916 if (!system_supports_fpsimd()) 1917 return; 1918 1919 put_cpu_fpsimd_context(); 1920 } 1921 EXPORT_SYMBOL_GPL(kernel_neon_end); 1922 1923 #ifdef CONFIG_EFI 1924 1925 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state); 1926 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used); 1927 static DEFINE_PER_CPU(bool, efi_sve_state_used); 1928 static DEFINE_PER_CPU(bool, efi_sm_state); 1929 1930 /* 1931 * EFI runtime services support functions 1932 * 1933 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call. 1934 * This means that for EFI (and only for EFI), we have to assume that FPSIMD 1935 * is always used rather than being an optional accelerator. 1936 * 1937 * These functions provide the necessary support for ensuring FPSIMD 1938 * save/restore in the contexts from which EFI is used. 1939 * 1940 * Do not use them for any other purpose -- if tempted to do so, you are 1941 * either doing something wrong or you need to propose some refactoring. 1942 */ 1943 1944 /* 1945 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call 1946 */ 1947 void __efi_fpsimd_begin(void) 1948 { 1949 if (!system_supports_fpsimd()) 1950 return; 1951 1952 WARN_ON(preemptible()); 1953 1954 if (may_use_simd()) { 1955 kernel_neon_begin(); 1956 } else { 1957 /* 1958 * If !efi_sve_state, SVE can't be in use yet and doesn't need 1959 * preserving: 1960 */ 1961 if (system_supports_sve() && likely(efi_sve_state)) { 1962 char *sve_state = this_cpu_ptr(efi_sve_state); 1963 bool ffr = true; 1964 u64 svcr; 1965 1966 __this_cpu_write(efi_sve_state_used, true); 1967 1968 if (system_supports_sme()) { 1969 svcr = read_sysreg_s(SYS_SVCR); 1970 1971 __this_cpu_write(efi_sm_state, 1972 svcr & SVCR_SM_MASK); 1973 1974 /* 1975 * Unless we have FA64 FFR does not 1976 * exist in streaming mode. 1977 */ 1978 if (!system_supports_fa64()) 1979 ffr = !(svcr & SVCR_SM_MASK); 1980 } 1981 1982 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()), 1983 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1984 ffr); 1985 1986 if (system_supports_sme()) 1987 sysreg_clear_set_s(SYS_SVCR, 1988 SVCR_SM_MASK, 0); 1989 1990 } else { 1991 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); 1992 } 1993 1994 __this_cpu_write(efi_fpsimd_state_used, true); 1995 } 1996 } 1997 1998 /* 1999 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call 2000 */ 2001 void __efi_fpsimd_end(void) 2002 { 2003 if (!system_supports_fpsimd()) 2004 return; 2005 2006 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) { 2007 kernel_neon_end(); 2008 } else { 2009 if (system_supports_sve() && 2010 likely(__this_cpu_read(efi_sve_state_used))) { 2011 char const *sve_state = this_cpu_ptr(efi_sve_state); 2012 bool ffr = true; 2013 2014 /* 2015 * Restore streaming mode; EFI calls are 2016 * normal function calls so should not return in 2017 * streaming mode. 2018 */ 2019 if (system_supports_sme()) { 2020 if (__this_cpu_read(efi_sm_state)) { 2021 sysreg_clear_set_s(SYS_SVCR, 2022 0, 2023 SVCR_SM_MASK); 2024 2025 /* 2026 * Unless we have FA64 FFR does not 2027 * exist in streaming mode. 2028 */ 2029 if (!system_supports_fa64()) 2030 ffr = false; 2031 } 2032 } 2033 2034 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()), 2035 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 2036 ffr); 2037 2038 __this_cpu_write(efi_sve_state_used, false); 2039 } else { 2040 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); 2041 } 2042 } 2043 } 2044 2045 #endif /* CONFIG_EFI */ 2046 2047 #endif /* CONFIG_KERNEL_MODE_NEON */ 2048 2049 #ifdef CONFIG_CPU_PM 2050 static int fpsimd_cpu_pm_notifier(struct notifier_block *self, 2051 unsigned long cmd, void *v) 2052 { 2053 switch (cmd) { 2054 case CPU_PM_ENTER: 2055 fpsimd_save_and_flush_cpu_state(); 2056 break; 2057 case CPU_PM_EXIT: 2058 break; 2059 case CPU_PM_ENTER_FAILED: 2060 default: 2061 return NOTIFY_DONE; 2062 } 2063 return NOTIFY_OK; 2064 } 2065 2066 static struct notifier_block fpsimd_cpu_pm_notifier_block = { 2067 .notifier_call = fpsimd_cpu_pm_notifier, 2068 }; 2069 2070 static void __init fpsimd_pm_init(void) 2071 { 2072 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); 2073 } 2074 2075 #else 2076 static inline void fpsimd_pm_init(void) { } 2077 #endif /* CONFIG_CPU_PM */ 2078 2079 #ifdef CONFIG_HOTPLUG_CPU 2080 static int fpsimd_cpu_dead(unsigned int cpu) 2081 { 2082 per_cpu(fpsimd_last_state.st, cpu) = NULL; 2083 return 0; 2084 } 2085 2086 static inline void fpsimd_hotplug_init(void) 2087 { 2088 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead", 2089 NULL, fpsimd_cpu_dead); 2090 } 2091 2092 #else 2093 static inline void fpsimd_hotplug_init(void) { } 2094 #endif 2095 2096 /* 2097 * FP/SIMD support code initialisation. 2098 */ 2099 static int __init fpsimd_init(void) 2100 { 2101 if (cpu_have_named_feature(FP)) { 2102 fpsimd_pm_init(); 2103 fpsimd_hotplug_init(); 2104 } else { 2105 pr_notice("Floating-point is not implemented\n"); 2106 } 2107 2108 if (!cpu_have_named_feature(ASIMD)) 2109 pr_notice("Advanced SIMD is not implemented\n"); 2110 2111 2112 if (cpu_have_named_feature(SME) && !cpu_have_named_feature(SVE)) 2113 pr_notice("SME is implemented but not SVE\n"); 2114 2115 sve_sysctl_init(); 2116 sme_sysctl_init(); 2117 2118 return 0; 2119 } 2120 core_initcall(fpsimd_init); 2121