1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FP/SIMD context switching and fault handling 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/bottom_half.h> 12 #include <linux/bug.h> 13 #include <linux/cache.h> 14 #include <linux/compat.h> 15 #include <linux/compiler.h> 16 #include <linux/cpu.h> 17 #include <linux/cpu_pm.h> 18 #include <linux/ctype.h> 19 #include <linux/kernel.h> 20 #include <linux/linkage.h> 21 #include <linux/irqflags.h> 22 #include <linux/init.h> 23 #include <linux/percpu.h> 24 #include <linux/prctl.h> 25 #include <linux/preempt.h> 26 #include <linux/ptrace.h> 27 #include <linux/sched/signal.h> 28 #include <linux/sched/task_stack.h> 29 #include <linux/signal.h> 30 #include <linux/slab.h> 31 #include <linux/stddef.h> 32 #include <linux/sysctl.h> 33 #include <linux/swab.h> 34 35 #include <asm/esr.h> 36 #include <asm/exception.h> 37 #include <asm/fpsimd.h> 38 #include <asm/cpufeature.h> 39 #include <asm/cputype.h> 40 #include <asm/neon.h> 41 #include <asm/processor.h> 42 #include <asm/simd.h> 43 #include <asm/sigcontext.h> 44 #include <asm/sysreg.h> 45 #include <asm/traps.h> 46 #include <asm/virt.h> 47 48 #define FPEXC_IOF (1 << 0) 49 #define FPEXC_DZF (1 << 1) 50 #define FPEXC_OFF (1 << 2) 51 #define FPEXC_UFF (1 << 3) 52 #define FPEXC_IXF (1 << 4) 53 #define FPEXC_IDF (1 << 7) 54 55 /* 56 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.) 57 * 58 * In order to reduce the number of times the FPSIMD state is needlessly saved 59 * and restored, we need to keep track of two things: 60 * (a) for each task, we need to remember which CPU was the last one to have 61 * the task's FPSIMD state loaded into its FPSIMD registers; 62 * (b) for each CPU, we need to remember which task's userland FPSIMD state has 63 * been loaded into its FPSIMD registers most recently, or whether it has 64 * been used to perform kernel mode NEON in the meantime. 65 * 66 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to 67 * the id of the current CPU every time the state is loaded onto a CPU. For (b), 68 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the 69 * address of the userland FPSIMD state of the task that was loaded onto the CPU 70 * the most recently, or NULL if kernel mode NEON has been performed after that. 71 * 72 * With this in place, we no longer have to restore the next FPSIMD state right 73 * when switching between tasks. Instead, we can defer this check to userland 74 * resume, at which time we verify whether the CPU's fpsimd_last_state and the 75 * task's fpsimd_cpu are still mutually in sync. If this is the case, we 76 * can omit the FPSIMD restore. 77 * 78 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to 79 * indicate whether or not the userland FPSIMD state of the current task is 80 * present in the registers. The flag is set unless the FPSIMD registers of this 81 * CPU currently contain the most recent userland FPSIMD state of the current 82 * task. If the task is behaving as a VMM, then this is will be managed by 83 * KVM which will clear it to indicate that the vcpu FPSIMD state is currently 84 * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware 85 * softirq kicks in. Upon vcpu_put(), KVM will save the vcpu FP state and 86 * flag the register state as invalid. 87 * 88 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may 89 * save the task's FPSIMD context back to task_struct from softirq context. 90 * To prevent this from racing with the manipulation of the task's FPSIMD state 91 * from task context and thereby corrupting the state, it is necessary to 92 * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE 93 * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to 94 * run but prevent them to use FPSIMD. 95 * 96 * For a certain task, the sequence may look something like this: 97 * - the task gets scheduled in; if both the task's fpsimd_cpu field 98 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu 99 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is 100 * cleared, otherwise it is set; 101 * 102 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's 103 * userland FPSIMD state is copied from memory to the registers, the task's 104 * fpsimd_cpu field is set to the id of the current CPU, the current 105 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the 106 * TIF_FOREIGN_FPSTATE flag is cleared; 107 * 108 * - the task executes an ordinary syscall; upon return to userland, the 109 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is 110 * restored; 111 * 112 * - the task executes a syscall which executes some NEON instructions; this is 113 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD 114 * register contents to memory, clears the fpsimd_last_state per-cpu variable 115 * and sets the TIF_FOREIGN_FPSTATE flag; 116 * 117 * - the task gets preempted after kernel_neon_end() is called; as we have not 118 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so 119 * whatever is in the FPSIMD registers is not saved to memory, but discarded. 120 */ 121 struct fpsimd_last_state_struct { 122 struct user_fpsimd_state *st; 123 void *sve_state; 124 void *za_state; 125 u64 *svcr; 126 unsigned int sve_vl; 127 unsigned int sme_vl; 128 }; 129 130 static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state); 131 132 __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = { 133 #ifdef CONFIG_ARM64_SVE 134 [ARM64_VEC_SVE] = { 135 .type = ARM64_VEC_SVE, 136 .name = "SVE", 137 .min_vl = SVE_VL_MIN, 138 .max_vl = SVE_VL_MIN, 139 .max_virtualisable_vl = SVE_VL_MIN, 140 }, 141 #endif 142 #ifdef CONFIG_ARM64_SME 143 [ARM64_VEC_SME] = { 144 .type = ARM64_VEC_SME, 145 .name = "SME", 146 }, 147 #endif 148 }; 149 150 static unsigned int vec_vl_inherit_flag(enum vec_type type) 151 { 152 switch (type) { 153 case ARM64_VEC_SVE: 154 return TIF_SVE_VL_INHERIT; 155 case ARM64_VEC_SME: 156 return TIF_SME_VL_INHERIT; 157 default: 158 WARN_ON_ONCE(1); 159 return 0; 160 } 161 } 162 163 struct vl_config { 164 int __default_vl; /* Default VL for tasks */ 165 }; 166 167 static struct vl_config vl_config[ARM64_VEC_MAX]; 168 169 static inline int get_default_vl(enum vec_type type) 170 { 171 return READ_ONCE(vl_config[type].__default_vl); 172 } 173 174 #ifdef CONFIG_ARM64_SVE 175 176 static inline int get_sve_default_vl(void) 177 { 178 return get_default_vl(ARM64_VEC_SVE); 179 } 180 181 static inline void set_default_vl(enum vec_type type, int val) 182 { 183 WRITE_ONCE(vl_config[type].__default_vl, val); 184 } 185 186 static inline void set_sve_default_vl(int val) 187 { 188 set_default_vl(ARM64_VEC_SVE, val); 189 } 190 191 static void __percpu *efi_sve_state; 192 193 #else /* ! CONFIG_ARM64_SVE */ 194 195 /* Dummy declaration for code that will be optimised out: */ 196 extern void __percpu *efi_sve_state; 197 198 #endif /* ! CONFIG_ARM64_SVE */ 199 200 #ifdef CONFIG_ARM64_SME 201 202 static int get_sme_default_vl(void) 203 { 204 return get_default_vl(ARM64_VEC_SME); 205 } 206 207 static void set_sme_default_vl(int val) 208 { 209 set_default_vl(ARM64_VEC_SME, val); 210 } 211 212 static void sme_free(struct task_struct *); 213 214 #else 215 216 static inline void sme_free(struct task_struct *t) { } 217 218 #endif 219 220 DEFINE_PER_CPU(bool, fpsimd_context_busy); 221 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy); 222 223 static void fpsimd_bind_task_to_cpu(void); 224 225 static void __get_cpu_fpsimd_context(void) 226 { 227 bool busy = __this_cpu_xchg(fpsimd_context_busy, true); 228 229 WARN_ON(busy); 230 } 231 232 /* 233 * Claim ownership of the CPU FPSIMD context for use by the calling context. 234 * 235 * The caller may freely manipulate the FPSIMD context metadata until 236 * put_cpu_fpsimd_context() is called. 237 * 238 * The double-underscore version must only be called if you know the task 239 * can't be preempted. 240 * 241 * On RT kernels local_bh_disable() is not sufficient because it only 242 * serializes soft interrupt related sections via a local lock, but stays 243 * preemptible. Disabling preemption is the right choice here as bottom 244 * half processing is always in thread context on RT kernels so it 245 * implicitly prevents bottom half processing as well. 246 */ 247 static void get_cpu_fpsimd_context(void) 248 { 249 if (!IS_ENABLED(CONFIG_PREEMPT_RT)) 250 local_bh_disable(); 251 else 252 preempt_disable(); 253 __get_cpu_fpsimd_context(); 254 } 255 256 static void __put_cpu_fpsimd_context(void) 257 { 258 bool busy = __this_cpu_xchg(fpsimd_context_busy, false); 259 260 WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */ 261 } 262 263 /* 264 * Release the CPU FPSIMD context. 265 * 266 * Must be called from a context in which get_cpu_fpsimd_context() was 267 * previously called, with no call to put_cpu_fpsimd_context() in the 268 * meantime. 269 */ 270 static void put_cpu_fpsimd_context(void) 271 { 272 __put_cpu_fpsimd_context(); 273 if (!IS_ENABLED(CONFIG_PREEMPT_RT)) 274 local_bh_enable(); 275 else 276 preempt_enable(); 277 } 278 279 static bool have_cpu_fpsimd_context(void) 280 { 281 return !preemptible() && __this_cpu_read(fpsimd_context_busy); 282 } 283 284 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type) 285 { 286 return task->thread.vl[type]; 287 } 288 289 void task_set_vl(struct task_struct *task, enum vec_type type, 290 unsigned long vl) 291 { 292 task->thread.vl[type] = vl; 293 } 294 295 unsigned int task_get_vl_onexec(const struct task_struct *task, 296 enum vec_type type) 297 { 298 return task->thread.vl_onexec[type]; 299 } 300 301 void task_set_vl_onexec(struct task_struct *task, enum vec_type type, 302 unsigned long vl) 303 { 304 task->thread.vl_onexec[type] = vl; 305 } 306 307 /* 308 * TIF_SME controls whether a task can use SME without trapping while 309 * in userspace, when TIF_SME is set then we must have storage 310 * alocated in sve_state and za_state to store the contents of both ZA 311 * and the SVE registers for both streaming and non-streaming modes. 312 * 313 * If both SVCR.ZA and SVCR.SM are disabled then at any point we 314 * may disable TIF_SME and reenable traps. 315 */ 316 317 318 /* 319 * TIF_SVE controls whether a task can use SVE without trapping while 320 * in userspace, and also (together with TIF_SME) the way a task's 321 * FPSIMD/SVE state is stored in thread_struct. 322 * 323 * The kernel uses this flag to track whether a user task is actively 324 * using SVE, and therefore whether full SVE register state needs to 325 * be tracked. If not, the cheaper FPSIMD context handling code can 326 * be used instead of the more costly SVE equivalents. 327 * 328 * * TIF_SVE or SVCR.SM set: 329 * 330 * The task can execute SVE instructions while in userspace without 331 * trapping to the kernel. 332 * 333 * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the 334 * corresponding Zn), P0-P15 and FFR are encoded in 335 * task->thread.sve_state, formatted appropriately for vector 336 * length task->thread.sve_vl or, if SVCR.SM is set, 337 * task->thread.sme_vl. 338 * 339 * task->thread.sve_state must point to a valid buffer at least 340 * sve_state_size(task) bytes in size. 341 * 342 * During any syscall, the kernel may optionally clear TIF_SVE and 343 * discard the vector state except for the FPSIMD subset. 344 * 345 * * TIF_SVE clear: 346 * 347 * An attempt by the user task to execute an SVE instruction causes 348 * do_sve_acc() to be called, which does some preparation and then 349 * sets TIF_SVE. 350 * 351 * When stored, FPSIMD registers V0-V31 are encoded in 352 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are 353 * logically zero but not stored anywhere; P0-P15 and FFR are not 354 * stored and have unspecified values from userspace's point of 355 * view. For hygiene purposes, the kernel zeroes them on next use, 356 * but userspace is discouraged from relying on this. 357 * 358 * task->thread.sve_state does not need to be non-NULL, valid or any 359 * particular size: it must not be dereferenced. 360 * 361 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state 362 * irrespective of whether TIF_SVE is clear or set, since these are 363 * not vector length dependent. 364 */ 365 366 /* 367 * Update current's FPSIMD/SVE registers from thread_struct. 368 * 369 * This function should be called only when the FPSIMD/SVE state in 370 * thread_struct is known to be up to date, when preparing to enter 371 * userspace. 372 */ 373 static void task_fpsimd_load(void) 374 { 375 bool restore_sve_regs = false; 376 bool restore_ffr; 377 378 WARN_ON(!system_supports_fpsimd()); 379 WARN_ON(!have_cpu_fpsimd_context()); 380 381 /* Check if we should restore SVE first */ 382 if (IS_ENABLED(CONFIG_ARM64_SVE) && test_thread_flag(TIF_SVE)) { 383 sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1); 384 restore_sve_regs = true; 385 restore_ffr = true; 386 } 387 388 /* Restore SME, override SVE register configuration if needed */ 389 if (system_supports_sme()) { 390 unsigned long sme_vl = task_get_sme_vl(current); 391 392 /* Ensure VL is set up for restoring data */ 393 if (test_thread_flag(TIF_SME)) 394 sme_set_vq(sve_vq_from_vl(sme_vl) - 1); 395 396 write_sysreg_s(current->thread.svcr, SYS_SVCR); 397 398 if (thread_za_enabled(¤t->thread)) 399 za_load_state(current->thread.za_state); 400 401 if (thread_sm_enabled(¤t->thread)) { 402 restore_sve_regs = true; 403 restore_ffr = system_supports_fa64(); 404 } 405 } 406 407 if (restore_sve_regs) 408 sve_load_state(sve_pffr(¤t->thread), 409 ¤t->thread.uw.fpsimd_state.fpsr, 410 restore_ffr); 411 else 412 fpsimd_load_state(¤t->thread.uw.fpsimd_state); 413 } 414 415 /* 416 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to 417 * date with respect to the CPU registers. Note carefully that the 418 * current context is the context last bound to the CPU stored in 419 * last, if KVM is involved this may be the guest VM context rather 420 * than the host thread for the VM pointed to by current. This means 421 * that we must always reference the state storage via last rather 422 * than via current, other than the TIF_ flags which KVM will 423 * carefully maintain for us. 424 */ 425 static void fpsimd_save(void) 426 { 427 struct fpsimd_last_state_struct const *last = 428 this_cpu_ptr(&fpsimd_last_state); 429 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */ 430 bool save_sve_regs = false; 431 bool save_ffr; 432 unsigned int vl; 433 434 WARN_ON(!system_supports_fpsimd()); 435 WARN_ON(!have_cpu_fpsimd_context()); 436 437 if (test_thread_flag(TIF_FOREIGN_FPSTATE)) 438 return; 439 440 if (test_thread_flag(TIF_SVE)) { 441 save_sve_regs = true; 442 save_ffr = true; 443 vl = last->sve_vl; 444 } 445 446 if (system_supports_sme()) { 447 u64 *svcr = last->svcr; 448 449 *svcr = read_sysreg_s(SYS_SVCR); 450 451 if (*svcr & SVCR_ZA_MASK) 452 za_save_state(last->za_state); 453 454 /* If we are in streaming mode override regular SVE. */ 455 if (*svcr & SVCR_SM_MASK) { 456 save_sve_regs = true; 457 save_ffr = system_supports_fa64(); 458 vl = last->sme_vl; 459 } 460 } 461 462 if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) { 463 /* Get the configured VL from RDVL, will account for SM */ 464 if (WARN_ON(sve_get_vl() != vl)) { 465 /* 466 * Can't save the user regs, so current would 467 * re-enter user with corrupt state. 468 * There's no way to recover, so kill it: 469 */ 470 force_signal_inject(SIGKILL, SI_KERNEL, 0, 0); 471 return; 472 } 473 474 sve_save_state((char *)last->sve_state + 475 sve_ffr_offset(vl), 476 &last->st->fpsr, save_ffr); 477 } else { 478 fpsimd_save_state(last->st); 479 } 480 } 481 482 /* 483 * All vector length selection from userspace comes through here. 484 * We're on a slow path, so some sanity-checks are included. 485 * If things go wrong there's a bug somewhere, but try to fall back to a 486 * safe choice. 487 */ 488 static unsigned int find_supported_vector_length(enum vec_type type, 489 unsigned int vl) 490 { 491 struct vl_info *info = &vl_info[type]; 492 int bit; 493 int max_vl = info->max_vl; 494 495 if (WARN_ON(!sve_vl_valid(vl))) 496 vl = info->min_vl; 497 498 if (WARN_ON(!sve_vl_valid(max_vl))) 499 max_vl = info->min_vl; 500 501 if (vl > max_vl) 502 vl = max_vl; 503 if (vl < info->min_vl) 504 vl = info->min_vl; 505 506 bit = find_next_bit(info->vq_map, SVE_VQ_MAX, 507 __vq_to_bit(sve_vq_from_vl(vl))); 508 return sve_vl_from_vq(__bit_to_vq(bit)); 509 } 510 511 #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL) 512 513 static int vec_proc_do_default_vl(struct ctl_table *table, int write, 514 void *buffer, size_t *lenp, loff_t *ppos) 515 { 516 struct vl_info *info = table->extra1; 517 enum vec_type type = info->type; 518 int ret; 519 int vl = get_default_vl(type); 520 struct ctl_table tmp_table = { 521 .data = &vl, 522 .maxlen = sizeof(vl), 523 }; 524 525 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos); 526 if (ret || !write) 527 return ret; 528 529 /* Writing -1 has the special meaning "set to max": */ 530 if (vl == -1) 531 vl = info->max_vl; 532 533 if (!sve_vl_valid(vl)) 534 return -EINVAL; 535 536 set_default_vl(type, find_supported_vector_length(type, vl)); 537 return 0; 538 } 539 540 static struct ctl_table sve_default_vl_table[] = { 541 { 542 .procname = "sve_default_vector_length", 543 .mode = 0644, 544 .proc_handler = vec_proc_do_default_vl, 545 .extra1 = &vl_info[ARM64_VEC_SVE], 546 }, 547 { } 548 }; 549 550 static int __init sve_sysctl_init(void) 551 { 552 if (system_supports_sve()) 553 if (!register_sysctl("abi", sve_default_vl_table)) 554 return -EINVAL; 555 556 return 0; 557 } 558 559 #else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 560 static int __init sve_sysctl_init(void) { return 0; } 561 #endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 562 563 #if defined(CONFIG_ARM64_SME) && defined(CONFIG_SYSCTL) 564 static struct ctl_table sme_default_vl_table[] = { 565 { 566 .procname = "sme_default_vector_length", 567 .mode = 0644, 568 .proc_handler = vec_proc_do_default_vl, 569 .extra1 = &vl_info[ARM64_VEC_SME], 570 }, 571 { } 572 }; 573 574 static int __init sme_sysctl_init(void) 575 { 576 if (system_supports_sme()) 577 if (!register_sysctl("abi", sme_default_vl_table)) 578 return -EINVAL; 579 580 return 0; 581 } 582 583 #else /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */ 584 static int __init sme_sysctl_init(void) { return 0; } 585 #endif /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */ 586 587 #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ 588 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) 589 590 #ifdef CONFIG_CPU_BIG_ENDIAN 591 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 592 { 593 u64 a = swab64(x); 594 u64 b = swab64(x >> 64); 595 596 return ((__uint128_t)a << 64) | b; 597 } 598 #else 599 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 600 { 601 return x; 602 } 603 #endif 604 605 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) 606 607 static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst, 608 unsigned int vq) 609 { 610 unsigned int i; 611 __uint128_t *p; 612 613 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 614 p = (__uint128_t *)ZREG(sst, vq, i); 615 *p = arm64_cpu_to_le128(fst->vregs[i]); 616 } 617 } 618 619 /* 620 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to 621 * task->thread.sve_state. 622 * 623 * Task can be a non-runnable task, or current. In the latter case, 624 * the caller must have ownership of the cpu FPSIMD context before calling 625 * this function. 626 * task->thread.sve_state must point to at least sve_state_size(task) 627 * bytes of allocated kernel memory. 628 * task->thread.uw.fpsimd_state must be up to date before calling this 629 * function. 630 */ 631 static void fpsimd_to_sve(struct task_struct *task) 632 { 633 unsigned int vq; 634 void *sst = task->thread.sve_state; 635 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 636 637 if (!system_supports_sve()) 638 return; 639 640 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); 641 __fpsimd_to_sve(sst, fst, vq); 642 } 643 644 /* 645 * Transfer the SVE state in task->thread.sve_state to 646 * task->thread.uw.fpsimd_state. 647 * 648 * Task can be a non-runnable task, or current. In the latter case, 649 * the caller must have ownership of the cpu FPSIMD context before calling 650 * this function. 651 * task->thread.sve_state must point to at least sve_state_size(task) 652 * bytes of allocated kernel memory. 653 * task->thread.sve_state must be up to date before calling this function. 654 */ 655 static void sve_to_fpsimd(struct task_struct *task) 656 { 657 unsigned int vq, vl; 658 void const *sst = task->thread.sve_state; 659 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state; 660 unsigned int i; 661 __uint128_t const *p; 662 663 if (!system_supports_sve()) 664 return; 665 666 vl = thread_get_cur_vl(&task->thread); 667 vq = sve_vq_from_vl(vl); 668 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 669 p = (__uint128_t const *)ZREG(sst, vq, i); 670 fst->vregs[i] = arm64_le128_to_cpu(*p); 671 } 672 } 673 674 #ifdef CONFIG_ARM64_SVE 675 /* 676 * Call __sve_free() directly only if you know task can't be scheduled 677 * or preempted. 678 */ 679 static void __sve_free(struct task_struct *task) 680 { 681 kfree(task->thread.sve_state); 682 task->thread.sve_state = NULL; 683 } 684 685 static void sve_free(struct task_struct *task) 686 { 687 WARN_ON(test_tsk_thread_flag(task, TIF_SVE)); 688 689 __sve_free(task); 690 } 691 692 /* 693 * Return how many bytes of memory are required to store the full SVE 694 * state for task, given task's currently configured vector length. 695 */ 696 size_t sve_state_size(struct task_struct const *task) 697 { 698 unsigned int vl = 0; 699 700 if (system_supports_sve()) 701 vl = task_get_sve_vl(task); 702 if (system_supports_sme()) 703 vl = max(vl, task_get_sme_vl(task)); 704 705 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)); 706 } 707 708 /* 709 * Ensure that task->thread.sve_state is allocated and sufficiently large. 710 * 711 * This function should be used only in preparation for replacing 712 * task->thread.sve_state with new data. The memory is always zeroed 713 * here to prevent stale data from showing through: this is done in 714 * the interest of testability and predictability: except in the 715 * do_sve_acc() case, there is no ABI requirement to hide stale data 716 * written previously be task. 717 */ 718 void sve_alloc(struct task_struct *task) 719 { 720 if (task->thread.sve_state) { 721 memset(task->thread.sve_state, 0, sve_state_size(task)); 722 return; 723 } 724 725 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */ 726 task->thread.sve_state = 727 kzalloc(sve_state_size(task), GFP_KERNEL); 728 } 729 730 731 /* 732 * Force the FPSIMD state shared with SVE to be updated in the SVE state 733 * even if the SVE state is the current active state. 734 * 735 * This should only be called by ptrace. task must be non-runnable. 736 * task->thread.sve_state must point to at least sve_state_size(task) 737 * bytes of allocated kernel memory. 738 */ 739 void fpsimd_force_sync_to_sve(struct task_struct *task) 740 { 741 fpsimd_to_sve(task); 742 } 743 744 /* 745 * Ensure that task->thread.sve_state is up to date with respect to 746 * the user task, irrespective of when SVE is in use or not. 747 * 748 * This should only be called by ptrace. task must be non-runnable. 749 * task->thread.sve_state must point to at least sve_state_size(task) 750 * bytes of allocated kernel memory. 751 */ 752 void fpsimd_sync_to_sve(struct task_struct *task) 753 { 754 if (!test_tsk_thread_flag(task, TIF_SVE) && 755 !thread_sm_enabled(&task->thread)) 756 fpsimd_to_sve(task); 757 } 758 759 /* 760 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to 761 * the user task, irrespective of whether SVE is in use or not. 762 * 763 * This should only be called by ptrace. task must be non-runnable. 764 * task->thread.sve_state must point to at least sve_state_size(task) 765 * bytes of allocated kernel memory. 766 */ 767 void sve_sync_to_fpsimd(struct task_struct *task) 768 { 769 if (test_tsk_thread_flag(task, TIF_SVE) || 770 thread_sm_enabled(&task->thread)) 771 sve_to_fpsimd(task); 772 } 773 774 /* 775 * Ensure that task->thread.sve_state is up to date with respect to 776 * the task->thread.uw.fpsimd_state. 777 * 778 * This should only be called by ptrace to merge new FPSIMD register 779 * values into a task for which SVE is currently active. 780 * task must be non-runnable. 781 * task->thread.sve_state must point to at least sve_state_size(task) 782 * bytes of allocated kernel memory. 783 * task->thread.uw.fpsimd_state must already have been initialised with 784 * the new FPSIMD register values to be merged in. 785 */ 786 void sve_sync_from_fpsimd_zeropad(struct task_struct *task) 787 { 788 unsigned int vq; 789 void *sst = task->thread.sve_state; 790 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 791 792 if (!test_tsk_thread_flag(task, TIF_SVE)) 793 return; 794 795 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); 796 797 memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); 798 __fpsimd_to_sve(sst, fst, vq); 799 } 800 801 int vec_set_vector_length(struct task_struct *task, enum vec_type type, 802 unsigned long vl, unsigned long flags) 803 { 804 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | 805 PR_SVE_SET_VL_ONEXEC)) 806 return -EINVAL; 807 808 if (!sve_vl_valid(vl)) 809 return -EINVAL; 810 811 /* 812 * Clamp to the maximum vector length that VL-agnostic code 813 * can work with. A flag may be assigned in the future to 814 * allow setting of larger vector lengths without confusing 815 * older software. 816 */ 817 if (vl > VL_ARCH_MAX) 818 vl = VL_ARCH_MAX; 819 820 vl = find_supported_vector_length(type, vl); 821 822 if (flags & (PR_SVE_VL_INHERIT | 823 PR_SVE_SET_VL_ONEXEC)) 824 task_set_vl_onexec(task, type, vl); 825 else 826 /* Reset VL to system default on next exec: */ 827 task_set_vl_onexec(task, type, 0); 828 829 /* Only actually set the VL if not deferred: */ 830 if (flags & PR_SVE_SET_VL_ONEXEC) 831 goto out; 832 833 if (vl == task_get_vl(task, type)) 834 goto out; 835 836 /* 837 * To ensure the FPSIMD bits of the SVE vector registers are preserved, 838 * write any live register state back to task_struct, and convert to a 839 * regular FPSIMD thread. 840 */ 841 if (task == current) { 842 get_cpu_fpsimd_context(); 843 844 fpsimd_save(); 845 } 846 847 fpsimd_flush_task_state(task); 848 if (test_and_clear_tsk_thread_flag(task, TIF_SVE) || 849 thread_sm_enabled(&task->thread)) 850 sve_to_fpsimd(task); 851 852 if (system_supports_sme() && type == ARM64_VEC_SME) { 853 task->thread.svcr &= ~(SVCR_SM_MASK | 854 SVCR_ZA_MASK); 855 clear_thread_flag(TIF_SME); 856 } 857 858 if (task == current) 859 put_cpu_fpsimd_context(); 860 861 /* 862 * Force reallocation of task SVE and SME state to the correct 863 * size on next use: 864 */ 865 sve_free(task); 866 if (system_supports_sme() && type == ARM64_VEC_SME) 867 sme_free(task); 868 869 task_set_vl(task, type, vl); 870 871 out: 872 update_tsk_thread_flag(task, vec_vl_inherit_flag(type), 873 flags & PR_SVE_VL_INHERIT); 874 875 return 0; 876 } 877 878 /* 879 * Encode the current vector length and flags for return. 880 * This is only required for prctl(): ptrace has separate fields. 881 * SVE and SME use the same bits for _ONEXEC and _INHERIT. 882 * 883 * flags are as for vec_set_vector_length(). 884 */ 885 static int vec_prctl_status(enum vec_type type, unsigned long flags) 886 { 887 int ret; 888 889 if (flags & PR_SVE_SET_VL_ONEXEC) 890 ret = task_get_vl_onexec(current, type); 891 else 892 ret = task_get_vl(current, type); 893 894 if (test_thread_flag(vec_vl_inherit_flag(type))) 895 ret |= PR_SVE_VL_INHERIT; 896 897 return ret; 898 } 899 900 /* PR_SVE_SET_VL */ 901 int sve_set_current_vl(unsigned long arg) 902 { 903 unsigned long vl, flags; 904 int ret; 905 906 vl = arg & PR_SVE_VL_LEN_MASK; 907 flags = arg & ~vl; 908 909 if (!system_supports_sve() || is_compat_task()) 910 return -EINVAL; 911 912 ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags); 913 if (ret) 914 return ret; 915 916 return vec_prctl_status(ARM64_VEC_SVE, flags); 917 } 918 919 /* PR_SVE_GET_VL */ 920 int sve_get_current_vl(void) 921 { 922 if (!system_supports_sve() || is_compat_task()) 923 return -EINVAL; 924 925 return vec_prctl_status(ARM64_VEC_SVE, 0); 926 } 927 928 #ifdef CONFIG_ARM64_SME 929 /* PR_SME_SET_VL */ 930 int sme_set_current_vl(unsigned long arg) 931 { 932 unsigned long vl, flags; 933 int ret; 934 935 vl = arg & PR_SME_VL_LEN_MASK; 936 flags = arg & ~vl; 937 938 if (!system_supports_sme() || is_compat_task()) 939 return -EINVAL; 940 941 ret = vec_set_vector_length(current, ARM64_VEC_SME, vl, flags); 942 if (ret) 943 return ret; 944 945 return vec_prctl_status(ARM64_VEC_SME, flags); 946 } 947 948 /* PR_SME_GET_VL */ 949 int sme_get_current_vl(void) 950 { 951 if (!system_supports_sme() || is_compat_task()) 952 return -EINVAL; 953 954 return vec_prctl_status(ARM64_VEC_SME, 0); 955 } 956 #endif /* CONFIG_ARM64_SME */ 957 958 static void vec_probe_vqs(struct vl_info *info, 959 DECLARE_BITMAP(map, SVE_VQ_MAX)) 960 { 961 unsigned int vq, vl; 962 963 bitmap_zero(map, SVE_VQ_MAX); 964 965 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) { 966 write_vl(info->type, vq - 1); /* self-syncing */ 967 968 switch (info->type) { 969 case ARM64_VEC_SVE: 970 vl = sve_get_vl(); 971 break; 972 case ARM64_VEC_SME: 973 vl = sme_get_vl(); 974 break; 975 default: 976 vl = 0; 977 break; 978 } 979 980 /* Minimum VL identified? */ 981 if (sve_vq_from_vl(vl) > vq) 982 break; 983 984 vq = sve_vq_from_vl(vl); /* skip intervening lengths */ 985 set_bit(__vq_to_bit(vq), map); 986 } 987 } 988 989 /* 990 * Initialise the set of known supported VQs for the boot CPU. 991 * This is called during kernel boot, before secondary CPUs are brought up. 992 */ 993 void __init vec_init_vq_map(enum vec_type type) 994 { 995 struct vl_info *info = &vl_info[type]; 996 vec_probe_vqs(info, info->vq_map); 997 bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX); 998 } 999 1000 /* 1001 * If we haven't committed to the set of supported VQs yet, filter out 1002 * those not supported by the current CPU. 1003 * This function is called during the bring-up of early secondary CPUs only. 1004 */ 1005 void vec_update_vq_map(enum vec_type type) 1006 { 1007 struct vl_info *info = &vl_info[type]; 1008 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1009 1010 vec_probe_vqs(info, tmp_map); 1011 bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX); 1012 bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map, 1013 SVE_VQ_MAX); 1014 } 1015 1016 /* 1017 * Check whether the current CPU supports all VQs in the committed set. 1018 * This function is called during the bring-up of late secondary CPUs only. 1019 */ 1020 int vec_verify_vq_map(enum vec_type type) 1021 { 1022 struct vl_info *info = &vl_info[type]; 1023 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1024 unsigned long b; 1025 1026 vec_probe_vqs(info, tmp_map); 1027 1028 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 1029 if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) { 1030 pr_warn("%s: cpu%d: Required vector length(s) missing\n", 1031 info->name, smp_processor_id()); 1032 return -EINVAL; 1033 } 1034 1035 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) 1036 return 0; 1037 1038 /* 1039 * For KVM, it is necessary to ensure that this CPU doesn't 1040 * support any vector length that guests may have probed as 1041 * unsupported. 1042 */ 1043 1044 /* Recover the set of supported VQs: */ 1045 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 1046 /* Find VQs supported that are not globally supported: */ 1047 bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX); 1048 1049 /* Find the lowest such VQ, if any: */ 1050 b = find_last_bit(tmp_map, SVE_VQ_MAX); 1051 if (b >= SVE_VQ_MAX) 1052 return 0; /* no mismatches */ 1053 1054 /* 1055 * Mismatches above sve_max_virtualisable_vl are fine, since 1056 * no guest is allowed to configure ZCR_EL2.LEN to exceed this: 1057 */ 1058 if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) { 1059 pr_warn("%s: cpu%d: Unsupported vector length(s) present\n", 1060 info->name, smp_processor_id()); 1061 return -EINVAL; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static void __init sve_efi_setup(void) 1068 { 1069 int max_vl = 0; 1070 int i; 1071 1072 if (!IS_ENABLED(CONFIG_EFI)) 1073 return; 1074 1075 for (i = 0; i < ARRAY_SIZE(vl_info); i++) 1076 max_vl = max(vl_info[i].max_vl, max_vl); 1077 1078 /* 1079 * alloc_percpu() warns and prints a backtrace if this goes wrong. 1080 * This is evidence of a crippled system and we are returning void, 1081 * so no attempt is made to handle this situation here. 1082 */ 1083 if (!sve_vl_valid(max_vl)) 1084 goto fail; 1085 1086 efi_sve_state = __alloc_percpu( 1087 SVE_SIG_REGS_SIZE(sve_vq_from_vl(max_vl)), SVE_VQ_BYTES); 1088 if (!efi_sve_state) 1089 goto fail; 1090 1091 return; 1092 1093 fail: 1094 panic("Cannot allocate percpu memory for EFI SVE save/restore"); 1095 } 1096 1097 /* 1098 * Enable SVE for EL1. 1099 * Intended for use by the cpufeatures code during CPU boot. 1100 */ 1101 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1102 { 1103 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); 1104 isb(); 1105 } 1106 1107 /* 1108 * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE 1109 * vector length. 1110 * 1111 * Use only if SVE is present. 1112 * This function clobbers the SVE vector length. 1113 */ 1114 u64 read_zcr_features(void) 1115 { 1116 u64 zcr; 1117 unsigned int vq_max; 1118 1119 /* 1120 * Set the maximum possible VL, and write zeroes to all other 1121 * bits to see if they stick. 1122 */ 1123 sve_kernel_enable(NULL); 1124 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); 1125 1126 zcr = read_sysreg_s(SYS_ZCR_EL1); 1127 zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ 1128 vq_max = sve_vq_from_vl(sve_get_vl()); 1129 zcr |= vq_max - 1; /* set LEN field to maximum effective value */ 1130 1131 return zcr; 1132 } 1133 1134 void __init sve_setup(void) 1135 { 1136 struct vl_info *info = &vl_info[ARM64_VEC_SVE]; 1137 u64 zcr; 1138 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1139 unsigned long b; 1140 1141 if (!system_supports_sve()) 1142 return; 1143 1144 /* 1145 * The SVE architecture mandates support for 128-bit vectors, 1146 * so sve_vq_map must have at least SVE_VQ_MIN set. 1147 * If something went wrong, at least try to patch it up: 1148 */ 1149 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map))) 1150 set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map); 1151 1152 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 1153 info->max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1); 1154 1155 /* 1156 * Sanity-check that the max VL we determined through CPU features 1157 * corresponds properly to sve_vq_map. If not, do our best: 1158 */ 1159 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SVE, 1160 info->max_vl))) 1161 info->max_vl = find_supported_vector_length(ARM64_VEC_SVE, 1162 info->max_vl); 1163 1164 /* 1165 * For the default VL, pick the maximum supported value <= 64. 1166 * VL == 64 is guaranteed not to grow the signal frame. 1167 */ 1168 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64)); 1169 1170 bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map, 1171 SVE_VQ_MAX); 1172 1173 b = find_last_bit(tmp_map, SVE_VQ_MAX); 1174 if (b >= SVE_VQ_MAX) 1175 /* No non-virtualisable VLs found */ 1176 info->max_virtualisable_vl = SVE_VQ_MAX; 1177 else if (WARN_ON(b == SVE_VQ_MAX - 1)) 1178 /* No virtualisable VLs? This is architecturally forbidden. */ 1179 info->max_virtualisable_vl = SVE_VQ_MIN; 1180 else /* b + 1 < SVE_VQ_MAX */ 1181 info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1)); 1182 1183 if (info->max_virtualisable_vl > info->max_vl) 1184 info->max_virtualisable_vl = info->max_vl; 1185 1186 pr_info("%s: maximum available vector length %u bytes per vector\n", 1187 info->name, info->max_vl); 1188 pr_info("%s: default vector length %u bytes per vector\n", 1189 info->name, get_sve_default_vl()); 1190 1191 /* KVM decides whether to support mismatched systems. Just warn here: */ 1192 if (sve_max_virtualisable_vl() < sve_max_vl()) 1193 pr_warn("%s: unvirtualisable vector lengths present\n", 1194 info->name); 1195 1196 sve_efi_setup(); 1197 } 1198 1199 /* 1200 * Called from the put_task_struct() path, which cannot get here 1201 * unless dead_task is really dead and not schedulable. 1202 */ 1203 void fpsimd_release_task(struct task_struct *dead_task) 1204 { 1205 __sve_free(dead_task); 1206 sme_free(dead_task); 1207 } 1208 1209 #endif /* CONFIG_ARM64_SVE */ 1210 1211 #ifdef CONFIG_ARM64_SME 1212 1213 /* 1214 * Ensure that task->thread.za_state is allocated and sufficiently large. 1215 * 1216 * This function should be used only in preparation for replacing 1217 * task->thread.za_state with new data. The memory is always zeroed 1218 * here to prevent stale data from showing through: this is done in 1219 * the interest of testability and predictability, the architecture 1220 * guarantees that when ZA is enabled it will be zeroed. 1221 */ 1222 void sme_alloc(struct task_struct *task) 1223 { 1224 if (task->thread.za_state) { 1225 memset(task->thread.za_state, 0, za_state_size(task)); 1226 return; 1227 } 1228 1229 /* This could potentially be up to 64K. */ 1230 task->thread.za_state = 1231 kzalloc(za_state_size(task), GFP_KERNEL); 1232 } 1233 1234 static void sme_free(struct task_struct *task) 1235 { 1236 kfree(task->thread.za_state); 1237 task->thread.za_state = NULL; 1238 } 1239 1240 void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1241 { 1242 /* Set priority for all PEs to architecturally defined minimum */ 1243 write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK, 1244 SYS_SMPRI_EL1); 1245 1246 /* Allow SME in kernel */ 1247 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1); 1248 isb(); 1249 1250 /* Allow EL0 to access TPIDR2 */ 1251 write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1); 1252 isb(); 1253 } 1254 1255 /* 1256 * This must be called after sme_kernel_enable(), we rely on the 1257 * feature table being sorted to ensure this. 1258 */ 1259 void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1260 { 1261 /* Allow use of FA64 */ 1262 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK, 1263 SYS_SMCR_EL1); 1264 } 1265 1266 /* 1267 * Read the pseudo-SMCR used by cpufeatures to identify the supported 1268 * vector length. 1269 * 1270 * Use only if SME is present. 1271 * This function clobbers the SME vector length. 1272 */ 1273 u64 read_smcr_features(void) 1274 { 1275 u64 smcr; 1276 unsigned int vq_max; 1277 1278 sme_kernel_enable(NULL); 1279 sme_smstart_sm(); 1280 1281 /* 1282 * Set the maximum possible VL. 1283 */ 1284 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK, 1285 SYS_SMCR_EL1); 1286 1287 smcr = read_sysreg_s(SYS_SMCR_EL1); 1288 smcr &= ~(u64)SMCR_ELx_LEN_MASK; /* Only the LEN field */ 1289 vq_max = sve_vq_from_vl(sve_get_vl()); 1290 smcr |= vq_max - 1; /* set LEN field to maximum effective value */ 1291 1292 sme_smstop_sm(); 1293 1294 return smcr; 1295 } 1296 1297 void __init sme_setup(void) 1298 { 1299 struct vl_info *info = &vl_info[ARM64_VEC_SME]; 1300 u64 smcr; 1301 int min_bit; 1302 1303 if (!system_supports_sme()) 1304 return; 1305 1306 /* 1307 * SME doesn't require any particular vector length be 1308 * supported but it does require at least one. We should have 1309 * disabled the feature entirely while bringing up CPUs but 1310 * let's double check here. 1311 */ 1312 WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX)); 1313 1314 min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX); 1315 info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit)); 1316 1317 smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 1318 info->max_vl = sve_vl_from_vq((smcr & SMCR_ELx_LEN_MASK) + 1); 1319 1320 /* 1321 * Sanity-check that the max VL we determined through CPU features 1322 * corresponds properly to sme_vq_map. If not, do our best: 1323 */ 1324 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SME, 1325 info->max_vl))) 1326 info->max_vl = find_supported_vector_length(ARM64_VEC_SME, 1327 info->max_vl); 1328 1329 WARN_ON(info->min_vl > info->max_vl); 1330 1331 /* 1332 * For the default VL, pick the maximum supported value <= 32 1333 * (256 bits) if there is one since this is guaranteed not to 1334 * grow the signal frame when in streaming mode, otherwise the 1335 * minimum available VL will be used. 1336 */ 1337 set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32)); 1338 1339 pr_info("SME: minimum available vector length %u bytes per vector\n", 1340 info->min_vl); 1341 pr_info("SME: maximum available vector length %u bytes per vector\n", 1342 info->max_vl); 1343 pr_info("SME: default vector length %u bytes per vector\n", 1344 get_sme_default_vl()); 1345 } 1346 1347 #endif /* CONFIG_ARM64_SME */ 1348 1349 static void sve_init_regs(void) 1350 { 1351 /* 1352 * Convert the FPSIMD state to SVE, zeroing all the state that 1353 * is not shared with FPSIMD. If (as is likely) the current 1354 * state is live in the registers then do this there and 1355 * update our metadata for the current task including 1356 * disabling the trap, otherwise update our in-memory copy. 1357 * We are guaranteed to not be in streaming mode, we can only 1358 * take a SVE trap when not in streaming mode and we can't be 1359 * in streaming mode when taking a SME trap. 1360 */ 1361 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 1362 unsigned long vq_minus_one = 1363 sve_vq_from_vl(task_get_sve_vl(current)) - 1; 1364 sve_set_vq(vq_minus_one); 1365 sve_flush_live(true, vq_minus_one); 1366 fpsimd_bind_task_to_cpu(); 1367 } else { 1368 fpsimd_to_sve(current); 1369 } 1370 } 1371 1372 /* 1373 * Trapped SVE access 1374 * 1375 * Storage is allocated for the full SVE state, the current FPSIMD 1376 * register contents are migrated across, and the access trap is 1377 * disabled. 1378 * 1379 * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state() 1380 * would have disabled the SVE access trap for userspace during 1381 * ret_to_user, making an SVE access trap impossible in that case. 1382 */ 1383 void do_sve_acc(unsigned long esr, struct pt_regs *regs) 1384 { 1385 /* Even if we chose not to use SVE, the hardware could still trap: */ 1386 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) { 1387 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1388 return; 1389 } 1390 1391 sve_alloc(current); 1392 if (!current->thread.sve_state) { 1393 force_sig(SIGKILL); 1394 return; 1395 } 1396 1397 get_cpu_fpsimd_context(); 1398 1399 if (test_and_set_thread_flag(TIF_SVE)) 1400 WARN_ON(1); /* SVE access shouldn't have trapped */ 1401 1402 /* 1403 * Even if the task can have used streaming mode we can only 1404 * generate SVE access traps in normal SVE mode and 1405 * transitioning out of streaming mode may discard any 1406 * streaming mode state. Always clear the high bits to avoid 1407 * any potential errors tracking what is properly initialised. 1408 */ 1409 sve_init_regs(); 1410 1411 put_cpu_fpsimd_context(); 1412 } 1413 1414 /* 1415 * Trapped SME access 1416 * 1417 * Storage is allocated for the full SVE and SME state, the current 1418 * FPSIMD register contents are migrated to SVE if SVE is not already 1419 * active, and the access trap is disabled. 1420 * 1421 * TIF_SME should be clear on entry: otherwise, fpsimd_restore_current_state() 1422 * would have disabled the SME access trap for userspace during 1423 * ret_to_user, making an SVE access trap impossible in that case. 1424 */ 1425 void do_sme_acc(unsigned long esr, struct pt_regs *regs) 1426 { 1427 /* Even if we chose not to use SME, the hardware could still trap: */ 1428 if (unlikely(!system_supports_sme()) || WARN_ON(is_compat_task())) { 1429 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1430 return; 1431 } 1432 1433 /* 1434 * If this not a trap due to SME being disabled then something 1435 * is being used in the wrong mode, report as SIGILL. 1436 */ 1437 if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) { 1438 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1439 return; 1440 } 1441 1442 sve_alloc(current); 1443 sme_alloc(current); 1444 if (!current->thread.sve_state || !current->thread.za_state) { 1445 force_sig(SIGKILL); 1446 return; 1447 } 1448 1449 get_cpu_fpsimd_context(); 1450 1451 /* With TIF_SME userspace shouldn't generate any traps */ 1452 if (test_and_set_thread_flag(TIF_SME)) 1453 WARN_ON(1); 1454 1455 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 1456 unsigned long vq_minus_one = 1457 sve_vq_from_vl(task_get_sme_vl(current)) - 1; 1458 sme_set_vq(vq_minus_one); 1459 1460 fpsimd_bind_task_to_cpu(); 1461 } 1462 1463 /* 1464 * If SVE was not already active initialise the SVE registers, 1465 * any non-shared state between the streaming and regular SVE 1466 * registers is architecturally guaranteed to be zeroed when 1467 * we enter streaming mode. We do not need to initialize ZA 1468 * since ZA must be disabled at this point and enabling ZA is 1469 * architecturally defined to zero ZA. 1470 */ 1471 if (system_supports_sve() && !test_thread_flag(TIF_SVE)) 1472 sve_init_regs(); 1473 1474 put_cpu_fpsimd_context(); 1475 } 1476 1477 /* 1478 * Trapped FP/ASIMD access. 1479 */ 1480 void do_fpsimd_acc(unsigned long esr, struct pt_regs *regs) 1481 { 1482 /* TODO: implement lazy context saving/restoring */ 1483 WARN_ON(1); 1484 } 1485 1486 /* 1487 * Raise a SIGFPE for the current process. 1488 */ 1489 void do_fpsimd_exc(unsigned long esr, struct pt_regs *regs) 1490 { 1491 unsigned int si_code = FPE_FLTUNK; 1492 1493 if (esr & ESR_ELx_FP_EXC_TFV) { 1494 if (esr & FPEXC_IOF) 1495 si_code = FPE_FLTINV; 1496 else if (esr & FPEXC_DZF) 1497 si_code = FPE_FLTDIV; 1498 else if (esr & FPEXC_OFF) 1499 si_code = FPE_FLTOVF; 1500 else if (esr & FPEXC_UFF) 1501 si_code = FPE_FLTUND; 1502 else if (esr & FPEXC_IXF) 1503 si_code = FPE_FLTRES; 1504 } 1505 1506 send_sig_fault(SIGFPE, si_code, 1507 (void __user *)instruction_pointer(regs), 1508 current); 1509 } 1510 1511 void fpsimd_thread_switch(struct task_struct *next) 1512 { 1513 bool wrong_task, wrong_cpu; 1514 1515 if (!system_supports_fpsimd()) 1516 return; 1517 1518 __get_cpu_fpsimd_context(); 1519 1520 /* Save unsaved fpsimd state, if any: */ 1521 fpsimd_save(); 1522 1523 /* 1524 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's 1525 * state. For kernel threads, FPSIMD registers are never loaded 1526 * and wrong_task and wrong_cpu will always be true. 1527 */ 1528 wrong_task = __this_cpu_read(fpsimd_last_state.st) != 1529 &next->thread.uw.fpsimd_state; 1530 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id(); 1531 1532 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE, 1533 wrong_task || wrong_cpu); 1534 1535 __put_cpu_fpsimd_context(); 1536 } 1537 1538 static void fpsimd_flush_thread_vl(enum vec_type type) 1539 { 1540 int vl, supported_vl; 1541 1542 /* 1543 * Reset the task vector length as required. This is where we 1544 * ensure that all user tasks have a valid vector length 1545 * configured: no kernel task can become a user task without 1546 * an exec and hence a call to this function. By the time the 1547 * first call to this function is made, all early hardware 1548 * probing is complete, so __sve_default_vl should be valid. 1549 * If a bug causes this to go wrong, we make some noise and 1550 * try to fudge thread.sve_vl to a safe value here. 1551 */ 1552 vl = task_get_vl_onexec(current, type); 1553 if (!vl) 1554 vl = get_default_vl(type); 1555 1556 if (WARN_ON(!sve_vl_valid(vl))) 1557 vl = vl_info[type].min_vl; 1558 1559 supported_vl = find_supported_vector_length(type, vl); 1560 if (WARN_ON(supported_vl != vl)) 1561 vl = supported_vl; 1562 1563 task_set_vl(current, type, vl); 1564 1565 /* 1566 * If the task is not set to inherit, ensure that the vector 1567 * length will be reset by a subsequent exec: 1568 */ 1569 if (!test_thread_flag(vec_vl_inherit_flag(type))) 1570 task_set_vl_onexec(current, type, 0); 1571 } 1572 1573 void fpsimd_flush_thread(void) 1574 { 1575 void *sve_state = NULL; 1576 void *za_state = NULL; 1577 1578 if (!system_supports_fpsimd()) 1579 return; 1580 1581 get_cpu_fpsimd_context(); 1582 1583 fpsimd_flush_task_state(current); 1584 memset(¤t->thread.uw.fpsimd_state, 0, 1585 sizeof(current->thread.uw.fpsimd_state)); 1586 1587 if (system_supports_sve()) { 1588 clear_thread_flag(TIF_SVE); 1589 1590 /* Defer kfree() while in atomic context */ 1591 sve_state = current->thread.sve_state; 1592 current->thread.sve_state = NULL; 1593 1594 fpsimd_flush_thread_vl(ARM64_VEC_SVE); 1595 } 1596 1597 if (system_supports_sme()) { 1598 clear_thread_flag(TIF_SME); 1599 1600 /* Defer kfree() while in atomic context */ 1601 za_state = current->thread.za_state; 1602 current->thread.za_state = NULL; 1603 1604 fpsimd_flush_thread_vl(ARM64_VEC_SME); 1605 current->thread.svcr = 0; 1606 } 1607 1608 put_cpu_fpsimd_context(); 1609 kfree(sve_state); 1610 kfree(za_state); 1611 } 1612 1613 /* 1614 * Save the userland FPSIMD state of 'current' to memory, but only if the state 1615 * currently held in the registers does in fact belong to 'current' 1616 */ 1617 void fpsimd_preserve_current_state(void) 1618 { 1619 if (!system_supports_fpsimd()) 1620 return; 1621 1622 get_cpu_fpsimd_context(); 1623 fpsimd_save(); 1624 put_cpu_fpsimd_context(); 1625 } 1626 1627 /* 1628 * Like fpsimd_preserve_current_state(), but ensure that 1629 * current->thread.uw.fpsimd_state is updated so that it can be copied to 1630 * the signal frame. 1631 */ 1632 void fpsimd_signal_preserve_current_state(void) 1633 { 1634 fpsimd_preserve_current_state(); 1635 if (test_thread_flag(TIF_SVE)) 1636 sve_to_fpsimd(current); 1637 } 1638 1639 /* 1640 * Associate current's FPSIMD context with this cpu 1641 * The caller must have ownership of the cpu FPSIMD context before calling 1642 * this function. 1643 */ 1644 static void fpsimd_bind_task_to_cpu(void) 1645 { 1646 struct fpsimd_last_state_struct *last = 1647 this_cpu_ptr(&fpsimd_last_state); 1648 1649 WARN_ON(!system_supports_fpsimd()); 1650 last->st = ¤t->thread.uw.fpsimd_state; 1651 last->sve_state = current->thread.sve_state; 1652 last->za_state = current->thread.za_state; 1653 last->sve_vl = task_get_sve_vl(current); 1654 last->sme_vl = task_get_sme_vl(current); 1655 last->svcr = ¤t->thread.svcr; 1656 current->thread.fpsimd_cpu = smp_processor_id(); 1657 1658 /* 1659 * Toggle SVE and SME trapping for userspace if needed, these 1660 * are serialsied by ret_to_user(). 1661 */ 1662 if (system_supports_sme()) { 1663 if (test_thread_flag(TIF_SME)) 1664 sme_user_enable(); 1665 else 1666 sme_user_disable(); 1667 } 1668 1669 if (system_supports_sve()) { 1670 if (test_thread_flag(TIF_SVE)) 1671 sve_user_enable(); 1672 else 1673 sve_user_disable(); 1674 } 1675 } 1676 1677 void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, 1678 unsigned int sve_vl, void *za_state, 1679 unsigned int sme_vl, u64 *svcr) 1680 { 1681 struct fpsimd_last_state_struct *last = 1682 this_cpu_ptr(&fpsimd_last_state); 1683 1684 WARN_ON(!system_supports_fpsimd()); 1685 WARN_ON(!in_softirq() && !irqs_disabled()); 1686 1687 last->st = st; 1688 last->svcr = svcr; 1689 last->sve_state = sve_state; 1690 last->za_state = za_state; 1691 last->sve_vl = sve_vl; 1692 last->sme_vl = sme_vl; 1693 } 1694 1695 /* 1696 * Load the userland FPSIMD state of 'current' from memory, but only if the 1697 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD 1698 * state of 'current'. This is called when we are preparing to return to 1699 * userspace to ensure that userspace sees a good register state. 1700 */ 1701 void fpsimd_restore_current_state(void) 1702 { 1703 /* 1704 * For the tasks that were created before we detected the absence of 1705 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(), 1706 * e.g, init. This could be then inherited by the children processes. 1707 * If we later detect that the system doesn't support FP/SIMD, 1708 * we must clear the flag for all the tasks to indicate that the 1709 * FPSTATE is clean (as we can't have one) to avoid looping for ever in 1710 * do_notify_resume(). 1711 */ 1712 if (!system_supports_fpsimd()) { 1713 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1714 return; 1715 } 1716 1717 get_cpu_fpsimd_context(); 1718 1719 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { 1720 task_fpsimd_load(); 1721 fpsimd_bind_task_to_cpu(); 1722 } 1723 1724 put_cpu_fpsimd_context(); 1725 } 1726 1727 /* 1728 * Load an updated userland FPSIMD state for 'current' from memory and set the 1729 * flag that indicates that the FPSIMD register contents are the most recent 1730 * FPSIMD state of 'current'. This is used by the signal code to restore the 1731 * register state when returning from a signal handler in FPSIMD only cases, 1732 * any SVE context will be discarded. 1733 */ 1734 void fpsimd_update_current_state(struct user_fpsimd_state const *state) 1735 { 1736 if (WARN_ON(!system_supports_fpsimd())) 1737 return; 1738 1739 get_cpu_fpsimd_context(); 1740 1741 current->thread.uw.fpsimd_state = *state; 1742 if (test_thread_flag(TIF_SVE)) 1743 fpsimd_to_sve(current); 1744 1745 task_fpsimd_load(); 1746 fpsimd_bind_task_to_cpu(); 1747 1748 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1749 1750 put_cpu_fpsimd_context(); 1751 } 1752 1753 /* 1754 * Invalidate live CPU copies of task t's FPSIMD state 1755 * 1756 * This function may be called with preemption enabled. The barrier() 1757 * ensures that the assignment to fpsimd_cpu is visible to any 1758 * preemption/softirq that could race with set_tsk_thread_flag(), so 1759 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared. 1760 * 1761 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any 1762 * subsequent code. 1763 */ 1764 void fpsimd_flush_task_state(struct task_struct *t) 1765 { 1766 t->thread.fpsimd_cpu = NR_CPUS; 1767 /* 1768 * If we don't support fpsimd, bail out after we have 1769 * reset the fpsimd_cpu for this task and clear the 1770 * FPSTATE. 1771 */ 1772 if (!system_supports_fpsimd()) 1773 return; 1774 barrier(); 1775 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE); 1776 1777 barrier(); 1778 } 1779 1780 /* 1781 * Invalidate any task's FPSIMD state that is present on this cpu. 1782 * The FPSIMD context should be acquired with get_cpu_fpsimd_context() 1783 * before calling this function. 1784 */ 1785 static void fpsimd_flush_cpu_state(void) 1786 { 1787 WARN_ON(!system_supports_fpsimd()); 1788 __this_cpu_write(fpsimd_last_state.st, NULL); 1789 1790 /* 1791 * Leaving streaming mode enabled will cause issues for any kernel 1792 * NEON and leaving streaming mode or ZA enabled may increase power 1793 * consumption. 1794 */ 1795 if (system_supports_sme()) 1796 sme_smstop(); 1797 1798 set_thread_flag(TIF_FOREIGN_FPSTATE); 1799 } 1800 1801 /* 1802 * Save the FPSIMD state to memory and invalidate cpu view. 1803 * This function must be called with preemption disabled. 1804 */ 1805 void fpsimd_save_and_flush_cpu_state(void) 1806 { 1807 if (!system_supports_fpsimd()) 1808 return; 1809 WARN_ON(preemptible()); 1810 __get_cpu_fpsimd_context(); 1811 fpsimd_save(); 1812 fpsimd_flush_cpu_state(); 1813 __put_cpu_fpsimd_context(); 1814 } 1815 1816 #ifdef CONFIG_KERNEL_MODE_NEON 1817 1818 /* 1819 * Kernel-side NEON support functions 1820 */ 1821 1822 /* 1823 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling 1824 * context 1825 * 1826 * Must not be called unless may_use_simd() returns true. 1827 * Task context in the FPSIMD registers is saved back to memory as necessary. 1828 * 1829 * A matching call to kernel_neon_end() must be made before returning from the 1830 * calling context. 1831 * 1832 * The caller may freely use the FPSIMD registers until kernel_neon_end() is 1833 * called. 1834 */ 1835 void kernel_neon_begin(void) 1836 { 1837 if (WARN_ON(!system_supports_fpsimd())) 1838 return; 1839 1840 BUG_ON(!may_use_simd()); 1841 1842 get_cpu_fpsimd_context(); 1843 1844 /* Save unsaved fpsimd state, if any: */ 1845 fpsimd_save(); 1846 1847 /* Invalidate any task state remaining in the fpsimd regs: */ 1848 fpsimd_flush_cpu_state(); 1849 } 1850 EXPORT_SYMBOL(kernel_neon_begin); 1851 1852 /* 1853 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task 1854 * 1855 * Must be called from a context in which kernel_neon_begin() was previously 1856 * called, with no call to kernel_neon_end() in the meantime. 1857 * 1858 * The caller must not use the FPSIMD registers after this function is called, 1859 * unless kernel_neon_begin() is called again in the meantime. 1860 */ 1861 void kernel_neon_end(void) 1862 { 1863 if (!system_supports_fpsimd()) 1864 return; 1865 1866 put_cpu_fpsimd_context(); 1867 } 1868 EXPORT_SYMBOL(kernel_neon_end); 1869 1870 #ifdef CONFIG_EFI 1871 1872 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state); 1873 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used); 1874 static DEFINE_PER_CPU(bool, efi_sve_state_used); 1875 static DEFINE_PER_CPU(bool, efi_sm_state); 1876 1877 /* 1878 * EFI runtime services support functions 1879 * 1880 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call. 1881 * This means that for EFI (and only for EFI), we have to assume that FPSIMD 1882 * is always used rather than being an optional accelerator. 1883 * 1884 * These functions provide the necessary support for ensuring FPSIMD 1885 * save/restore in the contexts from which EFI is used. 1886 * 1887 * Do not use them for any other purpose -- if tempted to do so, you are 1888 * either doing something wrong or you need to propose some refactoring. 1889 */ 1890 1891 /* 1892 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call 1893 */ 1894 void __efi_fpsimd_begin(void) 1895 { 1896 if (!system_supports_fpsimd()) 1897 return; 1898 1899 WARN_ON(preemptible()); 1900 1901 if (may_use_simd()) { 1902 kernel_neon_begin(); 1903 } else { 1904 /* 1905 * If !efi_sve_state, SVE can't be in use yet and doesn't need 1906 * preserving: 1907 */ 1908 if (system_supports_sve() && likely(efi_sve_state)) { 1909 char *sve_state = this_cpu_ptr(efi_sve_state); 1910 bool ffr = true; 1911 u64 svcr; 1912 1913 __this_cpu_write(efi_sve_state_used, true); 1914 1915 if (system_supports_sme()) { 1916 svcr = read_sysreg_s(SYS_SVCR); 1917 1918 __this_cpu_write(efi_sm_state, 1919 svcr & SVCR_SM_MASK); 1920 1921 /* 1922 * Unless we have FA64 FFR does not 1923 * exist in streaming mode. 1924 */ 1925 if (!system_supports_fa64()) 1926 ffr = !(svcr & SVCR_SM_MASK); 1927 } 1928 1929 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()), 1930 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1931 ffr); 1932 1933 if (system_supports_sme()) 1934 sysreg_clear_set_s(SYS_SVCR, 1935 SVCR_SM_MASK, 0); 1936 1937 } else { 1938 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); 1939 } 1940 1941 __this_cpu_write(efi_fpsimd_state_used, true); 1942 } 1943 } 1944 1945 /* 1946 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call 1947 */ 1948 void __efi_fpsimd_end(void) 1949 { 1950 if (!system_supports_fpsimd()) 1951 return; 1952 1953 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) { 1954 kernel_neon_end(); 1955 } else { 1956 if (system_supports_sve() && 1957 likely(__this_cpu_read(efi_sve_state_used))) { 1958 char const *sve_state = this_cpu_ptr(efi_sve_state); 1959 bool ffr = true; 1960 1961 /* 1962 * Restore streaming mode; EFI calls are 1963 * normal function calls so should not return in 1964 * streaming mode. 1965 */ 1966 if (system_supports_sme()) { 1967 if (__this_cpu_read(efi_sm_state)) { 1968 sysreg_clear_set_s(SYS_SVCR, 1969 0, 1970 SVCR_SM_MASK); 1971 1972 /* 1973 * Unless we have FA64 FFR does not 1974 * exist in streaming mode. 1975 */ 1976 if (!system_supports_fa64()) 1977 ffr = false; 1978 } 1979 } 1980 1981 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()), 1982 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1983 ffr); 1984 1985 __this_cpu_write(efi_sve_state_used, false); 1986 } else { 1987 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); 1988 } 1989 } 1990 } 1991 1992 #endif /* CONFIG_EFI */ 1993 1994 #endif /* CONFIG_KERNEL_MODE_NEON */ 1995 1996 #ifdef CONFIG_CPU_PM 1997 static int fpsimd_cpu_pm_notifier(struct notifier_block *self, 1998 unsigned long cmd, void *v) 1999 { 2000 switch (cmd) { 2001 case CPU_PM_ENTER: 2002 fpsimd_save_and_flush_cpu_state(); 2003 break; 2004 case CPU_PM_EXIT: 2005 break; 2006 case CPU_PM_ENTER_FAILED: 2007 default: 2008 return NOTIFY_DONE; 2009 } 2010 return NOTIFY_OK; 2011 } 2012 2013 static struct notifier_block fpsimd_cpu_pm_notifier_block = { 2014 .notifier_call = fpsimd_cpu_pm_notifier, 2015 }; 2016 2017 static void __init fpsimd_pm_init(void) 2018 { 2019 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); 2020 } 2021 2022 #else 2023 static inline void fpsimd_pm_init(void) { } 2024 #endif /* CONFIG_CPU_PM */ 2025 2026 #ifdef CONFIG_HOTPLUG_CPU 2027 static int fpsimd_cpu_dead(unsigned int cpu) 2028 { 2029 per_cpu(fpsimd_last_state.st, cpu) = NULL; 2030 return 0; 2031 } 2032 2033 static inline void fpsimd_hotplug_init(void) 2034 { 2035 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead", 2036 NULL, fpsimd_cpu_dead); 2037 } 2038 2039 #else 2040 static inline void fpsimd_hotplug_init(void) { } 2041 #endif 2042 2043 /* 2044 * FP/SIMD support code initialisation. 2045 */ 2046 static int __init fpsimd_init(void) 2047 { 2048 if (cpu_have_named_feature(FP)) { 2049 fpsimd_pm_init(); 2050 fpsimd_hotplug_init(); 2051 } else { 2052 pr_notice("Floating-point is not implemented\n"); 2053 } 2054 2055 if (!cpu_have_named_feature(ASIMD)) 2056 pr_notice("Advanced SIMD is not implemented\n"); 2057 2058 2059 if (cpu_have_named_feature(SME) && !cpu_have_named_feature(SVE)) 2060 pr_notice("SME is implemented but not SVE\n"); 2061 2062 sve_sysctl_init(); 2063 sme_sysctl_init(); 2064 2065 return 0; 2066 } 2067 core_initcall(fpsimd_init); 2068