1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FP/SIMD context switching and fault handling 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/bottom_half.h> 12 #include <linux/bug.h> 13 #include <linux/cache.h> 14 #include <linux/compat.h> 15 #include <linux/cpu.h> 16 #include <linux/cpu_pm.h> 17 #include <linux/kernel.h> 18 #include <linux/linkage.h> 19 #include <linux/irqflags.h> 20 #include <linux/init.h> 21 #include <linux/percpu.h> 22 #include <linux/prctl.h> 23 #include <linux/preempt.h> 24 #include <linux/ptrace.h> 25 #include <linux/sched/signal.h> 26 #include <linux/sched/task_stack.h> 27 #include <linux/signal.h> 28 #include <linux/slab.h> 29 #include <linux/stddef.h> 30 #include <linux/sysctl.h> 31 #include <linux/swab.h> 32 33 #include <asm/esr.h> 34 #include <asm/fpsimd.h> 35 #include <asm/cpufeature.h> 36 #include <asm/cputype.h> 37 #include <asm/processor.h> 38 #include <asm/simd.h> 39 #include <asm/sigcontext.h> 40 #include <asm/sysreg.h> 41 #include <asm/traps.h> 42 #include <asm/virt.h> 43 44 #define FPEXC_IOF (1 << 0) 45 #define FPEXC_DZF (1 << 1) 46 #define FPEXC_OFF (1 << 2) 47 #define FPEXC_UFF (1 << 3) 48 #define FPEXC_IXF (1 << 4) 49 #define FPEXC_IDF (1 << 7) 50 51 /* 52 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.) 53 * 54 * In order to reduce the number of times the FPSIMD state is needlessly saved 55 * and restored, we need to keep track of two things: 56 * (a) for each task, we need to remember which CPU was the last one to have 57 * the task's FPSIMD state loaded into its FPSIMD registers; 58 * (b) for each CPU, we need to remember which task's userland FPSIMD state has 59 * been loaded into its FPSIMD registers most recently, or whether it has 60 * been used to perform kernel mode NEON in the meantime. 61 * 62 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to 63 * the id of the current CPU every time the state is loaded onto a CPU. For (b), 64 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the 65 * address of the userland FPSIMD state of the task that was loaded onto the CPU 66 * the most recently, or NULL if kernel mode NEON has been performed after that. 67 * 68 * With this in place, we no longer have to restore the next FPSIMD state right 69 * when switching between tasks. Instead, we can defer this check to userland 70 * resume, at which time we verify whether the CPU's fpsimd_last_state and the 71 * task's fpsimd_cpu are still mutually in sync. If this is the case, we 72 * can omit the FPSIMD restore. 73 * 74 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to 75 * indicate whether or not the userland FPSIMD state of the current task is 76 * present in the registers. The flag is set unless the FPSIMD registers of this 77 * CPU currently contain the most recent userland FPSIMD state of the current 78 * task. 79 * 80 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may 81 * save the task's FPSIMD context back to task_struct from softirq context. 82 * To prevent this from racing with the manipulation of the task's FPSIMD state 83 * from task context and thereby corrupting the state, it is necessary to 84 * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE 85 * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to 86 * run but prevent them to use FPSIMD. 87 * 88 * For a certain task, the sequence may look something like this: 89 * - the task gets scheduled in; if both the task's fpsimd_cpu field 90 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu 91 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is 92 * cleared, otherwise it is set; 93 * 94 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's 95 * userland FPSIMD state is copied from memory to the registers, the task's 96 * fpsimd_cpu field is set to the id of the current CPU, the current 97 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the 98 * TIF_FOREIGN_FPSTATE flag is cleared; 99 * 100 * - the task executes an ordinary syscall; upon return to userland, the 101 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is 102 * restored; 103 * 104 * - the task executes a syscall which executes some NEON instructions; this is 105 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD 106 * register contents to memory, clears the fpsimd_last_state per-cpu variable 107 * and sets the TIF_FOREIGN_FPSTATE flag; 108 * 109 * - the task gets preempted after kernel_neon_end() is called; as we have not 110 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so 111 * whatever is in the FPSIMD registers is not saved to memory, but discarded. 112 */ 113 struct fpsimd_last_state_struct { 114 struct user_fpsimd_state *st; 115 void *sve_state; 116 unsigned int sve_vl; 117 }; 118 119 static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state); 120 121 /* Default VL for tasks that don't set it explicitly: */ 122 static int sve_default_vl = -1; 123 124 #ifdef CONFIG_ARM64_SVE 125 126 /* Maximum supported vector length across all CPUs (initially poisoned) */ 127 int __ro_after_init sve_max_vl = SVE_VL_MIN; 128 int __ro_after_init sve_max_virtualisable_vl = SVE_VL_MIN; 129 130 /* 131 * Set of available vector lengths, 132 * where length vq encoded as bit __vq_to_bit(vq): 133 */ 134 __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); 135 /* Set of vector lengths present on at least one cpu: */ 136 static __ro_after_init DECLARE_BITMAP(sve_vq_partial_map, SVE_VQ_MAX); 137 138 static void __percpu *efi_sve_state; 139 140 #else /* ! CONFIG_ARM64_SVE */ 141 142 /* Dummy declaration for code that will be optimised out: */ 143 extern __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); 144 extern __ro_after_init DECLARE_BITMAP(sve_vq_partial_map, SVE_VQ_MAX); 145 extern void __percpu *efi_sve_state; 146 147 #endif /* ! CONFIG_ARM64_SVE */ 148 149 DEFINE_PER_CPU(bool, fpsimd_context_busy); 150 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy); 151 152 static void __get_cpu_fpsimd_context(void) 153 { 154 bool busy = __this_cpu_xchg(fpsimd_context_busy, true); 155 156 WARN_ON(busy); 157 } 158 159 /* 160 * Claim ownership of the CPU FPSIMD context for use by the calling context. 161 * 162 * The caller may freely manipulate the FPSIMD context metadata until 163 * put_cpu_fpsimd_context() is called. 164 * 165 * The double-underscore version must only be called if you know the task 166 * can't be preempted. 167 */ 168 static void get_cpu_fpsimd_context(void) 169 { 170 preempt_disable(); 171 __get_cpu_fpsimd_context(); 172 } 173 174 static void __put_cpu_fpsimd_context(void) 175 { 176 bool busy = __this_cpu_xchg(fpsimd_context_busy, false); 177 178 WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */ 179 } 180 181 /* 182 * Release the CPU FPSIMD context. 183 * 184 * Must be called from a context in which get_cpu_fpsimd_context() was 185 * previously called, with no call to put_cpu_fpsimd_context() in the 186 * meantime. 187 */ 188 static void put_cpu_fpsimd_context(void) 189 { 190 __put_cpu_fpsimd_context(); 191 preempt_enable(); 192 } 193 194 static bool have_cpu_fpsimd_context(void) 195 { 196 return !preemptible() && __this_cpu_read(fpsimd_context_busy); 197 } 198 199 /* 200 * Call __sve_free() directly only if you know task can't be scheduled 201 * or preempted. 202 */ 203 static void __sve_free(struct task_struct *task) 204 { 205 kfree(task->thread.sve_state); 206 task->thread.sve_state = NULL; 207 } 208 209 static void sve_free(struct task_struct *task) 210 { 211 WARN_ON(test_tsk_thread_flag(task, TIF_SVE)); 212 213 __sve_free(task); 214 } 215 216 /* 217 * TIF_SVE controls whether a task can use SVE without trapping while 218 * in userspace, and also the way a task's FPSIMD/SVE state is stored 219 * in thread_struct. 220 * 221 * The kernel uses this flag to track whether a user task is actively 222 * using SVE, and therefore whether full SVE register state needs to 223 * be tracked. If not, the cheaper FPSIMD context handling code can 224 * be used instead of the more costly SVE equivalents. 225 * 226 * * TIF_SVE set: 227 * 228 * The task can execute SVE instructions while in userspace without 229 * trapping to the kernel. 230 * 231 * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the 232 * corresponding Zn), P0-P15 and FFR are encoded in in 233 * task->thread.sve_state, formatted appropriately for vector 234 * length task->thread.sve_vl. 235 * 236 * task->thread.sve_state must point to a valid buffer at least 237 * sve_state_size(task) bytes in size. 238 * 239 * During any syscall, the kernel may optionally clear TIF_SVE and 240 * discard the vector state except for the FPSIMD subset. 241 * 242 * * TIF_SVE clear: 243 * 244 * An attempt by the user task to execute an SVE instruction causes 245 * do_sve_acc() to be called, which does some preparation and then 246 * sets TIF_SVE. 247 * 248 * When stored, FPSIMD registers V0-V31 are encoded in 249 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are 250 * logically zero but not stored anywhere; P0-P15 and FFR are not 251 * stored and have unspecified values from userspace's point of 252 * view. For hygiene purposes, the kernel zeroes them on next use, 253 * but userspace is discouraged from relying on this. 254 * 255 * task->thread.sve_state does not need to be non-NULL, valid or any 256 * particular size: it must not be dereferenced. 257 * 258 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state 259 * irrespective of whether TIF_SVE is clear or set, since these are 260 * not vector length dependent. 261 */ 262 263 /* 264 * Update current's FPSIMD/SVE registers from thread_struct. 265 * 266 * This function should be called only when the FPSIMD/SVE state in 267 * thread_struct is known to be up to date, when preparing to enter 268 * userspace. 269 */ 270 static void task_fpsimd_load(void) 271 { 272 WARN_ON(!have_cpu_fpsimd_context()); 273 274 if (system_supports_sve() && test_thread_flag(TIF_SVE)) 275 sve_load_state(sve_pffr(¤t->thread), 276 ¤t->thread.uw.fpsimd_state.fpsr, 277 sve_vq_from_vl(current->thread.sve_vl) - 1); 278 else 279 fpsimd_load_state(¤t->thread.uw.fpsimd_state); 280 } 281 282 /* 283 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to 284 * date with respect to the CPU registers. 285 */ 286 static void fpsimd_save(void) 287 { 288 struct fpsimd_last_state_struct const *last = 289 this_cpu_ptr(&fpsimd_last_state); 290 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */ 291 292 WARN_ON(!have_cpu_fpsimd_context()); 293 294 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 295 if (system_supports_sve() && test_thread_flag(TIF_SVE)) { 296 if (WARN_ON(sve_get_vl() != last->sve_vl)) { 297 /* 298 * Can't save the user regs, so current would 299 * re-enter user with corrupt state. 300 * There's no way to recover, so kill it: 301 */ 302 force_signal_inject(SIGKILL, SI_KERNEL, 0); 303 return; 304 } 305 306 sve_save_state((char *)last->sve_state + 307 sve_ffr_offset(last->sve_vl), 308 &last->st->fpsr); 309 } else 310 fpsimd_save_state(last->st); 311 } 312 } 313 314 /* 315 * All vector length selection from userspace comes through here. 316 * We're on a slow path, so some sanity-checks are included. 317 * If things go wrong there's a bug somewhere, but try to fall back to a 318 * safe choice. 319 */ 320 static unsigned int find_supported_vector_length(unsigned int vl) 321 { 322 int bit; 323 int max_vl = sve_max_vl; 324 325 if (WARN_ON(!sve_vl_valid(vl))) 326 vl = SVE_VL_MIN; 327 328 if (WARN_ON(!sve_vl_valid(max_vl))) 329 max_vl = SVE_VL_MIN; 330 331 if (vl > max_vl) 332 vl = max_vl; 333 334 bit = find_next_bit(sve_vq_map, SVE_VQ_MAX, 335 __vq_to_bit(sve_vq_from_vl(vl))); 336 return sve_vl_from_vq(__bit_to_vq(bit)); 337 } 338 339 #ifdef CONFIG_SYSCTL 340 341 static int sve_proc_do_default_vl(struct ctl_table *table, int write, 342 void __user *buffer, size_t *lenp, 343 loff_t *ppos) 344 { 345 int ret; 346 int vl = sve_default_vl; 347 struct ctl_table tmp_table = { 348 .data = &vl, 349 .maxlen = sizeof(vl), 350 }; 351 352 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos); 353 if (ret || !write) 354 return ret; 355 356 /* Writing -1 has the special meaning "set to max": */ 357 if (vl == -1) 358 vl = sve_max_vl; 359 360 if (!sve_vl_valid(vl)) 361 return -EINVAL; 362 363 sve_default_vl = find_supported_vector_length(vl); 364 return 0; 365 } 366 367 static struct ctl_table sve_default_vl_table[] = { 368 { 369 .procname = "sve_default_vector_length", 370 .mode = 0644, 371 .proc_handler = sve_proc_do_default_vl, 372 }, 373 { } 374 }; 375 376 static int __init sve_sysctl_init(void) 377 { 378 if (system_supports_sve()) 379 if (!register_sysctl("abi", sve_default_vl_table)) 380 return -EINVAL; 381 382 return 0; 383 } 384 385 #else /* ! CONFIG_SYSCTL */ 386 static int __init sve_sysctl_init(void) { return 0; } 387 #endif /* ! CONFIG_SYSCTL */ 388 389 #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ 390 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) 391 392 #ifdef CONFIG_CPU_BIG_ENDIAN 393 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 394 { 395 u64 a = swab64(x); 396 u64 b = swab64(x >> 64); 397 398 return ((__uint128_t)a << 64) | b; 399 } 400 #else 401 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 402 { 403 return x; 404 } 405 #endif 406 407 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) 408 409 /* 410 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to 411 * task->thread.sve_state. 412 * 413 * Task can be a non-runnable task, or current. In the latter case, 414 * the caller must have ownership of the cpu FPSIMD context before calling 415 * this function. 416 * task->thread.sve_state must point to at least sve_state_size(task) 417 * bytes of allocated kernel memory. 418 * task->thread.uw.fpsimd_state must be up to date before calling this 419 * function. 420 */ 421 static void fpsimd_to_sve(struct task_struct *task) 422 { 423 unsigned int vq; 424 void *sst = task->thread.sve_state; 425 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 426 unsigned int i; 427 __uint128_t *p; 428 429 if (!system_supports_sve()) 430 return; 431 432 vq = sve_vq_from_vl(task->thread.sve_vl); 433 for (i = 0; i < 32; ++i) { 434 p = (__uint128_t *)ZREG(sst, vq, i); 435 *p = arm64_cpu_to_le128(fst->vregs[i]); 436 } 437 } 438 439 /* 440 * Transfer the SVE state in task->thread.sve_state to 441 * task->thread.uw.fpsimd_state. 442 * 443 * Task can be a non-runnable task, or current. In the latter case, 444 * the caller must have ownership of the cpu FPSIMD context before calling 445 * this function. 446 * task->thread.sve_state must point to at least sve_state_size(task) 447 * bytes of allocated kernel memory. 448 * task->thread.sve_state must be up to date before calling this function. 449 */ 450 static void sve_to_fpsimd(struct task_struct *task) 451 { 452 unsigned int vq; 453 void const *sst = task->thread.sve_state; 454 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state; 455 unsigned int i; 456 __uint128_t const *p; 457 458 if (!system_supports_sve()) 459 return; 460 461 vq = sve_vq_from_vl(task->thread.sve_vl); 462 for (i = 0; i < 32; ++i) { 463 p = (__uint128_t const *)ZREG(sst, vq, i); 464 fst->vregs[i] = arm64_le128_to_cpu(*p); 465 } 466 } 467 468 #ifdef CONFIG_ARM64_SVE 469 470 /* 471 * Return how many bytes of memory are required to store the full SVE 472 * state for task, given task's currently configured vector length. 473 */ 474 size_t sve_state_size(struct task_struct const *task) 475 { 476 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(task->thread.sve_vl)); 477 } 478 479 /* 480 * Ensure that task->thread.sve_state is allocated and sufficiently large. 481 * 482 * This function should be used only in preparation for replacing 483 * task->thread.sve_state with new data. The memory is always zeroed 484 * here to prevent stale data from showing through: this is done in 485 * the interest of testability and predictability: except in the 486 * do_sve_acc() case, there is no ABI requirement to hide stale data 487 * written previously be task. 488 */ 489 void sve_alloc(struct task_struct *task) 490 { 491 if (task->thread.sve_state) { 492 memset(task->thread.sve_state, 0, sve_state_size(current)); 493 return; 494 } 495 496 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */ 497 task->thread.sve_state = 498 kzalloc(sve_state_size(task), GFP_KERNEL); 499 500 /* 501 * If future SVE revisions can have larger vectors though, 502 * this may cease to be true: 503 */ 504 BUG_ON(!task->thread.sve_state); 505 } 506 507 508 /* 509 * Ensure that task->thread.sve_state is up to date with respect to 510 * the user task, irrespective of when SVE is in use or not. 511 * 512 * This should only be called by ptrace. task must be non-runnable. 513 * task->thread.sve_state must point to at least sve_state_size(task) 514 * bytes of allocated kernel memory. 515 */ 516 void fpsimd_sync_to_sve(struct task_struct *task) 517 { 518 if (!test_tsk_thread_flag(task, TIF_SVE)) 519 fpsimd_to_sve(task); 520 } 521 522 /* 523 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to 524 * the user task, irrespective of whether SVE is in use or not. 525 * 526 * This should only be called by ptrace. task must be non-runnable. 527 * task->thread.sve_state must point to at least sve_state_size(task) 528 * bytes of allocated kernel memory. 529 */ 530 void sve_sync_to_fpsimd(struct task_struct *task) 531 { 532 if (test_tsk_thread_flag(task, TIF_SVE)) 533 sve_to_fpsimd(task); 534 } 535 536 /* 537 * Ensure that task->thread.sve_state is up to date with respect to 538 * the task->thread.uw.fpsimd_state. 539 * 540 * This should only be called by ptrace to merge new FPSIMD register 541 * values into a task for which SVE is currently active. 542 * task must be non-runnable. 543 * task->thread.sve_state must point to at least sve_state_size(task) 544 * bytes of allocated kernel memory. 545 * task->thread.uw.fpsimd_state must already have been initialised with 546 * the new FPSIMD register values to be merged in. 547 */ 548 void sve_sync_from_fpsimd_zeropad(struct task_struct *task) 549 { 550 unsigned int vq; 551 void *sst = task->thread.sve_state; 552 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 553 unsigned int i; 554 __uint128_t *p; 555 556 if (!test_tsk_thread_flag(task, TIF_SVE)) 557 return; 558 559 vq = sve_vq_from_vl(task->thread.sve_vl); 560 561 memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); 562 563 for (i = 0; i < 32; ++i) { 564 p = (__uint128_t *)ZREG(sst, vq, i); 565 *p = arm64_cpu_to_le128(fst->vregs[i]); 566 } 567 } 568 569 int sve_set_vector_length(struct task_struct *task, 570 unsigned long vl, unsigned long flags) 571 { 572 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | 573 PR_SVE_SET_VL_ONEXEC)) 574 return -EINVAL; 575 576 if (!sve_vl_valid(vl)) 577 return -EINVAL; 578 579 /* 580 * Clamp to the maximum vector length that VL-agnostic SVE code can 581 * work with. A flag may be assigned in the future to allow setting 582 * of larger vector lengths without confusing older software. 583 */ 584 if (vl > SVE_VL_ARCH_MAX) 585 vl = SVE_VL_ARCH_MAX; 586 587 vl = find_supported_vector_length(vl); 588 589 if (flags & (PR_SVE_VL_INHERIT | 590 PR_SVE_SET_VL_ONEXEC)) 591 task->thread.sve_vl_onexec = vl; 592 else 593 /* Reset VL to system default on next exec: */ 594 task->thread.sve_vl_onexec = 0; 595 596 /* Only actually set the VL if not deferred: */ 597 if (flags & PR_SVE_SET_VL_ONEXEC) 598 goto out; 599 600 if (vl == task->thread.sve_vl) 601 goto out; 602 603 /* 604 * To ensure the FPSIMD bits of the SVE vector registers are preserved, 605 * write any live register state back to task_struct, and convert to a 606 * non-SVE thread. 607 */ 608 if (task == current) { 609 get_cpu_fpsimd_context(); 610 611 fpsimd_save(); 612 } 613 614 fpsimd_flush_task_state(task); 615 if (test_and_clear_tsk_thread_flag(task, TIF_SVE)) 616 sve_to_fpsimd(task); 617 618 if (task == current) 619 put_cpu_fpsimd_context(); 620 621 /* 622 * Force reallocation of task SVE state to the correct size 623 * on next use: 624 */ 625 sve_free(task); 626 627 task->thread.sve_vl = vl; 628 629 out: 630 update_tsk_thread_flag(task, TIF_SVE_VL_INHERIT, 631 flags & PR_SVE_VL_INHERIT); 632 633 return 0; 634 } 635 636 /* 637 * Encode the current vector length and flags for return. 638 * This is only required for prctl(): ptrace has separate fields 639 * 640 * flags are as for sve_set_vector_length(). 641 */ 642 static int sve_prctl_status(unsigned long flags) 643 { 644 int ret; 645 646 if (flags & PR_SVE_SET_VL_ONEXEC) 647 ret = current->thread.sve_vl_onexec; 648 else 649 ret = current->thread.sve_vl; 650 651 if (test_thread_flag(TIF_SVE_VL_INHERIT)) 652 ret |= PR_SVE_VL_INHERIT; 653 654 return ret; 655 } 656 657 /* PR_SVE_SET_VL */ 658 int sve_set_current_vl(unsigned long arg) 659 { 660 unsigned long vl, flags; 661 int ret; 662 663 vl = arg & PR_SVE_VL_LEN_MASK; 664 flags = arg & ~vl; 665 666 if (!system_supports_sve()) 667 return -EINVAL; 668 669 ret = sve_set_vector_length(current, vl, flags); 670 if (ret) 671 return ret; 672 673 return sve_prctl_status(flags); 674 } 675 676 /* PR_SVE_GET_VL */ 677 int sve_get_current_vl(void) 678 { 679 if (!system_supports_sve()) 680 return -EINVAL; 681 682 return sve_prctl_status(0); 683 } 684 685 static void sve_probe_vqs(DECLARE_BITMAP(map, SVE_VQ_MAX)) 686 { 687 unsigned int vq, vl; 688 unsigned long zcr; 689 690 bitmap_zero(map, SVE_VQ_MAX); 691 692 zcr = ZCR_ELx_LEN_MASK; 693 zcr = read_sysreg_s(SYS_ZCR_EL1) & ~zcr; 694 695 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) { 696 write_sysreg_s(zcr | (vq - 1), SYS_ZCR_EL1); /* self-syncing */ 697 vl = sve_get_vl(); 698 vq = sve_vq_from_vl(vl); /* skip intervening lengths */ 699 set_bit(__vq_to_bit(vq), map); 700 } 701 } 702 703 /* 704 * Initialise the set of known supported VQs for the boot CPU. 705 * This is called during kernel boot, before secondary CPUs are brought up. 706 */ 707 void __init sve_init_vq_map(void) 708 { 709 sve_probe_vqs(sve_vq_map); 710 bitmap_copy(sve_vq_partial_map, sve_vq_map, SVE_VQ_MAX); 711 } 712 713 /* 714 * If we haven't committed to the set of supported VQs yet, filter out 715 * those not supported by the current CPU. 716 * This function is called during the bring-up of early secondary CPUs only. 717 */ 718 void sve_update_vq_map(void) 719 { 720 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 721 722 sve_probe_vqs(tmp_map); 723 bitmap_and(sve_vq_map, sve_vq_map, tmp_map, SVE_VQ_MAX); 724 bitmap_or(sve_vq_partial_map, sve_vq_partial_map, tmp_map, SVE_VQ_MAX); 725 } 726 727 /* 728 * Check whether the current CPU supports all VQs in the committed set. 729 * This function is called during the bring-up of late secondary CPUs only. 730 */ 731 int sve_verify_vq_map(void) 732 { 733 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 734 unsigned long b; 735 736 sve_probe_vqs(tmp_map); 737 738 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 739 if (bitmap_intersects(tmp_map, sve_vq_map, SVE_VQ_MAX)) { 740 pr_warn("SVE: cpu%d: Required vector length(s) missing\n", 741 smp_processor_id()); 742 return -EINVAL; 743 } 744 745 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) 746 return 0; 747 748 /* 749 * For KVM, it is necessary to ensure that this CPU doesn't 750 * support any vector length that guests may have probed as 751 * unsupported. 752 */ 753 754 /* Recover the set of supported VQs: */ 755 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 756 /* Find VQs supported that are not globally supported: */ 757 bitmap_andnot(tmp_map, tmp_map, sve_vq_map, SVE_VQ_MAX); 758 759 /* Find the lowest such VQ, if any: */ 760 b = find_last_bit(tmp_map, SVE_VQ_MAX); 761 if (b >= SVE_VQ_MAX) 762 return 0; /* no mismatches */ 763 764 /* 765 * Mismatches above sve_max_virtualisable_vl are fine, since 766 * no guest is allowed to configure ZCR_EL2.LEN to exceed this: 767 */ 768 if (sve_vl_from_vq(__bit_to_vq(b)) <= sve_max_virtualisable_vl) { 769 pr_warn("SVE: cpu%d: Unsupported vector length(s) present\n", 770 smp_processor_id()); 771 return -EINVAL; 772 } 773 774 return 0; 775 } 776 777 static void __init sve_efi_setup(void) 778 { 779 if (!IS_ENABLED(CONFIG_EFI)) 780 return; 781 782 /* 783 * alloc_percpu() warns and prints a backtrace if this goes wrong. 784 * This is evidence of a crippled system and we are returning void, 785 * so no attempt is made to handle this situation here. 786 */ 787 if (!sve_vl_valid(sve_max_vl)) 788 goto fail; 789 790 efi_sve_state = __alloc_percpu( 791 SVE_SIG_REGS_SIZE(sve_vq_from_vl(sve_max_vl)), SVE_VQ_BYTES); 792 if (!efi_sve_state) 793 goto fail; 794 795 return; 796 797 fail: 798 panic("Cannot allocate percpu memory for EFI SVE save/restore"); 799 } 800 801 /* 802 * Enable SVE for EL1. 803 * Intended for use by the cpufeatures code during CPU boot. 804 */ 805 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 806 { 807 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); 808 isb(); 809 } 810 811 /* 812 * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE 813 * vector length. 814 * 815 * Use only if SVE is present. 816 * This function clobbers the SVE vector length. 817 */ 818 u64 read_zcr_features(void) 819 { 820 u64 zcr; 821 unsigned int vq_max; 822 823 /* 824 * Set the maximum possible VL, and write zeroes to all other 825 * bits to see if they stick. 826 */ 827 sve_kernel_enable(NULL); 828 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); 829 830 zcr = read_sysreg_s(SYS_ZCR_EL1); 831 zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ 832 vq_max = sve_vq_from_vl(sve_get_vl()); 833 zcr |= vq_max - 1; /* set LEN field to maximum effective value */ 834 835 return zcr; 836 } 837 838 void __init sve_setup(void) 839 { 840 u64 zcr; 841 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 842 unsigned long b; 843 844 if (!system_supports_sve()) 845 return; 846 847 /* 848 * The SVE architecture mandates support for 128-bit vectors, 849 * so sve_vq_map must have at least SVE_VQ_MIN set. 850 * If something went wrong, at least try to patch it up: 851 */ 852 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), sve_vq_map))) 853 set_bit(__vq_to_bit(SVE_VQ_MIN), sve_vq_map); 854 855 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 856 sve_max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1); 857 858 /* 859 * Sanity-check that the max VL we determined through CPU features 860 * corresponds properly to sve_vq_map. If not, do our best: 861 */ 862 if (WARN_ON(sve_max_vl != find_supported_vector_length(sve_max_vl))) 863 sve_max_vl = find_supported_vector_length(sve_max_vl); 864 865 /* 866 * For the default VL, pick the maximum supported value <= 64. 867 * VL == 64 is guaranteed not to grow the signal frame. 868 */ 869 sve_default_vl = find_supported_vector_length(64); 870 871 bitmap_andnot(tmp_map, sve_vq_partial_map, sve_vq_map, 872 SVE_VQ_MAX); 873 874 b = find_last_bit(tmp_map, SVE_VQ_MAX); 875 if (b >= SVE_VQ_MAX) 876 /* No non-virtualisable VLs found */ 877 sve_max_virtualisable_vl = SVE_VQ_MAX; 878 else if (WARN_ON(b == SVE_VQ_MAX - 1)) 879 /* No virtualisable VLs? This is architecturally forbidden. */ 880 sve_max_virtualisable_vl = SVE_VQ_MIN; 881 else /* b + 1 < SVE_VQ_MAX */ 882 sve_max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1)); 883 884 if (sve_max_virtualisable_vl > sve_max_vl) 885 sve_max_virtualisable_vl = sve_max_vl; 886 887 pr_info("SVE: maximum available vector length %u bytes per vector\n", 888 sve_max_vl); 889 pr_info("SVE: default vector length %u bytes per vector\n", 890 sve_default_vl); 891 892 /* KVM decides whether to support mismatched systems. Just warn here: */ 893 if (sve_max_virtualisable_vl < sve_max_vl) 894 pr_warn("SVE: unvirtualisable vector lengths present\n"); 895 896 sve_efi_setup(); 897 } 898 899 /* 900 * Called from the put_task_struct() path, which cannot get here 901 * unless dead_task is really dead and not schedulable. 902 */ 903 void fpsimd_release_task(struct task_struct *dead_task) 904 { 905 __sve_free(dead_task); 906 } 907 908 #endif /* CONFIG_ARM64_SVE */ 909 910 /* 911 * Trapped SVE access 912 * 913 * Storage is allocated for the full SVE state, the current FPSIMD 914 * register contents are migrated across, and TIF_SVE is set so that 915 * the SVE access trap will be disabled the next time this task 916 * reaches ret_to_user. 917 * 918 * TIF_SVE should be clear on entry: otherwise, task_fpsimd_load() 919 * would have disabled the SVE access trap for userspace during 920 * ret_to_user, making an SVE access trap impossible in that case. 921 */ 922 asmlinkage void do_sve_acc(unsigned int esr, struct pt_regs *regs) 923 { 924 /* Even if we chose not to use SVE, the hardware could still trap: */ 925 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) { 926 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); 927 return; 928 } 929 930 sve_alloc(current); 931 932 get_cpu_fpsimd_context(); 933 934 fpsimd_save(); 935 936 /* Force ret_to_user to reload the registers: */ 937 fpsimd_flush_task_state(current); 938 939 fpsimd_to_sve(current); 940 if (test_and_set_thread_flag(TIF_SVE)) 941 WARN_ON(1); /* SVE access shouldn't have trapped */ 942 943 put_cpu_fpsimd_context(); 944 } 945 946 /* 947 * Trapped FP/ASIMD access. 948 */ 949 asmlinkage void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs) 950 { 951 /* TODO: implement lazy context saving/restoring */ 952 WARN_ON(1); 953 } 954 955 /* 956 * Raise a SIGFPE for the current process. 957 */ 958 asmlinkage void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs) 959 { 960 unsigned int si_code = FPE_FLTUNK; 961 962 if (esr & ESR_ELx_FP_EXC_TFV) { 963 if (esr & FPEXC_IOF) 964 si_code = FPE_FLTINV; 965 else if (esr & FPEXC_DZF) 966 si_code = FPE_FLTDIV; 967 else if (esr & FPEXC_OFF) 968 si_code = FPE_FLTOVF; 969 else if (esr & FPEXC_UFF) 970 si_code = FPE_FLTUND; 971 else if (esr & FPEXC_IXF) 972 si_code = FPE_FLTRES; 973 } 974 975 send_sig_fault(SIGFPE, si_code, 976 (void __user *)instruction_pointer(regs), 977 current); 978 } 979 980 void fpsimd_thread_switch(struct task_struct *next) 981 { 982 bool wrong_task, wrong_cpu; 983 984 if (!system_supports_fpsimd()) 985 return; 986 987 __get_cpu_fpsimd_context(); 988 989 /* Save unsaved fpsimd state, if any: */ 990 fpsimd_save(); 991 992 /* 993 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's 994 * state. For kernel threads, FPSIMD registers are never loaded 995 * and wrong_task and wrong_cpu will always be true. 996 */ 997 wrong_task = __this_cpu_read(fpsimd_last_state.st) != 998 &next->thread.uw.fpsimd_state; 999 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id(); 1000 1001 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE, 1002 wrong_task || wrong_cpu); 1003 1004 __put_cpu_fpsimd_context(); 1005 } 1006 1007 void fpsimd_flush_thread(void) 1008 { 1009 int vl, supported_vl; 1010 1011 if (!system_supports_fpsimd()) 1012 return; 1013 1014 get_cpu_fpsimd_context(); 1015 1016 fpsimd_flush_task_state(current); 1017 memset(¤t->thread.uw.fpsimd_state, 0, 1018 sizeof(current->thread.uw.fpsimd_state)); 1019 1020 if (system_supports_sve()) { 1021 clear_thread_flag(TIF_SVE); 1022 sve_free(current); 1023 1024 /* 1025 * Reset the task vector length as required. 1026 * This is where we ensure that all user tasks have a valid 1027 * vector length configured: no kernel task can become a user 1028 * task without an exec and hence a call to this function. 1029 * By the time the first call to this function is made, all 1030 * early hardware probing is complete, so sve_default_vl 1031 * should be valid. 1032 * If a bug causes this to go wrong, we make some noise and 1033 * try to fudge thread.sve_vl to a safe value here. 1034 */ 1035 vl = current->thread.sve_vl_onexec ? 1036 current->thread.sve_vl_onexec : sve_default_vl; 1037 1038 if (WARN_ON(!sve_vl_valid(vl))) 1039 vl = SVE_VL_MIN; 1040 1041 supported_vl = find_supported_vector_length(vl); 1042 if (WARN_ON(supported_vl != vl)) 1043 vl = supported_vl; 1044 1045 current->thread.sve_vl = vl; 1046 1047 /* 1048 * If the task is not set to inherit, ensure that the vector 1049 * length will be reset by a subsequent exec: 1050 */ 1051 if (!test_thread_flag(TIF_SVE_VL_INHERIT)) 1052 current->thread.sve_vl_onexec = 0; 1053 } 1054 1055 put_cpu_fpsimd_context(); 1056 } 1057 1058 /* 1059 * Save the userland FPSIMD state of 'current' to memory, but only if the state 1060 * currently held in the registers does in fact belong to 'current' 1061 */ 1062 void fpsimd_preserve_current_state(void) 1063 { 1064 if (!system_supports_fpsimd()) 1065 return; 1066 1067 get_cpu_fpsimd_context(); 1068 fpsimd_save(); 1069 put_cpu_fpsimd_context(); 1070 } 1071 1072 /* 1073 * Like fpsimd_preserve_current_state(), but ensure that 1074 * current->thread.uw.fpsimd_state is updated so that it can be copied to 1075 * the signal frame. 1076 */ 1077 void fpsimd_signal_preserve_current_state(void) 1078 { 1079 fpsimd_preserve_current_state(); 1080 if (system_supports_sve() && test_thread_flag(TIF_SVE)) 1081 sve_to_fpsimd(current); 1082 } 1083 1084 /* 1085 * Associate current's FPSIMD context with this cpu 1086 * The caller must have ownership of the cpu FPSIMD context before calling 1087 * this function. 1088 */ 1089 void fpsimd_bind_task_to_cpu(void) 1090 { 1091 struct fpsimd_last_state_struct *last = 1092 this_cpu_ptr(&fpsimd_last_state); 1093 1094 last->st = ¤t->thread.uw.fpsimd_state; 1095 last->sve_state = current->thread.sve_state; 1096 last->sve_vl = current->thread.sve_vl; 1097 current->thread.fpsimd_cpu = smp_processor_id(); 1098 1099 if (system_supports_sve()) { 1100 /* Toggle SVE trapping for userspace if needed */ 1101 if (test_thread_flag(TIF_SVE)) 1102 sve_user_enable(); 1103 else 1104 sve_user_disable(); 1105 1106 /* Serialised by exception return to user */ 1107 } 1108 } 1109 1110 void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, 1111 unsigned int sve_vl) 1112 { 1113 struct fpsimd_last_state_struct *last = 1114 this_cpu_ptr(&fpsimd_last_state); 1115 1116 WARN_ON(!in_softirq() && !irqs_disabled()); 1117 1118 last->st = st; 1119 last->sve_state = sve_state; 1120 last->sve_vl = sve_vl; 1121 } 1122 1123 /* 1124 * Load the userland FPSIMD state of 'current' from memory, but only if the 1125 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD 1126 * state of 'current' 1127 */ 1128 void fpsimd_restore_current_state(void) 1129 { 1130 if (!system_supports_fpsimd()) 1131 return; 1132 1133 get_cpu_fpsimd_context(); 1134 1135 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { 1136 task_fpsimd_load(); 1137 fpsimd_bind_task_to_cpu(); 1138 } 1139 1140 put_cpu_fpsimd_context(); 1141 } 1142 1143 /* 1144 * Load an updated userland FPSIMD state for 'current' from memory and set the 1145 * flag that indicates that the FPSIMD register contents are the most recent 1146 * FPSIMD state of 'current' 1147 */ 1148 void fpsimd_update_current_state(struct user_fpsimd_state const *state) 1149 { 1150 if (!system_supports_fpsimd()) 1151 return; 1152 1153 get_cpu_fpsimd_context(); 1154 1155 current->thread.uw.fpsimd_state = *state; 1156 if (system_supports_sve() && test_thread_flag(TIF_SVE)) 1157 fpsimd_to_sve(current); 1158 1159 task_fpsimd_load(); 1160 fpsimd_bind_task_to_cpu(); 1161 1162 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1163 1164 put_cpu_fpsimd_context(); 1165 } 1166 1167 /* 1168 * Invalidate live CPU copies of task t's FPSIMD state 1169 * 1170 * This function may be called with preemption enabled. The barrier() 1171 * ensures that the assignment to fpsimd_cpu is visible to any 1172 * preemption/softirq that could race with set_tsk_thread_flag(), so 1173 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared. 1174 * 1175 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any 1176 * subsequent code. 1177 */ 1178 void fpsimd_flush_task_state(struct task_struct *t) 1179 { 1180 t->thread.fpsimd_cpu = NR_CPUS; 1181 1182 barrier(); 1183 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE); 1184 1185 barrier(); 1186 } 1187 1188 /* 1189 * Invalidate any task's FPSIMD state that is present on this cpu. 1190 * The FPSIMD context should be acquired with get_cpu_fpsimd_context() 1191 * before calling this function. 1192 */ 1193 static void fpsimd_flush_cpu_state(void) 1194 { 1195 __this_cpu_write(fpsimd_last_state.st, NULL); 1196 set_thread_flag(TIF_FOREIGN_FPSTATE); 1197 } 1198 1199 /* 1200 * Save the FPSIMD state to memory and invalidate cpu view. 1201 * This function must be called with preemption disabled. 1202 */ 1203 void fpsimd_save_and_flush_cpu_state(void) 1204 { 1205 WARN_ON(preemptible()); 1206 __get_cpu_fpsimd_context(); 1207 fpsimd_save(); 1208 fpsimd_flush_cpu_state(); 1209 __put_cpu_fpsimd_context(); 1210 } 1211 1212 #ifdef CONFIG_KERNEL_MODE_NEON 1213 1214 /* 1215 * Kernel-side NEON support functions 1216 */ 1217 1218 /* 1219 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling 1220 * context 1221 * 1222 * Must not be called unless may_use_simd() returns true. 1223 * Task context in the FPSIMD registers is saved back to memory as necessary. 1224 * 1225 * A matching call to kernel_neon_end() must be made before returning from the 1226 * calling context. 1227 * 1228 * The caller may freely use the FPSIMD registers until kernel_neon_end() is 1229 * called. 1230 */ 1231 void kernel_neon_begin(void) 1232 { 1233 if (WARN_ON(!system_supports_fpsimd())) 1234 return; 1235 1236 BUG_ON(!may_use_simd()); 1237 1238 get_cpu_fpsimd_context(); 1239 1240 /* Save unsaved fpsimd state, if any: */ 1241 fpsimd_save(); 1242 1243 /* Invalidate any task state remaining in the fpsimd regs: */ 1244 fpsimd_flush_cpu_state(); 1245 } 1246 EXPORT_SYMBOL(kernel_neon_begin); 1247 1248 /* 1249 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task 1250 * 1251 * Must be called from a context in which kernel_neon_begin() was previously 1252 * called, with no call to kernel_neon_end() in the meantime. 1253 * 1254 * The caller must not use the FPSIMD registers after this function is called, 1255 * unless kernel_neon_begin() is called again in the meantime. 1256 */ 1257 void kernel_neon_end(void) 1258 { 1259 if (!system_supports_fpsimd()) 1260 return; 1261 1262 put_cpu_fpsimd_context(); 1263 } 1264 EXPORT_SYMBOL(kernel_neon_end); 1265 1266 #ifdef CONFIG_EFI 1267 1268 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state); 1269 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used); 1270 static DEFINE_PER_CPU(bool, efi_sve_state_used); 1271 1272 /* 1273 * EFI runtime services support functions 1274 * 1275 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call. 1276 * This means that for EFI (and only for EFI), we have to assume that FPSIMD 1277 * is always used rather than being an optional accelerator. 1278 * 1279 * These functions provide the necessary support for ensuring FPSIMD 1280 * save/restore in the contexts from which EFI is used. 1281 * 1282 * Do not use them for any other purpose -- if tempted to do so, you are 1283 * either doing something wrong or you need to propose some refactoring. 1284 */ 1285 1286 /* 1287 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call 1288 */ 1289 void __efi_fpsimd_begin(void) 1290 { 1291 if (!system_supports_fpsimd()) 1292 return; 1293 1294 WARN_ON(preemptible()); 1295 1296 if (may_use_simd()) { 1297 kernel_neon_begin(); 1298 } else { 1299 /* 1300 * If !efi_sve_state, SVE can't be in use yet and doesn't need 1301 * preserving: 1302 */ 1303 if (system_supports_sve() && likely(efi_sve_state)) { 1304 char *sve_state = this_cpu_ptr(efi_sve_state); 1305 1306 __this_cpu_write(efi_sve_state_used, true); 1307 1308 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl), 1309 &this_cpu_ptr(&efi_fpsimd_state)->fpsr); 1310 } else { 1311 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); 1312 } 1313 1314 __this_cpu_write(efi_fpsimd_state_used, true); 1315 } 1316 } 1317 1318 /* 1319 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call 1320 */ 1321 void __efi_fpsimd_end(void) 1322 { 1323 if (!system_supports_fpsimd()) 1324 return; 1325 1326 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) { 1327 kernel_neon_end(); 1328 } else { 1329 if (system_supports_sve() && 1330 likely(__this_cpu_read(efi_sve_state_used))) { 1331 char const *sve_state = this_cpu_ptr(efi_sve_state); 1332 1333 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl), 1334 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1335 sve_vq_from_vl(sve_get_vl()) - 1); 1336 1337 __this_cpu_write(efi_sve_state_used, false); 1338 } else { 1339 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); 1340 } 1341 } 1342 } 1343 1344 #endif /* CONFIG_EFI */ 1345 1346 #endif /* CONFIG_KERNEL_MODE_NEON */ 1347 1348 #ifdef CONFIG_CPU_PM 1349 static int fpsimd_cpu_pm_notifier(struct notifier_block *self, 1350 unsigned long cmd, void *v) 1351 { 1352 switch (cmd) { 1353 case CPU_PM_ENTER: 1354 fpsimd_save_and_flush_cpu_state(); 1355 break; 1356 case CPU_PM_EXIT: 1357 break; 1358 case CPU_PM_ENTER_FAILED: 1359 default: 1360 return NOTIFY_DONE; 1361 } 1362 return NOTIFY_OK; 1363 } 1364 1365 static struct notifier_block fpsimd_cpu_pm_notifier_block = { 1366 .notifier_call = fpsimd_cpu_pm_notifier, 1367 }; 1368 1369 static void __init fpsimd_pm_init(void) 1370 { 1371 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); 1372 } 1373 1374 #else 1375 static inline void fpsimd_pm_init(void) { } 1376 #endif /* CONFIG_CPU_PM */ 1377 1378 #ifdef CONFIG_HOTPLUG_CPU 1379 static int fpsimd_cpu_dead(unsigned int cpu) 1380 { 1381 per_cpu(fpsimd_last_state.st, cpu) = NULL; 1382 return 0; 1383 } 1384 1385 static inline void fpsimd_hotplug_init(void) 1386 { 1387 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead", 1388 NULL, fpsimd_cpu_dead); 1389 } 1390 1391 #else 1392 static inline void fpsimd_hotplug_init(void) { } 1393 #endif 1394 1395 /* 1396 * FP/SIMD support code initialisation. 1397 */ 1398 static int __init fpsimd_init(void) 1399 { 1400 if (cpu_have_named_feature(FP)) { 1401 fpsimd_pm_init(); 1402 fpsimd_hotplug_init(); 1403 } else { 1404 pr_notice("Floating-point is not implemented\n"); 1405 } 1406 1407 if (!cpu_have_named_feature(ASIMD)) 1408 pr_notice("Advanced SIMD is not implemented\n"); 1409 1410 return sve_sysctl_init(); 1411 } 1412 core_initcall(fpsimd_init); 1413