1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FP/SIMD context switching and fault handling 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/bottom_half.h> 12 #include <linux/bug.h> 13 #include <linux/cache.h> 14 #include <linux/compat.h> 15 #include <linux/compiler.h> 16 #include <linux/cpu.h> 17 #include <linux/cpu_pm.h> 18 #include <linux/kernel.h> 19 #include <linux/linkage.h> 20 #include <linux/irqflags.h> 21 #include <linux/init.h> 22 #include <linux/percpu.h> 23 #include <linux/prctl.h> 24 #include <linux/preempt.h> 25 #include <linux/ptrace.h> 26 #include <linux/sched/signal.h> 27 #include <linux/sched/task_stack.h> 28 #include <linux/signal.h> 29 #include <linux/slab.h> 30 #include <linux/stddef.h> 31 #include <linux/sysctl.h> 32 #include <linux/swab.h> 33 34 #include <asm/esr.h> 35 #include <asm/exception.h> 36 #include <asm/fpsimd.h> 37 #include <asm/cpufeature.h> 38 #include <asm/cputype.h> 39 #include <asm/neon.h> 40 #include <asm/processor.h> 41 #include <asm/simd.h> 42 #include <asm/sigcontext.h> 43 #include <asm/sysreg.h> 44 #include <asm/traps.h> 45 #include <asm/virt.h> 46 47 #define FPEXC_IOF (1 << 0) 48 #define FPEXC_DZF (1 << 1) 49 #define FPEXC_OFF (1 << 2) 50 #define FPEXC_UFF (1 << 3) 51 #define FPEXC_IXF (1 << 4) 52 #define FPEXC_IDF (1 << 7) 53 54 /* 55 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.) 56 * 57 * In order to reduce the number of times the FPSIMD state is needlessly saved 58 * and restored, we need to keep track of two things: 59 * (a) for each task, we need to remember which CPU was the last one to have 60 * the task's FPSIMD state loaded into its FPSIMD registers; 61 * (b) for each CPU, we need to remember which task's userland FPSIMD state has 62 * been loaded into its FPSIMD registers most recently, or whether it has 63 * been used to perform kernel mode NEON in the meantime. 64 * 65 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to 66 * the id of the current CPU every time the state is loaded onto a CPU. For (b), 67 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the 68 * address of the userland FPSIMD state of the task that was loaded onto the CPU 69 * the most recently, or NULL if kernel mode NEON has been performed after that. 70 * 71 * With this in place, we no longer have to restore the next FPSIMD state right 72 * when switching between tasks. Instead, we can defer this check to userland 73 * resume, at which time we verify whether the CPU's fpsimd_last_state and the 74 * task's fpsimd_cpu are still mutually in sync. If this is the case, we 75 * can omit the FPSIMD restore. 76 * 77 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to 78 * indicate whether or not the userland FPSIMD state of the current task is 79 * present in the registers. The flag is set unless the FPSIMD registers of this 80 * CPU currently contain the most recent userland FPSIMD state of the current 81 * task. 82 * 83 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may 84 * save the task's FPSIMD context back to task_struct from softirq context. 85 * To prevent this from racing with the manipulation of the task's FPSIMD state 86 * from task context and thereby corrupting the state, it is necessary to 87 * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE 88 * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to 89 * run but prevent them to use FPSIMD. 90 * 91 * For a certain task, the sequence may look something like this: 92 * - the task gets scheduled in; if both the task's fpsimd_cpu field 93 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu 94 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is 95 * cleared, otherwise it is set; 96 * 97 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's 98 * userland FPSIMD state is copied from memory to the registers, the task's 99 * fpsimd_cpu field is set to the id of the current CPU, the current 100 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the 101 * TIF_FOREIGN_FPSTATE flag is cleared; 102 * 103 * - the task executes an ordinary syscall; upon return to userland, the 104 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is 105 * restored; 106 * 107 * - the task executes a syscall which executes some NEON instructions; this is 108 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD 109 * register contents to memory, clears the fpsimd_last_state per-cpu variable 110 * and sets the TIF_FOREIGN_FPSTATE flag; 111 * 112 * - the task gets preempted after kernel_neon_end() is called; as we have not 113 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so 114 * whatever is in the FPSIMD registers is not saved to memory, but discarded. 115 */ 116 struct fpsimd_last_state_struct { 117 struct user_fpsimd_state *st; 118 void *sve_state; 119 unsigned int sve_vl; 120 }; 121 122 static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state); 123 124 __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = { 125 #ifdef CONFIG_ARM64_SVE 126 [ARM64_VEC_SVE] = { 127 .type = ARM64_VEC_SVE, 128 .name = "SVE", 129 .min_vl = SVE_VL_MIN, 130 .max_vl = SVE_VL_MIN, 131 .max_virtualisable_vl = SVE_VL_MIN, 132 }, 133 #endif 134 }; 135 136 static unsigned int vec_vl_inherit_flag(enum vec_type type) 137 { 138 switch (type) { 139 case ARM64_VEC_SVE: 140 return TIF_SVE_VL_INHERIT; 141 default: 142 WARN_ON_ONCE(1); 143 return 0; 144 } 145 } 146 147 struct vl_config { 148 int __default_vl; /* Default VL for tasks */ 149 }; 150 151 static struct vl_config vl_config[ARM64_VEC_MAX]; 152 153 static inline int get_default_vl(enum vec_type type) 154 { 155 return READ_ONCE(vl_config[type].__default_vl); 156 } 157 158 #ifdef CONFIG_ARM64_SVE 159 160 static inline int get_sve_default_vl(void) 161 { 162 return get_default_vl(ARM64_VEC_SVE); 163 } 164 165 static inline void set_default_vl(enum vec_type type, int val) 166 { 167 WRITE_ONCE(vl_config[type].__default_vl, val); 168 } 169 170 static inline void set_sve_default_vl(int val) 171 { 172 set_default_vl(ARM64_VEC_SVE, val); 173 } 174 175 static void __percpu *efi_sve_state; 176 177 #else /* ! CONFIG_ARM64_SVE */ 178 179 /* Dummy declaration for code that will be optimised out: */ 180 extern void __percpu *efi_sve_state; 181 182 #endif /* ! CONFIG_ARM64_SVE */ 183 184 DEFINE_PER_CPU(bool, fpsimd_context_busy); 185 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy); 186 187 static void fpsimd_bind_task_to_cpu(void); 188 189 static void __get_cpu_fpsimd_context(void) 190 { 191 bool busy = __this_cpu_xchg(fpsimd_context_busy, true); 192 193 WARN_ON(busy); 194 } 195 196 /* 197 * Claim ownership of the CPU FPSIMD context for use by the calling context. 198 * 199 * The caller may freely manipulate the FPSIMD context metadata until 200 * put_cpu_fpsimd_context() is called. 201 * 202 * The double-underscore version must only be called if you know the task 203 * can't be preempted. 204 */ 205 static void get_cpu_fpsimd_context(void) 206 { 207 local_bh_disable(); 208 __get_cpu_fpsimd_context(); 209 } 210 211 static void __put_cpu_fpsimd_context(void) 212 { 213 bool busy = __this_cpu_xchg(fpsimd_context_busy, false); 214 215 WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */ 216 } 217 218 /* 219 * Release the CPU FPSIMD context. 220 * 221 * Must be called from a context in which get_cpu_fpsimd_context() was 222 * previously called, with no call to put_cpu_fpsimd_context() in the 223 * meantime. 224 */ 225 static void put_cpu_fpsimd_context(void) 226 { 227 __put_cpu_fpsimd_context(); 228 local_bh_enable(); 229 } 230 231 static bool have_cpu_fpsimd_context(void) 232 { 233 return !preemptible() && __this_cpu_read(fpsimd_context_busy); 234 } 235 236 /* 237 * Call __sve_free() directly only if you know task can't be scheduled 238 * or preempted. 239 */ 240 static void __sve_free(struct task_struct *task) 241 { 242 kfree(task->thread.sve_state); 243 task->thread.sve_state = NULL; 244 } 245 246 static void sve_free(struct task_struct *task) 247 { 248 WARN_ON(test_tsk_thread_flag(task, TIF_SVE)); 249 250 __sve_free(task); 251 } 252 253 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type) 254 { 255 return task->thread.vl[type]; 256 } 257 258 void task_set_vl(struct task_struct *task, enum vec_type type, 259 unsigned long vl) 260 { 261 task->thread.vl[type] = vl; 262 } 263 264 unsigned int task_get_vl_onexec(const struct task_struct *task, 265 enum vec_type type) 266 { 267 return task->thread.vl_onexec[type]; 268 } 269 270 void task_set_vl_onexec(struct task_struct *task, enum vec_type type, 271 unsigned long vl) 272 { 273 task->thread.vl_onexec[type] = vl; 274 } 275 276 /* 277 * TIF_SVE controls whether a task can use SVE without trapping while 278 * in userspace, and also the way a task's FPSIMD/SVE state is stored 279 * in thread_struct. 280 * 281 * The kernel uses this flag to track whether a user task is actively 282 * using SVE, and therefore whether full SVE register state needs to 283 * be tracked. If not, the cheaper FPSIMD context handling code can 284 * be used instead of the more costly SVE equivalents. 285 * 286 * * TIF_SVE set: 287 * 288 * The task can execute SVE instructions while in userspace without 289 * trapping to the kernel. 290 * 291 * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the 292 * corresponding Zn), P0-P15 and FFR are encoded in in 293 * task->thread.sve_state, formatted appropriately for vector 294 * length task->thread.sve_vl. 295 * 296 * task->thread.sve_state must point to a valid buffer at least 297 * sve_state_size(task) bytes in size. 298 * 299 * During any syscall, the kernel may optionally clear TIF_SVE and 300 * discard the vector state except for the FPSIMD subset. 301 * 302 * * TIF_SVE clear: 303 * 304 * An attempt by the user task to execute an SVE instruction causes 305 * do_sve_acc() to be called, which does some preparation and then 306 * sets TIF_SVE. 307 * 308 * When stored, FPSIMD registers V0-V31 are encoded in 309 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are 310 * logically zero but not stored anywhere; P0-P15 and FFR are not 311 * stored and have unspecified values from userspace's point of 312 * view. For hygiene purposes, the kernel zeroes them on next use, 313 * but userspace is discouraged from relying on this. 314 * 315 * task->thread.sve_state does not need to be non-NULL, valid or any 316 * particular size: it must not be dereferenced. 317 * 318 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state 319 * irrespective of whether TIF_SVE is clear or set, since these are 320 * not vector length dependent. 321 */ 322 323 /* 324 * Update current's FPSIMD/SVE registers from thread_struct. 325 * 326 * This function should be called only when the FPSIMD/SVE state in 327 * thread_struct is known to be up to date, when preparing to enter 328 * userspace. 329 */ 330 static void task_fpsimd_load(void) 331 { 332 WARN_ON(!system_supports_fpsimd()); 333 WARN_ON(!have_cpu_fpsimd_context()); 334 335 if (IS_ENABLED(CONFIG_ARM64_SVE) && test_thread_flag(TIF_SVE)) { 336 sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1); 337 sve_load_state(sve_pffr(¤t->thread), 338 ¤t->thread.uw.fpsimd_state.fpsr, true); 339 } else { 340 fpsimd_load_state(¤t->thread.uw.fpsimd_state); 341 } 342 } 343 344 /* 345 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to 346 * date with respect to the CPU registers. 347 */ 348 static void fpsimd_save(void) 349 { 350 struct fpsimd_last_state_struct const *last = 351 this_cpu_ptr(&fpsimd_last_state); 352 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */ 353 354 WARN_ON(!system_supports_fpsimd()); 355 WARN_ON(!have_cpu_fpsimd_context()); 356 357 if (test_thread_flag(TIF_FOREIGN_FPSTATE)) 358 return; 359 360 if (IS_ENABLED(CONFIG_ARM64_SVE) && 361 test_thread_flag(TIF_SVE)) { 362 if (WARN_ON(sve_get_vl() != last->sve_vl)) { 363 /* 364 * Can't save the user regs, so current would 365 * re-enter user with corrupt state. 366 * There's no way to recover, so kill it: 367 */ 368 force_signal_inject(SIGKILL, SI_KERNEL, 0, 0); 369 return; 370 } 371 372 sve_save_state((char *)last->sve_state + 373 sve_ffr_offset(last->sve_vl), 374 &last->st->fpsr, true); 375 } else { 376 fpsimd_save_state(last->st); 377 } 378 } 379 380 /* 381 * All vector length selection from userspace comes through here. 382 * We're on a slow path, so some sanity-checks are included. 383 * If things go wrong there's a bug somewhere, but try to fall back to a 384 * safe choice. 385 */ 386 static unsigned int find_supported_vector_length(enum vec_type type, 387 unsigned int vl) 388 { 389 struct vl_info *info = &vl_info[type]; 390 int bit; 391 int max_vl = info->max_vl; 392 393 if (WARN_ON(!sve_vl_valid(vl))) 394 vl = info->min_vl; 395 396 if (WARN_ON(!sve_vl_valid(max_vl))) 397 max_vl = info->min_vl; 398 399 if (vl > max_vl) 400 vl = max_vl; 401 402 bit = find_next_bit(info->vq_map, SVE_VQ_MAX, 403 __vq_to_bit(sve_vq_from_vl(vl))); 404 return sve_vl_from_vq(__bit_to_vq(bit)); 405 } 406 407 #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL) 408 409 static int sve_proc_do_default_vl(struct ctl_table *table, int write, 410 void *buffer, size_t *lenp, loff_t *ppos) 411 { 412 struct vl_info *info = &vl_info[ARM64_VEC_SVE]; 413 int ret; 414 int vl = get_sve_default_vl(); 415 struct ctl_table tmp_table = { 416 .data = &vl, 417 .maxlen = sizeof(vl), 418 }; 419 420 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos); 421 if (ret || !write) 422 return ret; 423 424 /* Writing -1 has the special meaning "set to max": */ 425 if (vl == -1) 426 vl = info->max_vl; 427 428 if (!sve_vl_valid(vl)) 429 return -EINVAL; 430 431 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, vl)); 432 return 0; 433 } 434 435 static struct ctl_table sve_default_vl_table[] = { 436 { 437 .procname = "sve_default_vector_length", 438 .mode = 0644, 439 .proc_handler = sve_proc_do_default_vl, 440 }, 441 { } 442 }; 443 444 static int __init sve_sysctl_init(void) 445 { 446 if (system_supports_sve()) 447 if (!register_sysctl("abi", sve_default_vl_table)) 448 return -EINVAL; 449 450 return 0; 451 } 452 453 #else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 454 static int __init sve_sysctl_init(void) { return 0; } 455 #endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 456 457 #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ 458 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) 459 460 #ifdef CONFIG_CPU_BIG_ENDIAN 461 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 462 { 463 u64 a = swab64(x); 464 u64 b = swab64(x >> 64); 465 466 return ((__uint128_t)a << 64) | b; 467 } 468 #else 469 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 470 { 471 return x; 472 } 473 #endif 474 475 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) 476 477 static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst, 478 unsigned int vq) 479 { 480 unsigned int i; 481 __uint128_t *p; 482 483 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 484 p = (__uint128_t *)ZREG(sst, vq, i); 485 *p = arm64_cpu_to_le128(fst->vregs[i]); 486 } 487 } 488 489 /* 490 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to 491 * task->thread.sve_state. 492 * 493 * Task can be a non-runnable task, or current. In the latter case, 494 * the caller must have ownership of the cpu FPSIMD context before calling 495 * this function. 496 * task->thread.sve_state must point to at least sve_state_size(task) 497 * bytes of allocated kernel memory. 498 * task->thread.uw.fpsimd_state must be up to date before calling this 499 * function. 500 */ 501 static void fpsimd_to_sve(struct task_struct *task) 502 { 503 unsigned int vq; 504 void *sst = task->thread.sve_state; 505 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 506 507 if (!system_supports_sve()) 508 return; 509 510 vq = sve_vq_from_vl(task_get_sve_vl(task)); 511 __fpsimd_to_sve(sst, fst, vq); 512 } 513 514 /* 515 * Transfer the SVE state in task->thread.sve_state to 516 * task->thread.uw.fpsimd_state. 517 * 518 * Task can be a non-runnable task, or current. In the latter case, 519 * the caller must have ownership of the cpu FPSIMD context before calling 520 * this function. 521 * task->thread.sve_state must point to at least sve_state_size(task) 522 * bytes of allocated kernel memory. 523 * task->thread.sve_state must be up to date before calling this function. 524 */ 525 static void sve_to_fpsimd(struct task_struct *task) 526 { 527 unsigned int vq; 528 void const *sst = task->thread.sve_state; 529 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state; 530 unsigned int i; 531 __uint128_t const *p; 532 533 if (!system_supports_sve()) 534 return; 535 536 vq = sve_vq_from_vl(task_get_sve_vl(task)); 537 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 538 p = (__uint128_t const *)ZREG(sst, vq, i); 539 fst->vregs[i] = arm64_le128_to_cpu(*p); 540 } 541 } 542 543 #ifdef CONFIG_ARM64_SVE 544 545 /* 546 * Return how many bytes of memory are required to store the full SVE 547 * state for task, given task's currently configured vector length. 548 */ 549 static size_t sve_state_size(struct task_struct const *task) 550 { 551 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(task_get_sve_vl(task))); 552 } 553 554 /* 555 * Ensure that task->thread.sve_state is allocated and sufficiently large. 556 * 557 * This function should be used only in preparation for replacing 558 * task->thread.sve_state with new data. The memory is always zeroed 559 * here to prevent stale data from showing through: this is done in 560 * the interest of testability and predictability: except in the 561 * do_sve_acc() case, there is no ABI requirement to hide stale data 562 * written previously be task. 563 */ 564 void sve_alloc(struct task_struct *task) 565 { 566 if (task->thread.sve_state) { 567 memset(task->thread.sve_state, 0, sve_state_size(task)); 568 return; 569 } 570 571 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */ 572 task->thread.sve_state = 573 kzalloc(sve_state_size(task), GFP_KERNEL); 574 } 575 576 577 /* 578 * Ensure that task->thread.sve_state is up to date with respect to 579 * the user task, irrespective of when SVE is in use or not. 580 * 581 * This should only be called by ptrace. task must be non-runnable. 582 * task->thread.sve_state must point to at least sve_state_size(task) 583 * bytes of allocated kernel memory. 584 */ 585 void fpsimd_sync_to_sve(struct task_struct *task) 586 { 587 if (!test_tsk_thread_flag(task, TIF_SVE)) 588 fpsimd_to_sve(task); 589 } 590 591 /* 592 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to 593 * the user task, irrespective of whether SVE is in use or not. 594 * 595 * This should only be called by ptrace. task must be non-runnable. 596 * task->thread.sve_state must point to at least sve_state_size(task) 597 * bytes of allocated kernel memory. 598 */ 599 void sve_sync_to_fpsimd(struct task_struct *task) 600 { 601 if (test_tsk_thread_flag(task, TIF_SVE)) 602 sve_to_fpsimd(task); 603 } 604 605 /* 606 * Ensure that task->thread.sve_state is up to date with respect to 607 * the task->thread.uw.fpsimd_state. 608 * 609 * This should only be called by ptrace to merge new FPSIMD register 610 * values into a task for which SVE is currently active. 611 * task must be non-runnable. 612 * task->thread.sve_state must point to at least sve_state_size(task) 613 * bytes of allocated kernel memory. 614 * task->thread.uw.fpsimd_state must already have been initialised with 615 * the new FPSIMD register values to be merged in. 616 */ 617 void sve_sync_from_fpsimd_zeropad(struct task_struct *task) 618 { 619 unsigned int vq; 620 void *sst = task->thread.sve_state; 621 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 622 623 if (!test_tsk_thread_flag(task, TIF_SVE)) 624 return; 625 626 vq = sve_vq_from_vl(task_get_sve_vl(task)); 627 628 memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); 629 __fpsimd_to_sve(sst, fst, vq); 630 } 631 632 int sve_set_vector_length(struct task_struct *task, 633 unsigned long vl, unsigned long flags) 634 { 635 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | 636 PR_SVE_SET_VL_ONEXEC)) 637 return -EINVAL; 638 639 if (!sve_vl_valid(vl)) 640 return -EINVAL; 641 642 /* 643 * Clamp to the maximum vector length that VL-agnostic SVE code can 644 * work with. A flag may be assigned in the future to allow setting 645 * of larger vector lengths without confusing older software. 646 */ 647 if (vl > SVE_VL_ARCH_MAX) 648 vl = SVE_VL_ARCH_MAX; 649 650 vl = find_supported_vector_length(ARM64_VEC_SVE, vl); 651 652 if (flags & (PR_SVE_VL_INHERIT | 653 PR_SVE_SET_VL_ONEXEC)) 654 task_set_sve_vl_onexec(task, vl); 655 else 656 /* Reset VL to system default on next exec: */ 657 task_set_sve_vl_onexec(task, 0); 658 659 /* Only actually set the VL if not deferred: */ 660 if (flags & PR_SVE_SET_VL_ONEXEC) 661 goto out; 662 663 if (vl == task_get_sve_vl(task)) 664 goto out; 665 666 /* 667 * To ensure the FPSIMD bits of the SVE vector registers are preserved, 668 * write any live register state back to task_struct, and convert to a 669 * non-SVE thread. 670 */ 671 if (task == current) { 672 get_cpu_fpsimd_context(); 673 674 fpsimd_save(); 675 } 676 677 fpsimd_flush_task_state(task); 678 if (test_and_clear_tsk_thread_flag(task, TIF_SVE)) 679 sve_to_fpsimd(task); 680 681 if (task == current) 682 put_cpu_fpsimd_context(); 683 684 /* 685 * Force reallocation of task SVE state to the correct size 686 * on next use: 687 */ 688 sve_free(task); 689 690 task_set_sve_vl(task, vl); 691 692 out: 693 update_tsk_thread_flag(task, TIF_SVE_VL_INHERIT, 694 flags & PR_SVE_VL_INHERIT); 695 696 return 0; 697 } 698 699 /* 700 * Encode the current vector length and flags for return. 701 * This is only required for prctl(): ptrace has separate fields 702 * 703 * flags are as for sve_set_vector_length(). 704 */ 705 static int sve_prctl_status(unsigned long flags) 706 { 707 int ret; 708 709 if (flags & PR_SVE_SET_VL_ONEXEC) 710 ret = task_get_sve_vl_onexec(current); 711 else 712 ret = task_get_sve_vl(current); 713 714 if (test_thread_flag(TIF_SVE_VL_INHERIT)) 715 ret |= PR_SVE_VL_INHERIT; 716 717 return ret; 718 } 719 720 /* PR_SVE_SET_VL */ 721 int sve_set_current_vl(unsigned long arg) 722 { 723 unsigned long vl, flags; 724 int ret; 725 726 vl = arg & PR_SVE_VL_LEN_MASK; 727 flags = arg & ~vl; 728 729 if (!system_supports_sve() || is_compat_task()) 730 return -EINVAL; 731 732 ret = sve_set_vector_length(current, vl, flags); 733 if (ret) 734 return ret; 735 736 return sve_prctl_status(flags); 737 } 738 739 /* PR_SVE_GET_VL */ 740 int sve_get_current_vl(void) 741 { 742 if (!system_supports_sve() || is_compat_task()) 743 return -EINVAL; 744 745 return sve_prctl_status(0); 746 } 747 748 static void vec_probe_vqs(struct vl_info *info, 749 DECLARE_BITMAP(map, SVE_VQ_MAX)) 750 { 751 unsigned int vq, vl; 752 753 bitmap_zero(map, SVE_VQ_MAX); 754 755 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) { 756 write_vl(info->type, vq - 1); /* self-syncing */ 757 vl = sve_get_vl(); 758 vq = sve_vq_from_vl(vl); /* skip intervening lengths */ 759 set_bit(__vq_to_bit(vq), map); 760 } 761 } 762 763 /* 764 * Initialise the set of known supported VQs for the boot CPU. 765 * This is called during kernel boot, before secondary CPUs are brought up. 766 */ 767 void __init vec_init_vq_map(enum vec_type type) 768 { 769 struct vl_info *info = &vl_info[type]; 770 vec_probe_vqs(info, info->vq_map); 771 bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX); 772 } 773 774 /* 775 * If we haven't committed to the set of supported VQs yet, filter out 776 * those not supported by the current CPU. 777 * This function is called during the bring-up of early secondary CPUs only. 778 */ 779 void vec_update_vq_map(enum vec_type type) 780 { 781 struct vl_info *info = &vl_info[type]; 782 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 783 784 vec_probe_vqs(info, tmp_map); 785 bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX); 786 bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map, 787 SVE_VQ_MAX); 788 } 789 790 /* 791 * Check whether the current CPU supports all VQs in the committed set. 792 * This function is called during the bring-up of late secondary CPUs only. 793 */ 794 int vec_verify_vq_map(enum vec_type type) 795 { 796 struct vl_info *info = &vl_info[type]; 797 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 798 unsigned long b; 799 800 vec_probe_vqs(info, tmp_map); 801 802 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 803 if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) { 804 pr_warn("%s: cpu%d: Required vector length(s) missing\n", 805 info->name, smp_processor_id()); 806 return -EINVAL; 807 } 808 809 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) 810 return 0; 811 812 /* 813 * For KVM, it is necessary to ensure that this CPU doesn't 814 * support any vector length that guests may have probed as 815 * unsupported. 816 */ 817 818 /* Recover the set of supported VQs: */ 819 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 820 /* Find VQs supported that are not globally supported: */ 821 bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX); 822 823 /* Find the lowest such VQ, if any: */ 824 b = find_last_bit(tmp_map, SVE_VQ_MAX); 825 if (b >= SVE_VQ_MAX) 826 return 0; /* no mismatches */ 827 828 /* 829 * Mismatches above sve_max_virtualisable_vl are fine, since 830 * no guest is allowed to configure ZCR_EL2.LEN to exceed this: 831 */ 832 if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) { 833 pr_warn("%s: cpu%d: Unsupported vector length(s) present\n", 834 info->name, smp_processor_id()); 835 return -EINVAL; 836 } 837 838 return 0; 839 } 840 841 static void __init sve_efi_setup(void) 842 { 843 struct vl_info *info = &vl_info[ARM64_VEC_SVE]; 844 845 if (!IS_ENABLED(CONFIG_EFI)) 846 return; 847 848 /* 849 * alloc_percpu() warns and prints a backtrace if this goes wrong. 850 * This is evidence of a crippled system and we are returning void, 851 * so no attempt is made to handle this situation here. 852 */ 853 if (!sve_vl_valid(info->max_vl)) 854 goto fail; 855 856 efi_sve_state = __alloc_percpu( 857 SVE_SIG_REGS_SIZE(sve_vq_from_vl(info->max_vl)), SVE_VQ_BYTES); 858 if (!efi_sve_state) 859 goto fail; 860 861 return; 862 863 fail: 864 panic("Cannot allocate percpu memory for EFI SVE save/restore"); 865 } 866 867 /* 868 * Enable SVE for EL1. 869 * Intended for use by the cpufeatures code during CPU boot. 870 */ 871 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 872 { 873 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); 874 isb(); 875 } 876 877 /* 878 * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE 879 * vector length. 880 * 881 * Use only if SVE is present. 882 * This function clobbers the SVE vector length. 883 */ 884 u64 read_zcr_features(void) 885 { 886 u64 zcr; 887 unsigned int vq_max; 888 889 /* 890 * Set the maximum possible VL, and write zeroes to all other 891 * bits to see if they stick. 892 */ 893 sve_kernel_enable(NULL); 894 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); 895 896 zcr = read_sysreg_s(SYS_ZCR_EL1); 897 zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ 898 vq_max = sve_vq_from_vl(sve_get_vl()); 899 zcr |= vq_max - 1; /* set LEN field to maximum effective value */ 900 901 return zcr; 902 } 903 904 void __init sve_setup(void) 905 { 906 struct vl_info *info = &vl_info[ARM64_VEC_SVE]; 907 u64 zcr; 908 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 909 unsigned long b; 910 911 if (!system_supports_sve()) 912 return; 913 914 /* 915 * The SVE architecture mandates support for 128-bit vectors, 916 * so sve_vq_map must have at least SVE_VQ_MIN set. 917 * If something went wrong, at least try to patch it up: 918 */ 919 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map))) 920 set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map); 921 922 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 923 info->max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1); 924 925 /* 926 * Sanity-check that the max VL we determined through CPU features 927 * corresponds properly to sve_vq_map. If not, do our best: 928 */ 929 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SVE, 930 info->max_vl))) 931 info->max_vl = find_supported_vector_length(ARM64_VEC_SVE, 932 info->max_vl); 933 934 /* 935 * For the default VL, pick the maximum supported value <= 64. 936 * VL == 64 is guaranteed not to grow the signal frame. 937 */ 938 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64)); 939 940 bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map, 941 SVE_VQ_MAX); 942 943 b = find_last_bit(tmp_map, SVE_VQ_MAX); 944 if (b >= SVE_VQ_MAX) 945 /* No non-virtualisable VLs found */ 946 info->max_virtualisable_vl = SVE_VQ_MAX; 947 else if (WARN_ON(b == SVE_VQ_MAX - 1)) 948 /* No virtualisable VLs? This is architecturally forbidden. */ 949 info->max_virtualisable_vl = SVE_VQ_MIN; 950 else /* b + 1 < SVE_VQ_MAX */ 951 info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1)); 952 953 if (info->max_virtualisable_vl > info->max_vl) 954 info->max_virtualisable_vl = info->max_vl; 955 956 pr_info("%s: maximum available vector length %u bytes per vector\n", 957 info->name, info->max_vl); 958 pr_info("%s: default vector length %u bytes per vector\n", 959 info->name, get_sve_default_vl()); 960 961 /* KVM decides whether to support mismatched systems. Just warn here: */ 962 if (sve_max_virtualisable_vl() < sve_max_vl()) 963 pr_warn("%s: unvirtualisable vector lengths present\n", 964 info->name); 965 966 sve_efi_setup(); 967 } 968 969 /* 970 * Called from the put_task_struct() path, which cannot get here 971 * unless dead_task is really dead and not schedulable. 972 */ 973 void fpsimd_release_task(struct task_struct *dead_task) 974 { 975 __sve_free(dead_task); 976 } 977 978 #endif /* CONFIG_ARM64_SVE */ 979 980 /* 981 * Trapped SVE access 982 * 983 * Storage is allocated for the full SVE state, the current FPSIMD 984 * register contents are migrated across, and the access trap is 985 * disabled. 986 * 987 * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state() 988 * would have disabled the SVE access trap for userspace during 989 * ret_to_user, making an SVE access trap impossible in that case. 990 */ 991 void do_sve_acc(unsigned int esr, struct pt_regs *regs) 992 { 993 /* Even if we chose not to use SVE, the hardware could still trap: */ 994 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) { 995 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 996 return; 997 } 998 999 sve_alloc(current); 1000 if (!current->thread.sve_state) { 1001 force_sig(SIGKILL); 1002 return; 1003 } 1004 1005 get_cpu_fpsimd_context(); 1006 1007 if (test_and_set_thread_flag(TIF_SVE)) 1008 WARN_ON(1); /* SVE access shouldn't have trapped */ 1009 1010 /* 1011 * Convert the FPSIMD state to SVE, zeroing all the state that 1012 * is not shared with FPSIMD. If (as is likely) the current 1013 * state is live in the registers then do this there and 1014 * update our metadata for the current task including 1015 * disabling the trap, otherwise update our in-memory copy. 1016 */ 1017 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 1018 unsigned long vq_minus_one = 1019 sve_vq_from_vl(task_get_sve_vl(current)) - 1; 1020 sve_set_vq(vq_minus_one); 1021 sve_flush_live(true, vq_minus_one); 1022 fpsimd_bind_task_to_cpu(); 1023 } else { 1024 fpsimd_to_sve(current); 1025 } 1026 1027 put_cpu_fpsimd_context(); 1028 } 1029 1030 /* 1031 * Trapped FP/ASIMD access. 1032 */ 1033 void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs) 1034 { 1035 /* TODO: implement lazy context saving/restoring */ 1036 WARN_ON(1); 1037 } 1038 1039 /* 1040 * Raise a SIGFPE for the current process. 1041 */ 1042 void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs) 1043 { 1044 unsigned int si_code = FPE_FLTUNK; 1045 1046 if (esr & ESR_ELx_FP_EXC_TFV) { 1047 if (esr & FPEXC_IOF) 1048 si_code = FPE_FLTINV; 1049 else if (esr & FPEXC_DZF) 1050 si_code = FPE_FLTDIV; 1051 else if (esr & FPEXC_OFF) 1052 si_code = FPE_FLTOVF; 1053 else if (esr & FPEXC_UFF) 1054 si_code = FPE_FLTUND; 1055 else if (esr & FPEXC_IXF) 1056 si_code = FPE_FLTRES; 1057 } 1058 1059 send_sig_fault(SIGFPE, si_code, 1060 (void __user *)instruction_pointer(regs), 1061 current); 1062 } 1063 1064 void fpsimd_thread_switch(struct task_struct *next) 1065 { 1066 bool wrong_task, wrong_cpu; 1067 1068 if (!system_supports_fpsimd()) 1069 return; 1070 1071 __get_cpu_fpsimd_context(); 1072 1073 /* Save unsaved fpsimd state, if any: */ 1074 fpsimd_save(); 1075 1076 /* 1077 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's 1078 * state. For kernel threads, FPSIMD registers are never loaded 1079 * and wrong_task and wrong_cpu will always be true. 1080 */ 1081 wrong_task = __this_cpu_read(fpsimd_last_state.st) != 1082 &next->thread.uw.fpsimd_state; 1083 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id(); 1084 1085 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE, 1086 wrong_task || wrong_cpu); 1087 1088 __put_cpu_fpsimd_context(); 1089 } 1090 1091 static void fpsimd_flush_thread_vl(enum vec_type type) 1092 { 1093 int vl, supported_vl; 1094 1095 /* 1096 * Reset the task vector length as required. This is where we 1097 * ensure that all user tasks have a valid vector length 1098 * configured: no kernel task can become a user task without 1099 * an exec and hence a call to this function. By the time the 1100 * first call to this function is made, all early hardware 1101 * probing is complete, so __sve_default_vl should be valid. 1102 * If a bug causes this to go wrong, we make some noise and 1103 * try to fudge thread.sve_vl to a safe value here. 1104 */ 1105 vl = task_get_vl_onexec(current, type); 1106 if (!vl) 1107 vl = get_default_vl(type); 1108 1109 if (WARN_ON(!sve_vl_valid(vl))) 1110 vl = SVE_VL_MIN; 1111 1112 supported_vl = find_supported_vector_length(type, vl); 1113 if (WARN_ON(supported_vl != vl)) 1114 vl = supported_vl; 1115 1116 task_set_vl(current, type, vl); 1117 1118 /* 1119 * If the task is not set to inherit, ensure that the vector 1120 * length will be reset by a subsequent exec: 1121 */ 1122 if (!test_thread_flag(vec_vl_inherit_flag(type))) 1123 task_set_vl_onexec(current, type, 0); 1124 } 1125 1126 void fpsimd_flush_thread(void) 1127 { 1128 if (!system_supports_fpsimd()) 1129 return; 1130 1131 get_cpu_fpsimd_context(); 1132 1133 fpsimd_flush_task_state(current); 1134 memset(¤t->thread.uw.fpsimd_state, 0, 1135 sizeof(current->thread.uw.fpsimd_state)); 1136 1137 if (system_supports_sve()) { 1138 clear_thread_flag(TIF_SVE); 1139 sve_free(current); 1140 fpsimd_flush_thread_vl(ARM64_VEC_SVE); 1141 } 1142 1143 put_cpu_fpsimd_context(); 1144 } 1145 1146 /* 1147 * Save the userland FPSIMD state of 'current' to memory, but only if the state 1148 * currently held in the registers does in fact belong to 'current' 1149 */ 1150 void fpsimd_preserve_current_state(void) 1151 { 1152 if (!system_supports_fpsimd()) 1153 return; 1154 1155 get_cpu_fpsimd_context(); 1156 fpsimd_save(); 1157 put_cpu_fpsimd_context(); 1158 } 1159 1160 /* 1161 * Like fpsimd_preserve_current_state(), but ensure that 1162 * current->thread.uw.fpsimd_state is updated so that it can be copied to 1163 * the signal frame. 1164 */ 1165 void fpsimd_signal_preserve_current_state(void) 1166 { 1167 fpsimd_preserve_current_state(); 1168 if (test_thread_flag(TIF_SVE)) 1169 sve_to_fpsimd(current); 1170 } 1171 1172 /* 1173 * Associate current's FPSIMD context with this cpu 1174 * The caller must have ownership of the cpu FPSIMD context before calling 1175 * this function. 1176 */ 1177 static void fpsimd_bind_task_to_cpu(void) 1178 { 1179 struct fpsimd_last_state_struct *last = 1180 this_cpu_ptr(&fpsimd_last_state); 1181 1182 WARN_ON(!system_supports_fpsimd()); 1183 last->st = ¤t->thread.uw.fpsimd_state; 1184 last->sve_state = current->thread.sve_state; 1185 last->sve_vl = task_get_sve_vl(current); 1186 current->thread.fpsimd_cpu = smp_processor_id(); 1187 1188 if (system_supports_sve()) { 1189 /* Toggle SVE trapping for userspace if needed */ 1190 if (test_thread_flag(TIF_SVE)) 1191 sve_user_enable(); 1192 else 1193 sve_user_disable(); 1194 1195 /* Serialised by exception return to user */ 1196 } 1197 } 1198 1199 void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, 1200 unsigned int sve_vl) 1201 { 1202 struct fpsimd_last_state_struct *last = 1203 this_cpu_ptr(&fpsimd_last_state); 1204 1205 WARN_ON(!system_supports_fpsimd()); 1206 WARN_ON(!in_softirq() && !irqs_disabled()); 1207 1208 last->st = st; 1209 last->sve_state = sve_state; 1210 last->sve_vl = sve_vl; 1211 } 1212 1213 /* 1214 * Load the userland FPSIMD state of 'current' from memory, but only if the 1215 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD 1216 * state of 'current' 1217 */ 1218 void fpsimd_restore_current_state(void) 1219 { 1220 /* 1221 * For the tasks that were created before we detected the absence of 1222 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(), 1223 * e.g, init. This could be then inherited by the children processes. 1224 * If we later detect that the system doesn't support FP/SIMD, 1225 * we must clear the flag for all the tasks to indicate that the 1226 * FPSTATE is clean (as we can't have one) to avoid looping for ever in 1227 * do_notify_resume(). 1228 */ 1229 if (!system_supports_fpsimd()) { 1230 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1231 return; 1232 } 1233 1234 get_cpu_fpsimd_context(); 1235 1236 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { 1237 task_fpsimd_load(); 1238 fpsimd_bind_task_to_cpu(); 1239 } 1240 1241 put_cpu_fpsimd_context(); 1242 } 1243 1244 /* 1245 * Load an updated userland FPSIMD state for 'current' from memory and set the 1246 * flag that indicates that the FPSIMD register contents are the most recent 1247 * FPSIMD state of 'current' 1248 */ 1249 void fpsimd_update_current_state(struct user_fpsimd_state const *state) 1250 { 1251 if (WARN_ON(!system_supports_fpsimd())) 1252 return; 1253 1254 get_cpu_fpsimd_context(); 1255 1256 current->thread.uw.fpsimd_state = *state; 1257 if (test_thread_flag(TIF_SVE)) 1258 fpsimd_to_sve(current); 1259 1260 task_fpsimd_load(); 1261 fpsimd_bind_task_to_cpu(); 1262 1263 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1264 1265 put_cpu_fpsimd_context(); 1266 } 1267 1268 /* 1269 * Invalidate live CPU copies of task t's FPSIMD state 1270 * 1271 * This function may be called with preemption enabled. The barrier() 1272 * ensures that the assignment to fpsimd_cpu is visible to any 1273 * preemption/softirq that could race with set_tsk_thread_flag(), so 1274 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared. 1275 * 1276 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any 1277 * subsequent code. 1278 */ 1279 void fpsimd_flush_task_state(struct task_struct *t) 1280 { 1281 t->thread.fpsimd_cpu = NR_CPUS; 1282 /* 1283 * If we don't support fpsimd, bail out after we have 1284 * reset the fpsimd_cpu for this task and clear the 1285 * FPSTATE. 1286 */ 1287 if (!system_supports_fpsimd()) 1288 return; 1289 barrier(); 1290 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE); 1291 1292 barrier(); 1293 } 1294 1295 /* 1296 * Invalidate any task's FPSIMD state that is present on this cpu. 1297 * The FPSIMD context should be acquired with get_cpu_fpsimd_context() 1298 * before calling this function. 1299 */ 1300 static void fpsimd_flush_cpu_state(void) 1301 { 1302 WARN_ON(!system_supports_fpsimd()); 1303 __this_cpu_write(fpsimd_last_state.st, NULL); 1304 set_thread_flag(TIF_FOREIGN_FPSTATE); 1305 } 1306 1307 /* 1308 * Save the FPSIMD state to memory and invalidate cpu view. 1309 * This function must be called with preemption disabled. 1310 */ 1311 void fpsimd_save_and_flush_cpu_state(void) 1312 { 1313 if (!system_supports_fpsimd()) 1314 return; 1315 WARN_ON(preemptible()); 1316 __get_cpu_fpsimd_context(); 1317 fpsimd_save(); 1318 fpsimd_flush_cpu_state(); 1319 __put_cpu_fpsimd_context(); 1320 } 1321 1322 #ifdef CONFIG_KERNEL_MODE_NEON 1323 1324 /* 1325 * Kernel-side NEON support functions 1326 */ 1327 1328 /* 1329 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling 1330 * context 1331 * 1332 * Must not be called unless may_use_simd() returns true. 1333 * Task context in the FPSIMD registers is saved back to memory as necessary. 1334 * 1335 * A matching call to kernel_neon_end() must be made before returning from the 1336 * calling context. 1337 * 1338 * The caller may freely use the FPSIMD registers until kernel_neon_end() is 1339 * called. 1340 */ 1341 void kernel_neon_begin(void) 1342 { 1343 if (WARN_ON(!system_supports_fpsimd())) 1344 return; 1345 1346 BUG_ON(!may_use_simd()); 1347 1348 get_cpu_fpsimd_context(); 1349 1350 /* Save unsaved fpsimd state, if any: */ 1351 fpsimd_save(); 1352 1353 /* Invalidate any task state remaining in the fpsimd regs: */ 1354 fpsimd_flush_cpu_state(); 1355 } 1356 EXPORT_SYMBOL(kernel_neon_begin); 1357 1358 /* 1359 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task 1360 * 1361 * Must be called from a context in which kernel_neon_begin() was previously 1362 * called, with no call to kernel_neon_end() in the meantime. 1363 * 1364 * The caller must not use the FPSIMD registers after this function is called, 1365 * unless kernel_neon_begin() is called again in the meantime. 1366 */ 1367 void kernel_neon_end(void) 1368 { 1369 if (!system_supports_fpsimd()) 1370 return; 1371 1372 put_cpu_fpsimd_context(); 1373 } 1374 EXPORT_SYMBOL(kernel_neon_end); 1375 1376 #ifdef CONFIG_EFI 1377 1378 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state); 1379 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used); 1380 static DEFINE_PER_CPU(bool, efi_sve_state_used); 1381 1382 /* 1383 * EFI runtime services support functions 1384 * 1385 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call. 1386 * This means that for EFI (and only for EFI), we have to assume that FPSIMD 1387 * is always used rather than being an optional accelerator. 1388 * 1389 * These functions provide the necessary support for ensuring FPSIMD 1390 * save/restore in the contexts from which EFI is used. 1391 * 1392 * Do not use them for any other purpose -- if tempted to do so, you are 1393 * either doing something wrong or you need to propose some refactoring. 1394 */ 1395 1396 /* 1397 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call 1398 */ 1399 void __efi_fpsimd_begin(void) 1400 { 1401 if (!system_supports_fpsimd()) 1402 return; 1403 1404 WARN_ON(preemptible()); 1405 1406 if (may_use_simd()) { 1407 kernel_neon_begin(); 1408 } else { 1409 /* 1410 * If !efi_sve_state, SVE can't be in use yet and doesn't need 1411 * preserving: 1412 */ 1413 if (system_supports_sve() && likely(efi_sve_state)) { 1414 char *sve_state = this_cpu_ptr(efi_sve_state); 1415 1416 __this_cpu_write(efi_sve_state_used, true); 1417 1418 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()), 1419 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1420 true); 1421 } else { 1422 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); 1423 } 1424 1425 __this_cpu_write(efi_fpsimd_state_used, true); 1426 } 1427 } 1428 1429 /* 1430 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call 1431 */ 1432 void __efi_fpsimd_end(void) 1433 { 1434 if (!system_supports_fpsimd()) 1435 return; 1436 1437 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) { 1438 kernel_neon_end(); 1439 } else { 1440 if (system_supports_sve() && 1441 likely(__this_cpu_read(efi_sve_state_used))) { 1442 char const *sve_state = this_cpu_ptr(efi_sve_state); 1443 1444 sve_set_vq(sve_vq_from_vl(sve_get_vl()) - 1); 1445 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()), 1446 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1447 true); 1448 1449 __this_cpu_write(efi_sve_state_used, false); 1450 } else { 1451 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); 1452 } 1453 } 1454 } 1455 1456 #endif /* CONFIG_EFI */ 1457 1458 #endif /* CONFIG_KERNEL_MODE_NEON */ 1459 1460 #ifdef CONFIG_CPU_PM 1461 static int fpsimd_cpu_pm_notifier(struct notifier_block *self, 1462 unsigned long cmd, void *v) 1463 { 1464 switch (cmd) { 1465 case CPU_PM_ENTER: 1466 fpsimd_save_and_flush_cpu_state(); 1467 break; 1468 case CPU_PM_EXIT: 1469 break; 1470 case CPU_PM_ENTER_FAILED: 1471 default: 1472 return NOTIFY_DONE; 1473 } 1474 return NOTIFY_OK; 1475 } 1476 1477 static struct notifier_block fpsimd_cpu_pm_notifier_block = { 1478 .notifier_call = fpsimd_cpu_pm_notifier, 1479 }; 1480 1481 static void __init fpsimd_pm_init(void) 1482 { 1483 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); 1484 } 1485 1486 #else 1487 static inline void fpsimd_pm_init(void) { } 1488 #endif /* CONFIG_CPU_PM */ 1489 1490 #ifdef CONFIG_HOTPLUG_CPU 1491 static int fpsimd_cpu_dead(unsigned int cpu) 1492 { 1493 per_cpu(fpsimd_last_state.st, cpu) = NULL; 1494 return 0; 1495 } 1496 1497 static inline void fpsimd_hotplug_init(void) 1498 { 1499 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead", 1500 NULL, fpsimd_cpu_dead); 1501 } 1502 1503 #else 1504 static inline void fpsimd_hotplug_init(void) { } 1505 #endif 1506 1507 /* 1508 * FP/SIMD support code initialisation. 1509 */ 1510 static int __init fpsimd_init(void) 1511 { 1512 if (cpu_have_named_feature(FP)) { 1513 fpsimd_pm_init(); 1514 fpsimd_hotplug_init(); 1515 } else { 1516 pr_notice("Floating-point is not implemented\n"); 1517 } 1518 1519 if (!cpu_have_named_feature(ASIMD)) 1520 pr_notice("Advanced SIMD is not implemented\n"); 1521 1522 return sve_sysctl_init(); 1523 } 1524 core_initcall(fpsimd_init); 1525