1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32/* 33 * Context tracking subsystem. Used to instrument transitions 34 * between user and kernel mode. 35 */ 36 .macro ct_user_exit_irqoff 37#ifdef CONFIG_CONTEXT_TRACKING 38 bl enter_from_user_mode 39#endif 40 .endm 41 42 .macro ct_user_enter 43#ifdef CONFIG_CONTEXT_TRACKING 44 bl context_tracking_user_enter 45#endif 46 .endm 47 48 .macro clear_gp_regs 49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 50 mov x\n, xzr 51 .endr 52 .endm 53 54/* 55 * Bad Abort numbers 56 *----------------- 57 */ 58#define BAD_SYNC 0 59#define BAD_IRQ 1 60#define BAD_FIQ 2 61#define BAD_ERROR 3 62 63 .macro kernel_ventry, el, label, regsize = 64 64 .align 7 65#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 66 .if \el == 0 67alternative_if ARM64_UNMAP_KERNEL_AT_EL0 68 .if \regsize == 64 69 mrs x30, tpidrro_el0 70 msr tpidrro_el0, xzr 71 .else 72 mov x30, xzr 73 .endif 74alternative_else_nop_endif 75 .endif 76#endif 77 78 sub sp, sp, #S_FRAME_SIZE 79#ifdef CONFIG_VMAP_STACK 80 /* 81 * Test whether the SP has overflowed, without corrupting a GPR. 82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 83 * should always be zero. 84 */ 85 add sp, sp, x0 // sp' = sp + x0 86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 87 tbnz x0, #THREAD_SHIFT, 0f 88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 90 b el\()\el\()_\label 91 920: 93 /* 94 * Either we've just detected an overflow, or we've taken an exception 95 * while on the overflow stack. Either way, we won't return to 96 * userspace, and can clobber EL0 registers to free up GPRs. 97 */ 98 99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ 100 msr tpidr_el0, x0 101 102 /* Recover the original x0 value and stash it in tpidrro_el0 */ 103 sub x0, sp, x0 104 msr tpidrro_el0, x0 105 106 /* Switch to the overflow stack */ 107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 108 109 /* 110 * Check whether we were already on the overflow stack. This may happen 111 * after panic() re-enables interrupts. 112 */ 113 mrs x0, tpidr_el0 // sp of interrupted context 114 sub x0, sp, x0 // delta with top of overflow stack 115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 116 b.ne __bad_stack // no? -> bad stack pointer 117 118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 119 sub sp, sp, x0 120 mrs x0, tpidrro_el0 121#endif 122 b el\()\el\()_\label 123 .endm 124 125 .macro tramp_alias, dst, sym 126 mov_q \dst, TRAMP_VALIAS 127 add \dst, \dst, #(\sym - .entry.tramp.text) 128 .endm 129 130 /* 131 * This macro corrupts x0-x3. It is the caller's duty to save/restore 132 * them if required. 133 */ 134 .macro apply_ssbd, state, tmp1, tmp2 135alternative_cb spectre_v4_patch_fw_mitigation_enable 136 b .L__asm_ssbd_skip\@ // Patched to NOP 137alternative_cb_end 138 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 139 cbz \tmp2, .L__asm_ssbd_skip\@ 140 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 141 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 142 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 143 mov w1, #\state 144alternative_cb spectre_v4_patch_fw_mitigation_conduit 145 nop // Patched to SMC/HVC #0 146alternative_cb_end 147.L__asm_ssbd_skip\@: 148 .endm 149 150 /* Check for MTE asynchronous tag check faults */ 151 .macro check_mte_async_tcf, flgs, tmp 152#ifdef CONFIG_ARM64_MTE 153alternative_if_not ARM64_MTE 154 b 1f 155alternative_else_nop_endif 156 mrs_s \tmp, SYS_TFSRE0_EL1 157 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 158 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 159 orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT 160 str \flgs, [tsk, #TSK_TI_FLAGS] 161 msr_s SYS_TFSRE0_EL1, xzr 1621: 163#endif 164 .endm 165 166 /* Clear the MTE asynchronous tag check faults */ 167 .macro clear_mte_async_tcf 168#ifdef CONFIG_ARM64_MTE 169alternative_if ARM64_MTE 170 dsb ish 171 msr_s SYS_TFSRE0_EL1, xzr 172alternative_else_nop_endif 173#endif 174 .endm 175 176 .macro kernel_entry, el, regsize = 64 177 .if \regsize == 32 178 mov w0, w0 // zero upper 32 bits of x0 179 .endif 180 stp x0, x1, [sp, #16 * 0] 181 stp x2, x3, [sp, #16 * 1] 182 stp x4, x5, [sp, #16 * 2] 183 stp x6, x7, [sp, #16 * 3] 184 stp x8, x9, [sp, #16 * 4] 185 stp x10, x11, [sp, #16 * 5] 186 stp x12, x13, [sp, #16 * 6] 187 stp x14, x15, [sp, #16 * 7] 188 stp x16, x17, [sp, #16 * 8] 189 stp x18, x19, [sp, #16 * 9] 190 stp x20, x21, [sp, #16 * 10] 191 stp x22, x23, [sp, #16 * 11] 192 stp x24, x25, [sp, #16 * 12] 193 stp x26, x27, [sp, #16 * 13] 194 stp x28, x29, [sp, #16 * 14] 195 196 .if \el == 0 197 clear_gp_regs 198 mrs x21, sp_el0 199 ldr_this_cpu tsk, __entry_task, x20 200 msr sp_el0, tsk 201 202 /* 203 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 204 * when scheduling. 205 */ 206 ldr x19, [tsk, #TSK_TI_FLAGS] 207 disable_step_tsk x19, x20 208 209 /* Check for asynchronous tag check faults in user space */ 210 check_mte_async_tcf x19, x22 211 apply_ssbd 1, x22, x23 212 213 ptrauth_keys_install_kernel tsk, x20, x22, x23 214 215 scs_load tsk, x20 216 .else 217 add x21, sp, #S_FRAME_SIZE 218 get_current_task tsk 219 /* Save the task's original addr_limit and set USER_DS */ 220 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] 221 str x20, [sp, #S_ORIG_ADDR_LIMIT] 222 mov x20, #USER_DS 223 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 224 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ 225 .endif /* \el == 0 */ 226 mrs x22, elr_el1 227 mrs x23, spsr_el1 228 stp lr, x21, [sp, #S_LR] 229 230 /* 231 * In order to be able to dump the contents of struct pt_regs at the 232 * time the exception was taken (in case we attempt to walk the call 233 * stack later), chain it together with the stack frames. 234 */ 235 .if \el == 0 236 stp xzr, xzr, [sp, #S_STACKFRAME] 237 .else 238 stp x29, x22, [sp, #S_STACKFRAME] 239 .endif 240 add x29, sp, #S_STACKFRAME 241 242#ifdef CONFIG_ARM64_SW_TTBR0_PAN 243alternative_if_not ARM64_HAS_PAN 244 bl __swpan_entry_el\el 245alternative_else_nop_endif 246#endif 247 248 stp x22, x23, [sp, #S_PC] 249 250 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 251 .if \el == 0 252 mov w21, #NO_SYSCALL 253 str w21, [sp, #S_SYSCALLNO] 254 .endif 255 256 /* Save pmr */ 257alternative_if ARM64_HAS_IRQ_PRIO_MASKING 258 mrs_s x20, SYS_ICC_PMR_EL1 259 str x20, [sp, #S_PMR_SAVE] 260alternative_else_nop_endif 261 262 /* Re-enable tag checking (TCO set on exception entry) */ 263#ifdef CONFIG_ARM64_MTE 264alternative_if ARM64_MTE 265 SET_PSTATE_TCO(0) 266alternative_else_nop_endif 267#endif 268 269 /* 270 * Registers that may be useful after this macro is invoked: 271 * 272 * x20 - ICC_PMR_EL1 273 * x21 - aborted SP 274 * x22 - aborted PC 275 * x23 - aborted PSTATE 276 */ 277 .endm 278 279 .macro kernel_exit, el 280 .if \el != 0 281 disable_daif 282 283 /* Restore the task's original addr_limit. */ 284 ldr x20, [sp, #S_ORIG_ADDR_LIMIT] 285 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 286 287 /* No need to restore UAO, it will be restored from SPSR_EL1 */ 288 .endif 289 290 /* Restore pmr */ 291alternative_if ARM64_HAS_IRQ_PRIO_MASKING 292 ldr x20, [sp, #S_PMR_SAVE] 293 msr_s SYS_ICC_PMR_EL1, x20 294 mrs_s x21, SYS_ICC_CTLR_EL1 295 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 296 dsb sy // Ensure priority change is seen by redistributor 297.L__skip_pmr_sync\@: 298alternative_else_nop_endif 299 300 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 301 .if \el == 0 302 ct_user_enter 303 .endif 304 305#ifdef CONFIG_ARM64_SW_TTBR0_PAN 306alternative_if_not ARM64_HAS_PAN 307 bl __swpan_exit_el\el 308alternative_else_nop_endif 309#endif 310 311 .if \el == 0 312 ldr x23, [sp, #S_SP] // load return stack pointer 313 msr sp_el0, x23 314 tst x22, #PSR_MODE32_BIT // native task? 315 b.eq 3f 316 317#ifdef CONFIG_ARM64_ERRATUM_845719 318alternative_if ARM64_WORKAROUND_845719 319#ifdef CONFIG_PID_IN_CONTEXTIDR 320 mrs x29, contextidr_el1 321 msr contextidr_el1, x29 322#else 323 msr contextidr_el1, xzr 324#endif 325alternative_else_nop_endif 326#endif 3273: 328 scs_save tsk, x0 329 330 /* No kernel C function calls after this as user keys are set. */ 331 ptrauth_keys_install_user tsk, x0, x1, x2 332 333 apply_ssbd 0, x0, x1 334 .endif 335 336 msr elr_el1, x21 // set up the return data 337 msr spsr_el1, x22 338 ldp x0, x1, [sp, #16 * 0] 339 ldp x2, x3, [sp, #16 * 1] 340 ldp x4, x5, [sp, #16 * 2] 341 ldp x6, x7, [sp, #16 * 3] 342 ldp x8, x9, [sp, #16 * 4] 343 ldp x10, x11, [sp, #16 * 5] 344 ldp x12, x13, [sp, #16 * 6] 345 ldp x14, x15, [sp, #16 * 7] 346 ldp x16, x17, [sp, #16 * 8] 347 ldp x18, x19, [sp, #16 * 9] 348 ldp x20, x21, [sp, #16 * 10] 349 ldp x22, x23, [sp, #16 * 11] 350 ldp x24, x25, [sp, #16 * 12] 351 ldp x26, x27, [sp, #16 * 13] 352 ldp x28, x29, [sp, #16 * 14] 353 ldr lr, [sp, #S_LR] 354 add sp, sp, #S_FRAME_SIZE // restore sp 355 356 .if \el == 0 357alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 358#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 359 bne 4f 360 msr far_el1, x30 361 tramp_alias x30, tramp_exit_native 362 br x30 3634: 364 tramp_alias x30, tramp_exit_compat 365 br x30 366#endif 367 .else 368 eret 369 .endif 370 sb 371 .endm 372 373#ifdef CONFIG_ARM64_SW_TTBR0_PAN 374 /* 375 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 376 * EL0, there is no need to check the state of TTBR0_EL1 since 377 * accesses are always enabled. 378 * Note that the meaning of this bit differs from the ARMv8.1 PAN 379 * feature as all TTBR0_EL1 accesses are disabled, not just those to 380 * user mappings. 381 */ 382SYM_CODE_START_LOCAL(__swpan_entry_el1) 383 mrs x21, ttbr0_el1 384 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 385 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 386 b.eq 1f // TTBR0 access already disabled 387 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 388SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 389 __uaccess_ttbr0_disable x21 3901: ret 391SYM_CODE_END(__swpan_entry_el1) 392 393 /* 394 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 395 * PAN bit checking. 396 */ 397SYM_CODE_START_LOCAL(__swpan_exit_el1) 398 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 399 __uaccess_ttbr0_enable x0, x1 4001: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 401 ret 402SYM_CODE_END(__swpan_exit_el1) 403 404SYM_CODE_START_LOCAL(__swpan_exit_el0) 405 __uaccess_ttbr0_enable x0, x1 406 /* 407 * Enable errata workarounds only if returning to user. The only 408 * workaround currently required for TTBR0_EL1 changes are for the 409 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 410 * corruption). 411 */ 412 b post_ttbr_update_workaround 413SYM_CODE_END(__swpan_exit_el0) 414#endif 415 416 .macro irq_stack_entry 417 mov x19, sp // preserve the original sp 418#ifdef CONFIG_SHADOW_CALL_STACK 419 mov x24, scs_sp // preserve the original shadow stack 420#endif 421 422 /* 423 * Compare sp with the base of the task stack. 424 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, 425 * and should switch to the irq stack. 426 */ 427 ldr x25, [tsk, TSK_STACK] 428 eor x25, x25, x19 429 and x25, x25, #~(THREAD_SIZE - 1) 430 cbnz x25, 9998f 431 432 ldr_this_cpu x25, irq_stack_ptr, x26 433 mov x26, #IRQ_STACK_SIZE 434 add x26, x25, x26 435 436 /* switch to the irq stack */ 437 mov sp, x26 438 439#ifdef CONFIG_SHADOW_CALL_STACK 440 /* also switch to the irq shadow stack */ 441 adr_this_cpu scs_sp, irq_shadow_call_stack, x26 442#endif 443 4449998: 445 .endm 446 447 /* 448 * The callee-saved regs (x19-x29) should be preserved between 449 * irq_stack_entry and irq_stack_exit, but note that kernel_entry 450 * uses x20-x23 to store data for later use. 451 */ 452 .macro irq_stack_exit 453 mov sp, x19 454#ifdef CONFIG_SHADOW_CALL_STACK 455 mov scs_sp, x24 456#endif 457 .endm 458 459/* GPRs used by entry code */ 460tsk .req x28 // current thread_info 461 462/* 463 * Interrupt handling. 464 */ 465 .macro irq_handler 466 ldr_l x1, handle_arch_irq 467 mov x0, sp 468 irq_stack_entry 469 blr x1 470 irq_stack_exit 471 .endm 472 473#ifdef CONFIG_ARM64_PSEUDO_NMI 474 /* 475 * Set res to 0 if irqs were unmasked in interrupted context. 476 * Otherwise set res to non-0 value. 477 */ 478 .macro test_irqs_unmasked res:req, pmr:req 479alternative_if ARM64_HAS_IRQ_PRIO_MASKING 480 sub \res, \pmr, #GIC_PRIO_IRQON 481alternative_else 482 mov \res, xzr 483alternative_endif 484 .endm 485#endif 486 487 .macro gic_prio_kentry_setup, tmp:req 488#ifdef CONFIG_ARM64_PSEUDO_NMI 489 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 490 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON) 491 msr_s SYS_ICC_PMR_EL1, \tmp 492 alternative_else_nop_endif 493#endif 494 .endm 495 496 .macro gic_prio_irq_setup, pmr:req, tmp:req 497#ifdef CONFIG_ARM64_PSEUDO_NMI 498 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 499 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET 500 msr_s SYS_ICC_PMR_EL1, \tmp 501 alternative_else_nop_endif 502#endif 503 .endm 504 505 .text 506 507/* 508 * Exception vectors. 509 */ 510 .pushsection ".entry.text", "ax" 511 512 .align 11 513SYM_CODE_START(vectors) 514 kernel_ventry 1, sync_invalid // Synchronous EL1t 515 kernel_ventry 1, irq_invalid // IRQ EL1t 516 kernel_ventry 1, fiq_invalid // FIQ EL1t 517 kernel_ventry 1, error_invalid // Error EL1t 518 519 kernel_ventry 1, sync // Synchronous EL1h 520 kernel_ventry 1, irq // IRQ EL1h 521 kernel_ventry 1, fiq_invalid // FIQ EL1h 522 kernel_ventry 1, error // Error EL1h 523 524 kernel_ventry 0, sync // Synchronous 64-bit EL0 525 kernel_ventry 0, irq // IRQ 64-bit EL0 526 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 527 kernel_ventry 0, error // Error 64-bit EL0 528 529#ifdef CONFIG_COMPAT 530 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 531 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 532 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 533 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 534#else 535 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 536 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 537 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 538 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 539#endif 540SYM_CODE_END(vectors) 541 542#ifdef CONFIG_VMAP_STACK 543 /* 544 * We detected an overflow in kernel_ventry, which switched to the 545 * overflow stack. Stash the exception regs, and head to our overflow 546 * handler. 547 */ 548__bad_stack: 549 /* Restore the original x0 value */ 550 mrs x0, tpidrro_el0 551 552 /* 553 * Store the original GPRs to the new stack. The orginal SP (minus 554 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. 555 */ 556 sub sp, sp, #S_FRAME_SIZE 557 kernel_entry 1 558 mrs x0, tpidr_el0 559 add x0, x0, #S_FRAME_SIZE 560 str x0, [sp, #S_SP] 561 562 /* Stash the regs for handle_bad_stack */ 563 mov x0, sp 564 565 /* Time to die */ 566 bl handle_bad_stack 567 ASM_BUG() 568#endif /* CONFIG_VMAP_STACK */ 569 570/* 571 * Invalid mode handlers 572 */ 573 .macro inv_entry, el, reason, regsize = 64 574 kernel_entry \el, \regsize 575 mov x0, sp 576 mov x1, #\reason 577 mrs x2, esr_el1 578 bl bad_mode 579 ASM_BUG() 580 .endm 581 582SYM_CODE_START_LOCAL(el0_sync_invalid) 583 inv_entry 0, BAD_SYNC 584SYM_CODE_END(el0_sync_invalid) 585 586SYM_CODE_START_LOCAL(el0_irq_invalid) 587 inv_entry 0, BAD_IRQ 588SYM_CODE_END(el0_irq_invalid) 589 590SYM_CODE_START_LOCAL(el0_fiq_invalid) 591 inv_entry 0, BAD_FIQ 592SYM_CODE_END(el0_fiq_invalid) 593 594SYM_CODE_START_LOCAL(el0_error_invalid) 595 inv_entry 0, BAD_ERROR 596SYM_CODE_END(el0_error_invalid) 597 598#ifdef CONFIG_COMPAT 599SYM_CODE_START_LOCAL(el0_fiq_invalid_compat) 600 inv_entry 0, BAD_FIQ, 32 601SYM_CODE_END(el0_fiq_invalid_compat) 602#endif 603 604SYM_CODE_START_LOCAL(el1_sync_invalid) 605 inv_entry 1, BAD_SYNC 606SYM_CODE_END(el1_sync_invalid) 607 608SYM_CODE_START_LOCAL(el1_irq_invalid) 609 inv_entry 1, BAD_IRQ 610SYM_CODE_END(el1_irq_invalid) 611 612SYM_CODE_START_LOCAL(el1_fiq_invalid) 613 inv_entry 1, BAD_FIQ 614SYM_CODE_END(el1_fiq_invalid) 615 616SYM_CODE_START_LOCAL(el1_error_invalid) 617 inv_entry 1, BAD_ERROR 618SYM_CODE_END(el1_error_invalid) 619 620/* 621 * EL1 mode handlers. 622 */ 623 .align 6 624SYM_CODE_START_LOCAL_NOALIGN(el1_sync) 625 kernel_entry 1 626 mov x0, sp 627 bl el1_sync_handler 628 kernel_exit 1 629SYM_CODE_END(el1_sync) 630 631 .align 6 632SYM_CODE_START_LOCAL_NOALIGN(el1_irq) 633 kernel_entry 1 634 gic_prio_irq_setup pmr=x20, tmp=x1 635 enable_da_f 636 637#ifdef CONFIG_ARM64_PSEUDO_NMI 638 test_irqs_unmasked res=x0, pmr=x20 639 cbz x0, 1f 640 bl asm_nmi_enter 6411: 642#endif 643 644#ifdef CONFIG_TRACE_IRQFLAGS 645 bl trace_hardirqs_off 646#endif 647 648 irq_handler 649 650#ifdef CONFIG_PREEMPTION 651 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count 652alternative_if ARM64_HAS_IRQ_PRIO_MASKING 653 /* 654 * DA_F were cleared at start of handling. If anything is set in DAIF, 655 * we come back from an NMI, so skip preemption 656 */ 657 mrs x0, daif 658 orr x24, x24, x0 659alternative_else_nop_endif 660 cbnz x24, 1f // preempt count != 0 || NMI return path 661 bl arm64_preempt_schedule_irq // irq en/disable is done inside 6621: 663#endif 664 665#ifdef CONFIG_ARM64_PSEUDO_NMI 666 /* 667 * When using IRQ priority masking, we can get spurious interrupts while 668 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a 669 * section with interrupts disabled. Skip tracing in those cases. 670 */ 671 test_irqs_unmasked res=x0, pmr=x20 672 cbz x0, 1f 673 bl asm_nmi_exit 6741: 675#endif 676 677#ifdef CONFIG_TRACE_IRQFLAGS 678#ifdef CONFIG_ARM64_PSEUDO_NMI 679 test_irqs_unmasked res=x0, pmr=x20 680 cbnz x0, 1f 681#endif 682 bl trace_hardirqs_on 6831: 684#endif 685 686 kernel_exit 1 687SYM_CODE_END(el1_irq) 688 689/* 690 * EL0 mode handlers. 691 */ 692 .align 6 693SYM_CODE_START_LOCAL_NOALIGN(el0_sync) 694 kernel_entry 0 695 mov x0, sp 696 bl el0_sync_handler 697 b ret_to_user 698SYM_CODE_END(el0_sync) 699 700#ifdef CONFIG_COMPAT 701 .align 6 702SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat) 703 kernel_entry 0, 32 704 mov x0, sp 705 bl el0_sync_compat_handler 706 b ret_to_user 707SYM_CODE_END(el0_sync_compat) 708 709 .align 6 710SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) 711 kernel_entry 0, 32 712 b el0_irq_naked 713SYM_CODE_END(el0_irq_compat) 714 715SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) 716 kernel_entry 0, 32 717 b el0_error_naked 718SYM_CODE_END(el0_error_compat) 719#endif 720 721 .align 6 722SYM_CODE_START_LOCAL_NOALIGN(el0_irq) 723 kernel_entry 0 724el0_irq_naked: 725 gic_prio_irq_setup pmr=x20, tmp=x0 726 ct_user_exit_irqoff 727 enable_da_f 728 729#ifdef CONFIG_TRACE_IRQFLAGS 730 bl trace_hardirqs_off 731#endif 732 733 tbz x22, #55, 1f 734 bl do_el0_irq_bp_hardening 7351: 736 irq_handler 737 738#ifdef CONFIG_TRACE_IRQFLAGS 739 bl trace_hardirqs_on 740#endif 741 b ret_to_user 742SYM_CODE_END(el0_irq) 743 744SYM_CODE_START_LOCAL(el1_error) 745 kernel_entry 1 746 mrs x1, esr_el1 747 gic_prio_kentry_setup tmp=x2 748 enable_dbg 749 mov x0, sp 750 bl do_serror 751 kernel_exit 1 752SYM_CODE_END(el1_error) 753 754SYM_CODE_START_LOCAL(el0_error) 755 kernel_entry 0 756el0_error_naked: 757 mrs x25, esr_el1 758 gic_prio_kentry_setup tmp=x2 759 ct_user_exit_irqoff 760 enable_dbg 761 mov x0, sp 762 mov x1, x25 763 bl do_serror 764 enable_da_f 765 b ret_to_user 766SYM_CODE_END(el0_error) 767 768/* 769 * "slow" syscall return path. 770 */ 771SYM_CODE_START_LOCAL(ret_to_user) 772 disable_daif 773 gic_prio_kentry_setup tmp=x3 774 ldr x1, [tsk, #TSK_TI_FLAGS] 775 and x2, x1, #_TIF_WORK_MASK 776 cbnz x2, work_pending 777finish_ret_to_user: 778 /* Ignore asynchronous tag check faults in the uaccess routines */ 779 clear_mte_async_tcf 780 enable_step_tsk x1, x2 781#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 782 bl stackleak_erase 783#endif 784 kernel_exit 0 785 786/* 787 * Ok, we need to do extra processing, enter the slow path. 788 */ 789work_pending: 790 mov x0, sp // 'regs' 791 bl do_notify_resume 792#ifdef CONFIG_TRACE_IRQFLAGS 793 bl trace_hardirqs_on // enabled while in userspace 794#endif 795 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step 796 b finish_ret_to_user 797SYM_CODE_END(ret_to_user) 798 799 .popsection // .entry.text 800 801#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 802/* 803 * Exception vectors trampoline. 804 */ 805 .pushsection ".entry.tramp.text", "ax" 806 807 .macro tramp_map_kernel, tmp 808 mrs \tmp, ttbr1_el1 809 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 810 bic \tmp, \tmp, #USER_ASID_FLAG 811 msr ttbr1_el1, \tmp 812#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 813alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 814 /* ASID already in \tmp[63:48] */ 815 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 816 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 817 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 818 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 819 isb 820 tlbi vae1, \tmp 821 dsb nsh 822alternative_else_nop_endif 823#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 824 .endm 825 826 .macro tramp_unmap_kernel, tmp 827 mrs \tmp, ttbr1_el1 828 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 829 orr \tmp, \tmp, #USER_ASID_FLAG 830 msr ttbr1_el1, \tmp 831 /* 832 * We avoid running the post_ttbr_update_workaround here because 833 * it's only needed by Cavium ThunderX, which requires KPTI to be 834 * disabled. 835 */ 836 .endm 837 838 .macro tramp_ventry, regsize = 64 839 .align 7 8401: 841 .if \regsize == 64 842 msr tpidrro_el0, x30 // Restored in kernel_ventry 843 .endif 844 /* 845 * Defend against branch aliasing attacks by pushing a dummy 846 * entry onto the return stack and using a RET instruction to 847 * enter the full-fat kernel vectors. 848 */ 849 bl 2f 850 b . 8512: 852 tramp_map_kernel x30 853#ifdef CONFIG_RANDOMIZE_BASE 854 adr x30, tramp_vectors + PAGE_SIZE 855alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 856 ldr x30, [x30] 857#else 858 ldr x30, =vectors 859#endif 860alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 861 prfm plil1strm, [x30, #(1b - tramp_vectors)] 862alternative_else_nop_endif 863 msr vbar_el1, x30 864 add x30, x30, #(1b - tramp_vectors) 865 isb 866 ret 867 .endm 868 869 .macro tramp_exit, regsize = 64 870 adr x30, tramp_vectors 871 msr vbar_el1, x30 872 tramp_unmap_kernel x30 873 .if \regsize == 64 874 mrs x30, far_el1 875 .endif 876 eret 877 sb 878 .endm 879 880 .align 11 881SYM_CODE_START_NOALIGN(tramp_vectors) 882 .space 0x400 883 884 tramp_ventry 885 tramp_ventry 886 tramp_ventry 887 tramp_ventry 888 889 tramp_ventry 32 890 tramp_ventry 32 891 tramp_ventry 32 892 tramp_ventry 32 893SYM_CODE_END(tramp_vectors) 894 895SYM_CODE_START(tramp_exit_native) 896 tramp_exit 897SYM_CODE_END(tramp_exit_native) 898 899SYM_CODE_START(tramp_exit_compat) 900 tramp_exit 32 901SYM_CODE_END(tramp_exit_compat) 902 903 .ltorg 904 .popsection // .entry.tramp.text 905#ifdef CONFIG_RANDOMIZE_BASE 906 .pushsection ".rodata", "a" 907 .align PAGE_SHIFT 908SYM_DATA_START(__entry_tramp_data_start) 909 .quad vectors 910SYM_DATA_END(__entry_tramp_data_start) 911 .popsection // .rodata 912#endif /* CONFIG_RANDOMIZE_BASE */ 913#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 914 915/* 916 * Register switch for AArch64. The callee-saved registers need to be saved 917 * and restored. On entry: 918 * x0 = previous task_struct (must be preserved across the switch) 919 * x1 = next task_struct 920 * Previous and next are guaranteed not to be the same. 921 * 922 */ 923SYM_FUNC_START(cpu_switch_to) 924 mov x10, #THREAD_CPU_CONTEXT 925 add x8, x0, x10 926 mov x9, sp 927 stp x19, x20, [x8], #16 // store callee-saved registers 928 stp x21, x22, [x8], #16 929 stp x23, x24, [x8], #16 930 stp x25, x26, [x8], #16 931 stp x27, x28, [x8], #16 932 stp x29, x9, [x8], #16 933 str lr, [x8] 934 add x8, x1, x10 935 ldp x19, x20, [x8], #16 // restore callee-saved registers 936 ldp x21, x22, [x8], #16 937 ldp x23, x24, [x8], #16 938 ldp x25, x26, [x8], #16 939 ldp x27, x28, [x8], #16 940 ldp x29, x9, [x8], #16 941 ldr lr, [x8] 942 mov sp, x9 943 msr sp_el0, x1 944 ptrauth_keys_install_kernel x1, x8, x9, x10 945 scs_save x0, x8 946 scs_load x1, x8 947 ret 948SYM_FUNC_END(cpu_switch_to) 949NOKPROBE(cpu_switch_to) 950 951/* 952 * This is how we return from a fork. 953 */ 954SYM_CODE_START(ret_from_fork) 955 bl schedule_tail 956 cbz x19, 1f // not a kernel thread 957 mov x0, x20 958 blr x19 9591: get_current_task tsk 960 b ret_to_user 961SYM_CODE_END(ret_from_fork) 962NOKPROBE(ret_from_fork) 963 964#ifdef CONFIG_ARM_SDE_INTERFACE 965 966#include <asm/sdei.h> 967#include <uapi/linux/arm_sdei.h> 968 969.macro sdei_handler_exit exit_mode 970 /* On success, this call never returns... */ 971 cmp \exit_mode, #SDEI_EXIT_SMC 972 b.ne 99f 973 smc #0 974 b . 97599: hvc #0 976 b . 977.endm 978 979#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 980/* 981 * The regular SDEI entry point may have been unmapped along with the rest of 982 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 983 * argument accessible. 984 * 985 * This clobbers x4, __sdei_handler() will restore this from firmware's 986 * copy. 987 */ 988.ltorg 989.pushsection ".entry.tramp.text", "ax" 990SYM_CODE_START(__sdei_asm_entry_trampoline) 991 mrs x4, ttbr1_el1 992 tbz x4, #USER_ASID_BIT, 1f 993 994 tramp_map_kernel tmp=x4 995 isb 996 mov x4, xzr 997 998 /* 999 * Use reg->interrupted_regs.addr_limit to remember whether to unmap 1000 * the kernel on exit. 1001 */ 10021: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 1003 1004#ifdef CONFIG_RANDOMIZE_BASE 1005 adr x4, tramp_vectors + PAGE_SIZE 1006 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler 1007 ldr x4, [x4] 1008#else 1009 ldr x4, =__sdei_asm_handler 1010#endif 1011 br x4 1012SYM_CODE_END(__sdei_asm_entry_trampoline) 1013NOKPROBE(__sdei_asm_entry_trampoline) 1014 1015/* 1016 * Make the exit call and restore the original ttbr1_el1 1017 * 1018 * x0 & x1: setup for the exit API call 1019 * x2: exit_mode 1020 * x4: struct sdei_registered_event argument from registration time. 1021 */ 1022SYM_CODE_START(__sdei_asm_exit_trampoline) 1023 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 1024 cbnz x4, 1f 1025 1026 tramp_unmap_kernel tmp=x4 1027 10281: sdei_handler_exit exit_mode=x2 1029SYM_CODE_END(__sdei_asm_exit_trampoline) 1030NOKPROBE(__sdei_asm_exit_trampoline) 1031 .ltorg 1032.popsection // .entry.tramp.text 1033#ifdef CONFIG_RANDOMIZE_BASE 1034.pushsection ".rodata", "a" 1035SYM_DATA_START(__sdei_asm_trampoline_next_handler) 1036 .quad __sdei_asm_handler 1037SYM_DATA_END(__sdei_asm_trampoline_next_handler) 1038.popsection // .rodata 1039#endif /* CONFIG_RANDOMIZE_BASE */ 1040#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1041 1042/* 1043 * Software Delegated Exception entry point. 1044 * 1045 * x0: Event number 1046 * x1: struct sdei_registered_event argument from registration time. 1047 * x2: interrupted PC 1048 * x3: interrupted PSTATE 1049 * x4: maybe clobbered by the trampoline 1050 * 1051 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 1052 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 1053 * want them. 1054 */ 1055SYM_CODE_START(__sdei_asm_handler) 1056 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 1057 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 1058 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 1059 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 1060 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 1061 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 1062 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 1063 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 1064 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 1065 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 1066 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 1067 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 1068 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1069 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1070 mov x4, sp 1071 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1072 1073 mov x19, x1 1074 1075#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1076 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1077#endif 1078 1079#ifdef CONFIG_VMAP_STACK 1080 /* 1081 * entry.S may have been using sp as a scratch register, find whether 1082 * this is a normal or critical event and switch to the appropriate 1083 * stack for this CPU. 1084 */ 1085 cbnz w4, 1f 1086 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1087 b 2f 10881: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10892: mov x6, #SDEI_STACK_SIZE 1090 add x5, x5, x6 1091 mov sp, x5 1092#endif 1093 1094#ifdef CONFIG_SHADOW_CALL_STACK 1095 /* Use a separate shadow call stack for normal and critical events */ 1096 cbnz w4, 3f 1097 adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6 1098 b 4f 10993: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6 11004: 1101#endif 1102 1103 /* 1104 * We may have interrupted userspace, or a guest, or exit-from or 1105 * return-to either of these. We can't trust sp_el0, restore it. 1106 */ 1107 mrs x28, sp_el0 1108 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1109 msr sp_el0, x0 1110 1111 /* If we interrupted the kernel point to the previous stack/frame. */ 1112 and x0, x3, #0xc 1113 mrs x1, CurrentEL 1114 cmp x0, x1 1115 csel x29, x29, xzr, eq // fp, or zero 1116 csel x4, x2, xzr, eq // elr, or zero 1117 1118 stp x29, x4, [sp, #-16]! 1119 mov x29, sp 1120 1121 add x0, x19, #SDEI_EVENT_INTREGS 1122 mov x1, x19 1123 bl __sdei_handler 1124 1125 msr sp_el0, x28 1126 /* restore regs >x17 that we clobbered */ 1127 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1128 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1129 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1130 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1131 mov sp, x1 1132 1133 mov x1, x0 // address to complete_and_resume 1134 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1135 cmp x0, #1 1136 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1137 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1138 csel x0, x2, x3, ls 1139 1140 ldr_l x2, sdei_exit_mode 1141 1142alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1143 sdei_handler_exit exit_mode=x2 1144alternative_else_nop_endif 1145 1146#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1147 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1148 br x5 1149#endif 1150SYM_CODE_END(__sdei_asm_handler) 1151NOKPROBE(__sdei_asm_handler) 1152#endif /* CONFIG_ARM_SDE_INTERFACE */ 1153