1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32/* 33 * Context tracking and irqflag tracing need to instrument transitions between 34 * user and kernel mode. 35 */ 36 .macro user_exit_irqoff 37#if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS) 38 bl enter_from_user_mode 39#endif 40 .endm 41 42 .macro user_enter_irqoff 43#if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS) 44 bl exit_to_user_mode 45#endif 46 .endm 47 48 .macro clear_gp_regs 49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 50 mov x\n, xzr 51 .endr 52 .endm 53 54/* 55 * Bad Abort numbers 56 *----------------- 57 */ 58#define BAD_SYNC 0 59#define BAD_IRQ 1 60#define BAD_FIQ 2 61#define BAD_ERROR 3 62 63 .macro kernel_ventry, el, label, regsize = 64 64 .align 7 65#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 66 .if \el == 0 67alternative_if ARM64_UNMAP_KERNEL_AT_EL0 68 .if \regsize == 64 69 mrs x30, tpidrro_el0 70 msr tpidrro_el0, xzr 71 .else 72 mov x30, xzr 73 .endif 74alternative_else_nop_endif 75 .endif 76#endif 77 78 sub sp, sp, #PT_REGS_SIZE 79#ifdef CONFIG_VMAP_STACK 80 /* 81 * Test whether the SP has overflowed, without corrupting a GPR. 82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 83 * should always be zero. 84 */ 85 add sp, sp, x0 // sp' = sp + x0 86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 87 tbnz x0, #THREAD_SHIFT, 0f 88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 90 b el\()\el\()_\label 91 920: 93 /* 94 * Either we've just detected an overflow, or we've taken an exception 95 * while on the overflow stack. Either way, we won't return to 96 * userspace, and can clobber EL0 registers to free up GPRs. 97 */ 98 99 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ 100 msr tpidr_el0, x0 101 102 /* Recover the original x0 value and stash it in tpidrro_el0 */ 103 sub x0, sp, x0 104 msr tpidrro_el0, x0 105 106 /* Switch to the overflow stack */ 107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 108 109 /* 110 * Check whether we were already on the overflow stack. This may happen 111 * after panic() re-enables interrupts. 112 */ 113 mrs x0, tpidr_el0 // sp of interrupted context 114 sub x0, sp, x0 // delta with top of overflow stack 115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 116 b.ne __bad_stack // no? -> bad stack pointer 117 118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 119 sub sp, sp, x0 120 mrs x0, tpidrro_el0 121#endif 122 b el\()\el\()_\label 123 .endm 124 125 .macro tramp_alias, dst, sym 126 mov_q \dst, TRAMP_VALIAS 127 add \dst, \dst, #(\sym - .entry.tramp.text) 128 .endm 129 130 /* 131 * This macro corrupts x0-x3. It is the caller's duty to save/restore 132 * them if required. 133 */ 134 .macro apply_ssbd, state, tmp1, tmp2 135alternative_cb spectre_v4_patch_fw_mitigation_enable 136 b .L__asm_ssbd_skip\@ // Patched to NOP 137alternative_cb_end 138 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 139 cbz \tmp2, .L__asm_ssbd_skip\@ 140 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 141 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 142 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 143 mov w1, #\state 144alternative_cb spectre_v4_patch_fw_mitigation_conduit 145 nop // Patched to SMC/HVC #0 146alternative_cb_end 147.L__asm_ssbd_skip\@: 148 .endm 149 150 /* Check for MTE asynchronous tag check faults */ 151 .macro check_mte_async_tcf, tmp, ti_flags 152#ifdef CONFIG_ARM64_MTE 153 .arch_extension lse 154alternative_if_not ARM64_MTE 155 b 1f 156alternative_else_nop_endif 157 mrs_s \tmp, SYS_TFSRE0_EL1 158 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 159 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 160 mov \tmp, #_TIF_MTE_ASYNC_FAULT 161 add \ti_flags, tsk, #TSK_TI_FLAGS 162 stset \tmp, [\ti_flags] 163 msr_s SYS_TFSRE0_EL1, xzr 1641: 165#endif 166 .endm 167 168 /* Clear the MTE asynchronous tag check faults */ 169 .macro clear_mte_async_tcf 170#ifdef CONFIG_ARM64_MTE 171alternative_if ARM64_MTE 172 dsb ish 173 msr_s SYS_TFSRE0_EL1, xzr 174alternative_else_nop_endif 175#endif 176 .endm 177 178 .macro mte_set_gcr, tmp, tmp2 179#ifdef CONFIG_ARM64_MTE 180 /* 181 * Calculate and set the exclude mask preserving 182 * the RRND (bit[16]) setting. 183 */ 184 mrs_s \tmp2, SYS_GCR_EL1 185 bfi \tmp2, \tmp, #0, #16 186 msr_s SYS_GCR_EL1, \tmp2 187#endif 188 .endm 189 190 .macro mte_set_kernel_gcr, tmp, tmp2 191#ifdef CONFIG_KASAN_HW_TAGS 192alternative_if_not ARM64_MTE 193 b 1f 194alternative_else_nop_endif 195 ldr_l \tmp, gcr_kernel_excl 196 197 mte_set_gcr \tmp, \tmp2 198 isb 1991: 200#endif 201 .endm 202 203 .macro mte_set_user_gcr, tsk, tmp, tmp2 204#ifdef CONFIG_ARM64_MTE 205alternative_if_not ARM64_MTE 206 b 1f 207alternative_else_nop_endif 208 ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER] 209 210 mte_set_gcr \tmp, \tmp2 2111: 212#endif 213 .endm 214 215 .macro kernel_entry, el, regsize = 64 216 .if \regsize == 32 217 mov w0, w0 // zero upper 32 bits of x0 218 .endif 219 stp x0, x1, [sp, #16 * 0] 220 stp x2, x3, [sp, #16 * 1] 221 stp x4, x5, [sp, #16 * 2] 222 stp x6, x7, [sp, #16 * 3] 223 stp x8, x9, [sp, #16 * 4] 224 stp x10, x11, [sp, #16 * 5] 225 stp x12, x13, [sp, #16 * 6] 226 stp x14, x15, [sp, #16 * 7] 227 stp x16, x17, [sp, #16 * 8] 228 stp x18, x19, [sp, #16 * 9] 229 stp x20, x21, [sp, #16 * 10] 230 stp x22, x23, [sp, #16 * 11] 231 stp x24, x25, [sp, #16 * 12] 232 stp x26, x27, [sp, #16 * 13] 233 stp x28, x29, [sp, #16 * 14] 234 235 .if \el == 0 236 clear_gp_regs 237 mrs x21, sp_el0 238 ldr_this_cpu tsk, __entry_task, x20 239 msr sp_el0, tsk 240 241 /* 242 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 243 * when scheduling. 244 */ 245 ldr x19, [tsk, #TSK_TI_FLAGS] 246 disable_step_tsk x19, x20 247 248 /* Check for asynchronous tag check faults in user space */ 249 check_mte_async_tcf x22, x23 250 apply_ssbd 1, x22, x23 251 252#ifdef CONFIG_ARM64_PTR_AUTH 253alternative_if ARM64_HAS_ADDRESS_AUTH 254 /* 255 * Enable IA for in-kernel PAC if the task had it disabled. Although 256 * this could be implemented with an unconditional MRS which would avoid 257 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. 258 * 259 * Install the kernel IA key only if IA was enabled in the task. If IA 260 * was disabled on kernel exit then we would have left the kernel IA 261 * installed so there is no need to install it again. 262 */ 263 ldr x0, [tsk, THREAD_SCTLR_USER] 264 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 265 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 266 b 2f 2671: 268 mrs x0, sctlr_el1 269 orr x0, x0, SCTLR_ELx_ENIA 270 msr sctlr_el1, x0 2712: 272 isb 273alternative_else_nop_endif 274#endif 275 276 mte_set_kernel_gcr x22, x23 277 278 scs_load tsk, x20 279 .else 280 add x21, sp, #PT_REGS_SIZE 281 get_current_task tsk 282 .endif /* \el == 0 */ 283 mrs x22, elr_el1 284 mrs x23, spsr_el1 285 stp lr, x21, [sp, #S_LR] 286 287 /* 288 * For exceptions from EL0, create a terminal frame record. 289 * For exceptions from EL1, create a synthetic frame record so the 290 * interrupted code shows up in the backtrace. 291 */ 292 .if \el == 0 293 stp xzr, xzr, [sp, #S_STACKFRAME] 294 .else 295 stp x29, x22, [sp, #S_STACKFRAME] 296 .endif 297 add x29, sp, #S_STACKFRAME 298 299#ifdef CONFIG_ARM64_SW_TTBR0_PAN 300alternative_if_not ARM64_HAS_PAN 301 bl __swpan_entry_el\el 302alternative_else_nop_endif 303#endif 304 305 stp x22, x23, [sp, #S_PC] 306 307 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 308 .if \el == 0 309 mov w21, #NO_SYSCALL 310 str w21, [sp, #S_SYSCALLNO] 311 .endif 312 313 /* Save pmr */ 314alternative_if ARM64_HAS_IRQ_PRIO_MASKING 315 mrs_s x20, SYS_ICC_PMR_EL1 316 str x20, [sp, #S_PMR_SAVE] 317 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET 318 msr_s SYS_ICC_PMR_EL1, x20 319alternative_else_nop_endif 320 321 /* Re-enable tag checking (TCO set on exception entry) */ 322#ifdef CONFIG_ARM64_MTE 323alternative_if ARM64_MTE 324 SET_PSTATE_TCO(0) 325alternative_else_nop_endif 326#endif 327 328 /* 329 * Registers that may be useful after this macro is invoked: 330 * 331 * x20 - ICC_PMR_EL1 332 * x21 - aborted SP 333 * x22 - aborted PC 334 * x23 - aborted PSTATE 335 */ 336 .endm 337 338 .macro kernel_exit, el 339 .if \el != 0 340 disable_daif 341 .endif 342 343 /* Restore pmr */ 344alternative_if ARM64_HAS_IRQ_PRIO_MASKING 345 ldr x20, [sp, #S_PMR_SAVE] 346 msr_s SYS_ICC_PMR_EL1, x20 347 mrs_s x21, SYS_ICC_CTLR_EL1 348 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 349 dsb sy // Ensure priority change is seen by redistributor 350.L__skip_pmr_sync\@: 351alternative_else_nop_endif 352 353 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 354 355#ifdef CONFIG_ARM64_SW_TTBR0_PAN 356alternative_if_not ARM64_HAS_PAN 357 bl __swpan_exit_el\el 358alternative_else_nop_endif 359#endif 360 361 .if \el == 0 362 ldr x23, [sp, #S_SP] // load return stack pointer 363 msr sp_el0, x23 364 tst x22, #PSR_MODE32_BIT // native task? 365 b.eq 3f 366 367#ifdef CONFIG_ARM64_ERRATUM_845719 368alternative_if ARM64_WORKAROUND_845719 369#ifdef CONFIG_PID_IN_CONTEXTIDR 370 mrs x29, contextidr_el1 371 msr contextidr_el1, x29 372#else 373 msr contextidr_el1, xzr 374#endif 375alternative_else_nop_endif 376#endif 3773: 378 scs_save tsk, x0 379 380#ifdef CONFIG_ARM64_PTR_AUTH 381alternative_if ARM64_HAS_ADDRESS_AUTH 382 /* 383 * IA was enabled for in-kernel PAC. Disable it now if needed, or 384 * alternatively install the user's IA. All other per-task keys and 385 * SCTLR bits were updated on task switch. 386 * 387 * No kernel C function calls after this. 388 */ 389 ldr x0, [tsk, THREAD_SCTLR_USER] 390 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 391 __ptrauth_keys_install_user tsk, x0, x1, x2 392 b 2f 3931: 394 mrs x0, sctlr_el1 395 bic x0, x0, SCTLR_ELx_ENIA 396 msr sctlr_el1, x0 3972: 398alternative_else_nop_endif 399#endif 400 401 mte_set_user_gcr tsk, x0, x1 402 403 apply_ssbd 0, x0, x1 404 .endif 405 406 msr elr_el1, x21 // set up the return data 407 msr spsr_el1, x22 408 ldp x0, x1, [sp, #16 * 0] 409 ldp x2, x3, [sp, #16 * 1] 410 ldp x4, x5, [sp, #16 * 2] 411 ldp x6, x7, [sp, #16 * 3] 412 ldp x8, x9, [sp, #16 * 4] 413 ldp x10, x11, [sp, #16 * 5] 414 ldp x12, x13, [sp, #16 * 6] 415 ldp x14, x15, [sp, #16 * 7] 416 ldp x16, x17, [sp, #16 * 8] 417 ldp x18, x19, [sp, #16 * 9] 418 ldp x20, x21, [sp, #16 * 10] 419 ldp x22, x23, [sp, #16 * 11] 420 ldp x24, x25, [sp, #16 * 12] 421 ldp x26, x27, [sp, #16 * 13] 422 ldp x28, x29, [sp, #16 * 14] 423 ldr lr, [sp, #S_LR] 424 add sp, sp, #PT_REGS_SIZE // restore sp 425 426 .if \el == 0 427alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 428#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 429 bne 4f 430 msr far_el1, x30 431 tramp_alias x30, tramp_exit_native 432 br x30 4334: 434 tramp_alias x30, tramp_exit_compat 435 br x30 436#endif 437 .else 438 /* Ensure any device/NC reads complete */ 439 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 440 441 eret 442 .endif 443 sb 444 .endm 445 446#ifdef CONFIG_ARM64_SW_TTBR0_PAN 447 /* 448 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 449 * EL0, there is no need to check the state of TTBR0_EL1 since 450 * accesses are always enabled. 451 * Note that the meaning of this bit differs from the ARMv8.1 PAN 452 * feature as all TTBR0_EL1 accesses are disabled, not just those to 453 * user mappings. 454 */ 455SYM_CODE_START_LOCAL(__swpan_entry_el1) 456 mrs x21, ttbr0_el1 457 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 458 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 459 b.eq 1f // TTBR0 access already disabled 460 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 461SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 462 __uaccess_ttbr0_disable x21 4631: ret 464SYM_CODE_END(__swpan_entry_el1) 465 466 /* 467 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 468 * PAN bit checking. 469 */ 470SYM_CODE_START_LOCAL(__swpan_exit_el1) 471 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 472 __uaccess_ttbr0_enable x0, x1 4731: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 474 ret 475SYM_CODE_END(__swpan_exit_el1) 476 477SYM_CODE_START_LOCAL(__swpan_exit_el0) 478 __uaccess_ttbr0_enable x0, x1 479 /* 480 * Enable errata workarounds only if returning to user. The only 481 * workaround currently required for TTBR0_EL1 changes are for the 482 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 483 * corruption). 484 */ 485 b post_ttbr_update_workaround 486SYM_CODE_END(__swpan_exit_el0) 487#endif 488 489 .macro irq_stack_entry 490 mov x19, sp // preserve the original sp 491#ifdef CONFIG_SHADOW_CALL_STACK 492 mov x24, scs_sp // preserve the original shadow stack 493#endif 494 495 /* 496 * Compare sp with the base of the task stack. 497 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, 498 * and should switch to the irq stack. 499 */ 500 ldr x25, [tsk, TSK_STACK] 501 eor x25, x25, x19 502 and x25, x25, #~(THREAD_SIZE - 1) 503 cbnz x25, 9998f 504 505 ldr_this_cpu x25, irq_stack_ptr, x26 506 mov x26, #IRQ_STACK_SIZE 507 add x26, x25, x26 508 509 /* switch to the irq stack */ 510 mov sp, x26 511 512#ifdef CONFIG_SHADOW_CALL_STACK 513 /* also switch to the irq shadow stack */ 514 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x26 515#endif 516 5179998: 518 .endm 519 520 /* 521 * The callee-saved regs (x19-x29) should be preserved between 522 * irq_stack_entry and irq_stack_exit, but note that kernel_entry 523 * uses x20-x23 to store data for later use. 524 */ 525 .macro irq_stack_exit 526 mov sp, x19 527#ifdef CONFIG_SHADOW_CALL_STACK 528 mov scs_sp, x24 529#endif 530 .endm 531 532/* GPRs used by entry code */ 533tsk .req x28 // current thread_info 534 535/* 536 * Interrupt handling. 537 */ 538 .macro irq_handler, handler:req 539 ldr_l x1, \handler 540 mov x0, sp 541 irq_stack_entry 542 blr x1 543 irq_stack_exit 544 .endm 545 546 .macro gic_prio_kentry_setup, tmp:req 547#ifdef CONFIG_ARM64_PSEUDO_NMI 548 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 549 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON) 550 msr_s SYS_ICC_PMR_EL1, \tmp 551 alternative_else_nop_endif 552#endif 553 .endm 554 555 .macro el1_interrupt_handler, handler:req 556 enable_da 557 558 mov x0, sp 559 bl enter_el1_irq_or_nmi 560 561 irq_handler \handler 562 563#ifdef CONFIG_PREEMPTION 564 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count 565alternative_if ARM64_HAS_IRQ_PRIO_MASKING 566 /* 567 * DA were cleared at start of handling, and IF are cleared by 568 * the GIC irqchip driver using gic_arch_enable_irqs() for 569 * normal IRQs. If anything is set, it means we come back from 570 * an NMI instead of a normal IRQ, so skip preemption 571 */ 572 mrs x0, daif 573 orr x24, x24, x0 574alternative_else_nop_endif 575 cbnz x24, 1f // preempt count != 0 || NMI return path 576 bl arm64_preempt_schedule_irq // irq en/disable is done inside 5771: 578#endif 579 580 mov x0, sp 581 bl exit_el1_irq_or_nmi 582 .endm 583 584 .macro el0_interrupt_handler, handler:req 585 user_exit_irqoff 586 enable_da 587 588 tbz x22, #55, 1f 589 bl do_el0_irq_bp_hardening 5901: 591 irq_handler \handler 592 .endm 593 594 .text 595 596/* 597 * Exception vectors. 598 */ 599 .pushsection ".entry.text", "ax" 600 601 .align 11 602SYM_CODE_START(vectors) 603 kernel_ventry 1, sync_invalid // Synchronous EL1t 604 kernel_ventry 1, irq_invalid // IRQ EL1t 605 kernel_ventry 1, fiq_invalid // FIQ EL1t 606 kernel_ventry 1, error_invalid // Error EL1t 607 608 kernel_ventry 1, sync // Synchronous EL1h 609 kernel_ventry 1, irq // IRQ EL1h 610 kernel_ventry 1, fiq // FIQ EL1h 611 kernel_ventry 1, error // Error EL1h 612 613 kernel_ventry 0, sync // Synchronous 64-bit EL0 614 kernel_ventry 0, irq // IRQ 64-bit EL0 615 kernel_ventry 0, fiq // FIQ 64-bit EL0 616 kernel_ventry 0, error // Error 64-bit EL0 617 618#ifdef CONFIG_COMPAT 619 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 620 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 621 kernel_ventry 0, fiq_compat, 32 // FIQ 32-bit EL0 622 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 623#else 624 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 625 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 626 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 627 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 628#endif 629SYM_CODE_END(vectors) 630 631#ifdef CONFIG_VMAP_STACK 632 /* 633 * We detected an overflow in kernel_ventry, which switched to the 634 * overflow stack. Stash the exception regs, and head to our overflow 635 * handler. 636 */ 637__bad_stack: 638 /* Restore the original x0 value */ 639 mrs x0, tpidrro_el0 640 641 /* 642 * Store the original GPRs to the new stack. The orginal SP (minus 643 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. 644 */ 645 sub sp, sp, #PT_REGS_SIZE 646 kernel_entry 1 647 mrs x0, tpidr_el0 648 add x0, x0, #PT_REGS_SIZE 649 str x0, [sp, #S_SP] 650 651 /* Stash the regs for handle_bad_stack */ 652 mov x0, sp 653 654 /* Time to die */ 655 bl handle_bad_stack 656 ASM_BUG() 657#endif /* CONFIG_VMAP_STACK */ 658 659/* 660 * Invalid mode handlers 661 */ 662 .macro inv_entry, el, reason, regsize = 64 663 kernel_entry \el, \regsize 664 mov x0, sp 665 mov x1, #\reason 666 mrs x2, esr_el1 667 bl bad_mode 668 ASM_BUG() 669 .endm 670 671SYM_CODE_START_LOCAL(el0_sync_invalid) 672 inv_entry 0, BAD_SYNC 673SYM_CODE_END(el0_sync_invalid) 674 675SYM_CODE_START_LOCAL(el0_irq_invalid) 676 inv_entry 0, BAD_IRQ 677SYM_CODE_END(el0_irq_invalid) 678 679SYM_CODE_START_LOCAL(el0_fiq_invalid) 680 inv_entry 0, BAD_FIQ 681SYM_CODE_END(el0_fiq_invalid) 682 683SYM_CODE_START_LOCAL(el0_error_invalid) 684 inv_entry 0, BAD_ERROR 685SYM_CODE_END(el0_error_invalid) 686 687SYM_CODE_START_LOCAL(el1_sync_invalid) 688 inv_entry 1, BAD_SYNC 689SYM_CODE_END(el1_sync_invalid) 690 691SYM_CODE_START_LOCAL(el1_irq_invalid) 692 inv_entry 1, BAD_IRQ 693SYM_CODE_END(el1_irq_invalid) 694 695SYM_CODE_START_LOCAL(el1_fiq_invalid) 696 inv_entry 1, BAD_FIQ 697SYM_CODE_END(el1_fiq_invalid) 698 699SYM_CODE_START_LOCAL(el1_error_invalid) 700 inv_entry 1, BAD_ERROR 701SYM_CODE_END(el1_error_invalid) 702 703/* 704 * EL1 mode handlers. 705 */ 706 .align 6 707SYM_CODE_START_LOCAL_NOALIGN(el1_sync) 708 kernel_entry 1 709 mov x0, sp 710 bl el1_sync_handler 711 kernel_exit 1 712SYM_CODE_END(el1_sync) 713 714 .align 6 715SYM_CODE_START_LOCAL_NOALIGN(el1_irq) 716 kernel_entry 1 717 el1_interrupt_handler handle_arch_irq 718 kernel_exit 1 719SYM_CODE_END(el1_irq) 720 721SYM_CODE_START_LOCAL_NOALIGN(el1_fiq) 722 kernel_entry 1 723 el1_interrupt_handler handle_arch_fiq 724 kernel_exit 1 725SYM_CODE_END(el1_fiq) 726 727/* 728 * EL0 mode handlers. 729 */ 730 .align 6 731SYM_CODE_START_LOCAL_NOALIGN(el0_sync) 732 kernel_entry 0 733 mov x0, sp 734 bl el0_sync_handler 735 b ret_to_user 736SYM_CODE_END(el0_sync) 737 738#ifdef CONFIG_COMPAT 739 .align 6 740SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat) 741 kernel_entry 0, 32 742 mov x0, sp 743 bl el0_sync_compat_handler 744 b ret_to_user 745SYM_CODE_END(el0_sync_compat) 746 747 .align 6 748SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) 749 kernel_entry 0, 32 750 b el0_irq_naked 751SYM_CODE_END(el0_irq_compat) 752 753SYM_CODE_START_LOCAL_NOALIGN(el0_fiq_compat) 754 kernel_entry 0, 32 755 b el0_fiq_naked 756SYM_CODE_END(el0_fiq_compat) 757 758SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) 759 kernel_entry 0, 32 760 b el0_error_naked 761SYM_CODE_END(el0_error_compat) 762#endif 763 764 .align 6 765SYM_CODE_START_LOCAL_NOALIGN(el0_irq) 766 kernel_entry 0 767el0_irq_naked: 768 el0_interrupt_handler handle_arch_irq 769 b ret_to_user 770SYM_CODE_END(el0_irq) 771 772SYM_CODE_START_LOCAL_NOALIGN(el0_fiq) 773 kernel_entry 0 774el0_fiq_naked: 775 el0_interrupt_handler handle_arch_fiq 776 b ret_to_user 777SYM_CODE_END(el0_fiq) 778 779SYM_CODE_START_LOCAL(el1_error) 780 kernel_entry 1 781 mrs x1, esr_el1 782 enable_dbg 783 mov x0, sp 784 bl do_serror 785 kernel_exit 1 786SYM_CODE_END(el1_error) 787 788SYM_CODE_START_LOCAL(el0_error) 789 kernel_entry 0 790el0_error_naked: 791 mrs x25, esr_el1 792 user_exit_irqoff 793 enable_dbg 794 mov x0, sp 795 mov x1, x25 796 bl do_serror 797 enable_da 798 b ret_to_user 799SYM_CODE_END(el0_error) 800 801/* 802 * "slow" syscall return path. 803 */ 804SYM_CODE_START_LOCAL(ret_to_user) 805 disable_daif 806 gic_prio_kentry_setup tmp=x3 807#ifdef CONFIG_TRACE_IRQFLAGS 808 bl trace_hardirqs_off 809#endif 810 ldr x19, [tsk, #TSK_TI_FLAGS] 811 and x2, x19, #_TIF_WORK_MASK 812 cbnz x2, work_pending 813finish_ret_to_user: 814 user_enter_irqoff 815 /* Ignore asynchronous tag check faults in the uaccess routines */ 816 clear_mte_async_tcf 817 enable_step_tsk x19, x2 818#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 819 bl stackleak_erase 820#endif 821 kernel_exit 0 822 823/* 824 * Ok, we need to do extra processing, enter the slow path. 825 */ 826work_pending: 827 mov x0, sp // 'regs' 828 mov x1, x19 829 bl do_notify_resume 830 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 831 b finish_ret_to_user 832SYM_CODE_END(ret_to_user) 833 834 .popsection // .entry.text 835 836#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 837/* 838 * Exception vectors trampoline. 839 */ 840 .pushsection ".entry.tramp.text", "ax" 841 842 // Move from tramp_pg_dir to swapper_pg_dir 843 .macro tramp_map_kernel, tmp 844 mrs \tmp, ttbr1_el1 845 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 846 bic \tmp, \tmp, #USER_ASID_FLAG 847 msr ttbr1_el1, \tmp 848#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 849alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 850 /* ASID already in \tmp[63:48] */ 851 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 852 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 853 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 854 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 855 isb 856 tlbi vae1, \tmp 857 dsb nsh 858alternative_else_nop_endif 859#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 860 .endm 861 862 // Move from swapper_pg_dir to tramp_pg_dir 863 .macro tramp_unmap_kernel, tmp 864 mrs \tmp, ttbr1_el1 865 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 866 orr \tmp, \tmp, #USER_ASID_FLAG 867 msr ttbr1_el1, \tmp 868 /* 869 * We avoid running the post_ttbr_update_workaround here because 870 * it's only needed by Cavium ThunderX, which requires KPTI to be 871 * disabled. 872 */ 873 .endm 874 875 .macro tramp_ventry, regsize = 64 876 .align 7 8771: 878 .if \regsize == 64 879 msr tpidrro_el0, x30 // Restored in kernel_ventry 880 .endif 881 /* 882 * Defend against branch aliasing attacks by pushing a dummy 883 * entry onto the return stack and using a RET instruction to 884 * enter the full-fat kernel vectors. 885 */ 886 bl 2f 887 b . 8882: 889 tramp_map_kernel x30 890#ifdef CONFIG_RANDOMIZE_BASE 891 adr x30, tramp_vectors + PAGE_SIZE 892alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 893 ldr x30, [x30] 894#else 895 ldr x30, =vectors 896#endif 897alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 898 prfm plil1strm, [x30, #(1b - tramp_vectors)] 899alternative_else_nop_endif 900 msr vbar_el1, x30 901 add x30, x30, #(1b - tramp_vectors) 902 isb 903 ret 904 .endm 905 906 .macro tramp_exit, regsize = 64 907 adr x30, tramp_vectors 908 msr vbar_el1, x30 909 tramp_unmap_kernel x30 910 .if \regsize == 64 911 mrs x30, far_el1 912 .endif 913 eret 914 sb 915 .endm 916 917 .align 11 918SYM_CODE_START_NOALIGN(tramp_vectors) 919 .space 0x400 920 921 tramp_ventry 922 tramp_ventry 923 tramp_ventry 924 tramp_ventry 925 926 tramp_ventry 32 927 tramp_ventry 32 928 tramp_ventry 32 929 tramp_ventry 32 930SYM_CODE_END(tramp_vectors) 931 932SYM_CODE_START(tramp_exit_native) 933 tramp_exit 934SYM_CODE_END(tramp_exit_native) 935 936SYM_CODE_START(tramp_exit_compat) 937 tramp_exit 32 938SYM_CODE_END(tramp_exit_compat) 939 940 .ltorg 941 .popsection // .entry.tramp.text 942#ifdef CONFIG_RANDOMIZE_BASE 943 .pushsection ".rodata", "a" 944 .align PAGE_SHIFT 945SYM_DATA_START(__entry_tramp_data_start) 946 .quad vectors 947SYM_DATA_END(__entry_tramp_data_start) 948 .popsection // .rodata 949#endif /* CONFIG_RANDOMIZE_BASE */ 950#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 951 952/* 953 * Register switch for AArch64. The callee-saved registers need to be saved 954 * and restored. On entry: 955 * x0 = previous task_struct (must be preserved across the switch) 956 * x1 = next task_struct 957 * Previous and next are guaranteed not to be the same. 958 * 959 */ 960SYM_FUNC_START(cpu_switch_to) 961 mov x10, #THREAD_CPU_CONTEXT 962 add x8, x0, x10 963 mov x9, sp 964 stp x19, x20, [x8], #16 // store callee-saved registers 965 stp x21, x22, [x8], #16 966 stp x23, x24, [x8], #16 967 stp x25, x26, [x8], #16 968 stp x27, x28, [x8], #16 969 stp x29, x9, [x8], #16 970 str lr, [x8] 971 add x8, x1, x10 972 ldp x19, x20, [x8], #16 // restore callee-saved registers 973 ldp x21, x22, [x8], #16 974 ldp x23, x24, [x8], #16 975 ldp x25, x26, [x8], #16 976 ldp x27, x28, [x8], #16 977 ldp x29, x9, [x8], #16 978 ldr lr, [x8] 979 mov sp, x9 980 msr sp_el0, x1 981 ptrauth_keys_install_kernel x1, x8, x9, x10 982 scs_save x0, x8 983 scs_load x1, x8 984 ret 985SYM_FUNC_END(cpu_switch_to) 986NOKPROBE(cpu_switch_to) 987 988/* 989 * This is how we return from a fork. 990 */ 991SYM_CODE_START(ret_from_fork) 992 bl schedule_tail 993 cbz x19, 1f // not a kernel thread 994 mov x0, x20 995 blr x19 9961: get_current_task tsk 997 b ret_to_user 998SYM_CODE_END(ret_from_fork) 999NOKPROBE(ret_from_fork) 1000 1001#ifdef CONFIG_ARM_SDE_INTERFACE 1002 1003#include <asm/sdei.h> 1004#include <uapi/linux/arm_sdei.h> 1005 1006.macro sdei_handler_exit exit_mode 1007 /* On success, this call never returns... */ 1008 cmp \exit_mode, #SDEI_EXIT_SMC 1009 b.ne 99f 1010 smc #0 1011 b . 101299: hvc #0 1013 b . 1014.endm 1015 1016#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1017/* 1018 * The regular SDEI entry point may have been unmapped along with the rest of 1019 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 1020 * argument accessible. 1021 * 1022 * This clobbers x4, __sdei_handler() will restore this from firmware's 1023 * copy. 1024 */ 1025.ltorg 1026.pushsection ".entry.tramp.text", "ax" 1027SYM_CODE_START(__sdei_asm_entry_trampoline) 1028 mrs x4, ttbr1_el1 1029 tbz x4, #USER_ASID_BIT, 1f 1030 1031 tramp_map_kernel tmp=x4 1032 isb 1033 mov x4, xzr 1034 1035 /* 1036 * Remember whether to unmap the kernel on exit. 1037 */ 10381: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 1039 1040#ifdef CONFIG_RANDOMIZE_BASE 1041 adr x4, tramp_vectors + PAGE_SIZE 1042 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler 1043 ldr x4, [x4] 1044#else 1045 ldr x4, =__sdei_asm_handler 1046#endif 1047 br x4 1048SYM_CODE_END(__sdei_asm_entry_trampoline) 1049NOKPROBE(__sdei_asm_entry_trampoline) 1050 1051/* 1052 * Make the exit call and restore the original ttbr1_el1 1053 * 1054 * x0 & x1: setup for the exit API call 1055 * x2: exit_mode 1056 * x4: struct sdei_registered_event argument from registration time. 1057 */ 1058SYM_CODE_START(__sdei_asm_exit_trampoline) 1059 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 1060 cbnz x4, 1f 1061 1062 tramp_unmap_kernel tmp=x4 1063 10641: sdei_handler_exit exit_mode=x2 1065SYM_CODE_END(__sdei_asm_exit_trampoline) 1066NOKPROBE(__sdei_asm_exit_trampoline) 1067 .ltorg 1068.popsection // .entry.tramp.text 1069#ifdef CONFIG_RANDOMIZE_BASE 1070.pushsection ".rodata", "a" 1071SYM_DATA_START(__sdei_asm_trampoline_next_handler) 1072 .quad __sdei_asm_handler 1073SYM_DATA_END(__sdei_asm_trampoline_next_handler) 1074.popsection // .rodata 1075#endif /* CONFIG_RANDOMIZE_BASE */ 1076#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1077 1078/* 1079 * Software Delegated Exception entry point. 1080 * 1081 * x0: Event number 1082 * x1: struct sdei_registered_event argument from registration time. 1083 * x2: interrupted PC 1084 * x3: interrupted PSTATE 1085 * x4: maybe clobbered by the trampoline 1086 * 1087 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 1088 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 1089 * want them. 1090 */ 1091SYM_CODE_START(__sdei_asm_handler) 1092 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 1093 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 1094 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 1095 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 1096 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 1097 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 1098 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 1099 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 1100 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 1101 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 1102 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 1103 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 1104 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1105 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1106 mov x4, sp 1107 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1108 1109 mov x19, x1 1110 1111#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1112 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1113#endif 1114 1115#ifdef CONFIG_VMAP_STACK 1116 /* 1117 * entry.S may have been using sp as a scratch register, find whether 1118 * this is a normal or critical event and switch to the appropriate 1119 * stack for this CPU. 1120 */ 1121 cbnz w4, 1f 1122 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1123 b 2f 11241: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 11252: mov x6, #SDEI_STACK_SIZE 1126 add x5, x5, x6 1127 mov sp, x5 1128#endif 1129 1130#ifdef CONFIG_SHADOW_CALL_STACK 1131 /* Use a separate shadow call stack for normal and critical events */ 1132 cbnz w4, 3f 1133 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 1134 b 4f 11353: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 11364: 1137#endif 1138 1139 /* 1140 * We may have interrupted userspace, or a guest, or exit-from or 1141 * return-to either of these. We can't trust sp_el0, restore it. 1142 */ 1143 mrs x28, sp_el0 1144 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1145 msr sp_el0, x0 1146 1147 /* If we interrupted the kernel point to the previous stack/frame. */ 1148 and x0, x3, #0xc 1149 mrs x1, CurrentEL 1150 cmp x0, x1 1151 csel x29, x29, xzr, eq // fp, or zero 1152 csel x4, x2, xzr, eq // elr, or zero 1153 1154 stp x29, x4, [sp, #-16]! 1155 mov x29, sp 1156 1157 add x0, x19, #SDEI_EVENT_INTREGS 1158 mov x1, x19 1159 bl __sdei_handler 1160 1161 msr sp_el0, x28 1162 /* restore regs >x17 that we clobbered */ 1163 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1164 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1165 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1166 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1167 mov sp, x1 1168 1169 mov x1, x0 // address to complete_and_resume 1170 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1171 cmp x0, #1 1172 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1173 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1174 csel x0, x2, x3, ls 1175 1176 ldr_l x2, sdei_exit_mode 1177 1178alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1179 sdei_handler_exit exit_mode=x2 1180alternative_else_nop_endif 1181 1182#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1183 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1184 br x5 1185#endif 1186SYM_CODE_END(__sdei_asm_handler) 1187NOKPROBE(__sdei_asm_handler) 1188#endif /* CONFIG_ARM_SDE_INTERFACE */ 1189