1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32 .macro clear_gp_regs 33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 34 mov x\n, xzr 35 .endr 36 .endm 37 38 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req 39 .align 7 40.Lventry_start\@: 41 .if \el == 0 42 /* 43 * This must be the first instruction of the EL0 vector entries. It is 44 * skipped by the trampoline vectors, to trigger the cleanup. 45 */ 46 b .Lskip_tramp_vectors_cleanup\@ 47 .if \regsize == 64 48 mrs x30, tpidrro_el0 49 msr tpidrro_el0, xzr 50 .else 51 mov x30, xzr 52 .endif 53.Lskip_tramp_vectors_cleanup\@: 54 .endif 55 56 sub sp, sp, #PT_REGS_SIZE 57#ifdef CONFIG_VMAP_STACK 58 /* 59 * Test whether the SP has overflowed, without corrupting a GPR. 60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 61 * should always be zero. 62 */ 63 add sp, sp, x0 // sp' = sp + x0 64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 65 tbnz x0, #THREAD_SHIFT, 0f 66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 68 b el\el\ht\()_\regsize\()_\label 69 700: 71 /* 72 * Either we've just detected an overflow, or we've taken an exception 73 * while on the overflow stack. Either way, we won't return to 74 * userspace, and can clobber EL0 registers to free up GPRs. 75 */ 76 77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ 78 msr tpidr_el0, x0 79 80 /* Recover the original x0 value and stash it in tpidrro_el0 */ 81 sub x0, sp, x0 82 msr tpidrro_el0, x0 83 84 /* Switch to the overflow stack */ 85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 86 87 /* 88 * Check whether we were already on the overflow stack. This may happen 89 * after panic() re-enables interrupts. 90 */ 91 mrs x0, tpidr_el0 // sp of interrupted context 92 sub x0, sp, x0 // delta with top of overflow stack 93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 94 b.ne __bad_stack // no? -> bad stack pointer 95 96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 97 sub sp, sp, x0 98 mrs x0, tpidrro_el0 99#endif 100 b el\el\ht\()_\regsize\()_\label 101.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? 102 .endm 103 104 .macro tramp_alias, dst, sym 105 .set .Lalias\@, TRAMP_VALIAS + \sym - .entry.tramp.text 106 movz \dst, :abs_g2_s:.Lalias\@ 107 movk \dst, :abs_g1_nc:.Lalias\@ 108 movk \dst, :abs_g0_nc:.Lalias\@ 109 .endm 110 111 /* 112 * This macro corrupts x0-x3. It is the caller's duty to save/restore 113 * them if required. 114 */ 115 .macro apply_ssbd, state, tmp1, tmp2 116alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable 117 b .L__asm_ssbd_skip\@ // Patched to NOP 118alternative_cb_end 119 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 120 cbz \tmp2, .L__asm_ssbd_skip\@ 121 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 122 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 123 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 124 mov w1, #\state 125alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit 126 nop // Patched to SMC/HVC #0 127alternative_cb_end 128.L__asm_ssbd_skip\@: 129 .endm 130 131 /* Check for MTE asynchronous tag check faults */ 132 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr 133#ifdef CONFIG_ARM64_MTE 134 .arch_extension lse 135alternative_if_not ARM64_MTE 136 b 1f 137alternative_else_nop_endif 138 /* 139 * Asynchronous tag check faults are only possible in ASYNC (2) or 140 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is 141 * set, so skip the check if it is unset. 142 */ 143 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 144 mrs_s \tmp, SYS_TFSRE0_EL1 145 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 146 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 147 mov \tmp, #_TIF_MTE_ASYNC_FAULT 148 add \ti_flags, tsk, #TSK_TI_FLAGS 149 stset \tmp, [\ti_flags] 1501: 151#endif 152 .endm 153 154 /* Clear the MTE asynchronous tag check faults */ 155 .macro clear_mte_async_tcf thread_sctlr 156#ifdef CONFIG_ARM64_MTE 157alternative_if ARM64_MTE 158 /* See comment in check_mte_async_tcf above. */ 159 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 160 dsb ish 161 msr_s SYS_TFSRE0_EL1, xzr 1621: 163alternative_else_nop_endif 164#endif 165 .endm 166 167 .macro mte_set_gcr, mte_ctrl, tmp 168#ifdef CONFIG_ARM64_MTE 169 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 170 orr \tmp, \tmp, #SYS_GCR_EL1_RRND 171 msr_s SYS_GCR_EL1, \tmp 172#endif 173 .endm 174 175 .macro mte_set_kernel_gcr, tmp, tmp2 176#ifdef CONFIG_KASAN_HW_TAGS 177alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 178 b 1f 179alternative_cb_end 180 mov \tmp, KERNEL_GCR_EL1 181 msr_s SYS_GCR_EL1, \tmp 1821: 183#endif 184 .endm 185 186 .macro mte_set_user_gcr, tsk, tmp, tmp2 187#ifdef CONFIG_KASAN_HW_TAGS 188alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 189 b 1f 190alternative_cb_end 191 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] 192 193 mte_set_gcr \tmp, \tmp2 1941: 195#endif 196 .endm 197 198 .macro kernel_entry, el, regsize = 64 199 .if \el == 0 200 alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT 201 .endif 202 .if \regsize == 32 203 mov w0, w0 // zero upper 32 bits of x0 204 .endif 205 stp x0, x1, [sp, #16 * 0] 206 stp x2, x3, [sp, #16 * 1] 207 stp x4, x5, [sp, #16 * 2] 208 stp x6, x7, [sp, #16 * 3] 209 stp x8, x9, [sp, #16 * 4] 210 stp x10, x11, [sp, #16 * 5] 211 stp x12, x13, [sp, #16 * 6] 212 stp x14, x15, [sp, #16 * 7] 213 stp x16, x17, [sp, #16 * 8] 214 stp x18, x19, [sp, #16 * 9] 215 stp x20, x21, [sp, #16 * 10] 216 stp x22, x23, [sp, #16 * 11] 217 stp x24, x25, [sp, #16 * 12] 218 stp x26, x27, [sp, #16 * 13] 219 stp x28, x29, [sp, #16 * 14] 220 221 .if \el == 0 222 clear_gp_regs 223 mrs x21, sp_el0 224 ldr_this_cpu tsk, __entry_task, x20 225 msr sp_el0, tsk 226 227 /* 228 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 229 * when scheduling. 230 */ 231 ldr x19, [tsk, #TSK_TI_FLAGS] 232 disable_step_tsk x19, x20 233 234 /* Check for asynchronous tag check faults in user space */ 235 ldr x0, [tsk, THREAD_SCTLR_USER] 236 check_mte_async_tcf x22, x23, x0 237 238#ifdef CONFIG_ARM64_PTR_AUTH 239alternative_if ARM64_HAS_ADDRESS_AUTH 240 /* 241 * Enable IA for in-kernel PAC if the task had it disabled. Although 242 * this could be implemented with an unconditional MRS which would avoid 243 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. 244 * 245 * Install the kernel IA key only if IA was enabled in the task. If IA 246 * was disabled on kernel exit then we would have left the kernel IA 247 * installed so there is no need to install it again. 248 */ 249 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 250 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 251 b 2f 2521: 253 mrs x0, sctlr_el1 254 orr x0, x0, SCTLR_ELx_ENIA 255 msr sctlr_el1, x0 2562: 257alternative_else_nop_endif 258#endif 259 260 apply_ssbd 1, x22, x23 261 262 mte_set_kernel_gcr x22, x23 263 264 /* 265 * Any non-self-synchronizing system register updates required for 266 * kernel entry should be placed before this point. 267 */ 268alternative_if ARM64_MTE 269 isb 270 b 1f 271alternative_else_nop_endif 272alternative_if ARM64_HAS_ADDRESS_AUTH 273 isb 274alternative_else_nop_endif 2751: 276 277 scs_load_current 278 .else 279 add x21, sp, #PT_REGS_SIZE 280 get_current_task tsk 281 .endif /* \el == 0 */ 282 mrs x22, elr_el1 283 mrs x23, spsr_el1 284 stp lr, x21, [sp, #S_LR] 285 286 /* 287 * For exceptions from EL0, create a final frame record. 288 * For exceptions from EL1, create a synthetic frame record so the 289 * interrupted code shows up in the backtrace. 290 */ 291 .if \el == 0 292 stp xzr, xzr, [sp, #S_STACKFRAME] 293 .else 294 stp x29, x22, [sp, #S_STACKFRAME] 295 .endif 296 add x29, sp, #S_STACKFRAME 297 298#ifdef CONFIG_ARM64_SW_TTBR0_PAN 299alternative_if_not ARM64_HAS_PAN 300 bl __swpan_entry_el\el 301alternative_else_nop_endif 302#endif 303 304 stp x22, x23, [sp, #S_PC] 305 306 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 307 .if \el == 0 308 mov w21, #NO_SYSCALL 309 str w21, [sp, #S_SYSCALLNO] 310 .endif 311 312#ifdef CONFIG_ARM64_PSEUDO_NMI 313alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 314 b .Lskip_pmr_save\@ 315alternative_else_nop_endif 316 317 mrs_s x20, SYS_ICC_PMR_EL1 318 str x20, [sp, #S_PMR_SAVE] 319 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET 320 msr_s SYS_ICC_PMR_EL1, x20 321 322.Lskip_pmr_save\@: 323#endif 324 325 /* 326 * Registers that may be useful after this macro is invoked: 327 * 328 * x20 - ICC_PMR_EL1 329 * x21 - aborted SP 330 * x22 - aborted PC 331 * x23 - aborted PSTATE 332 */ 333 .endm 334 335 .macro kernel_exit, el 336 .if \el != 0 337 disable_daif 338 .endif 339 340#ifdef CONFIG_ARM64_PSEUDO_NMI 341alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 342 b .Lskip_pmr_restore\@ 343alternative_else_nop_endif 344 345 ldr x20, [sp, #S_PMR_SAVE] 346 msr_s SYS_ICC_PMR_EL1, x20 347 348 /* Ensure priority change is seen by redistributor */ 349alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_SYNC 350 dsb sy 351alternative_else_nop_endif 352 353.Lskip_pmr_restore\@: 354#endif 355 356 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 357 358#ifdef CONFIG_ARM64_SW_TTBR0_PAN 359alternative_if_not ARM64_HAS_PAN 360 bl __swpan_exit_el\el 361alternative_else_nop_endif 362#endif 363 364 .if \el == 0 365 ldr x23, [sp, #S_SP] // load return stack pointer 366 msr sp_el0, x23 367 tst x22, #PSR_MODE32_BIT // native task? 368 b.eq 3f 369 370#ifdef CONFIG_ARM64_ERRATUM_845719 371alternative_if ARM64_WORKAROUND_845719 372#ifdef CONFIG_PID_IN_CONTEXTIDR 373 mrs x29, contextidr_el1 374 msr contextidr_el1, x29 375#else 376 msr contextidr_el1, xzr 377#endif 378alternative_else_nop_endif 379#endif 3803: 381 scs_save tsk 382 383 /* Ignore asynchronous tag check faults in the uaccess routines */ 384 ldr x0, [tsk, THREAD_SCTLR_USER] 385 clear_mte_async_tcf x0 386 387#ifdef CONFIG_ARM64_PTR_AUTH 388alternative_if ARM64_HAS_ADDRESS_AUTH 389 /* 390 * IA was enabled for in-kernel PAC. Disable it now if needed, or 391 * alternatively install the user's IA. All other per-task keys and 392 * SCTLR bits were updated on task switch. 393 * 394 * No kernel C function calls after this. 395 */ 396 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 397 __ptrauth_keys_install_user tsk, x0, x1, x2 398 b 2f 3991: 400 mrs x0, sctlr_el1 401 bic x0, x0, SCTLR_ELx_ENIA 402 msr sctlr_el1, x0 4032: 404alternative_else_nop_endif 405#endif 406 407 mte_set_user_gcr tsk, x0, x1 408 409 apply_ssbd 0, x0, x1 410 .endif 411 412 msr elr_el1, x21 // set up the return data 413 msr spsr_el1, x22 414 ldp x0, x1, [sp, #16 * 0] 415 ldp x2, x3, [sp, #16 * 1] 416 ldp x4, x5, [sp, #16 * 2] 417 ldp x6, x7, [sp, #16 * 3] 418 ldp x8, x9, [sp, #16 * 4] 419 ldp x10, x11, [sp, #16 * 5] 420 ldp x12, x13, [sp, #16 * 6] 421 ldp x14, x15, [sp, #16 * 7] 422 ldp x16, x17, [sp, #16 * 8] 423 ldp x18, x19, [sp, #16 * 9] 424 ldp x20, x21, [sp, #16 * 10] 425 ldp x22, x23, [sp, #16 * 11] 426 ldp x24, x25, [sp, #16 * 12] 427 ldp x26, x27, [sp, #16 * 13] 428 ldp x28, x29, [sp, #16 * 14] 429 430 .if \el == 0 431#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 432 alternative_insn "b .L_skip_tramp_exit_\@", nop, ARM64_UNMAP_KERNEL_AT_EL0 433 434 msr far_el1, x29 435 436 ldr_this_cpu x30, this_cpu_vector, x29 437 tramp_alias x29, tramp_exit 438 msr vbar_el1, x30 // install vector table 439 ldr lr, [sp, #S_LR] // restore x30 440 add sp, sp, #PT_REGS_SIZE // restore sp 441 br x29 442 443.L_skip_tramp_exit_\@: 444#endif 445 ldr lr, [sp, #S_LR] 446 add sp, sp, #PT_REGS_SIZE // restore sp 447 448 /* This must be after the last explicit memory access */ 449alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 450 tlbi vale1, xzr 451 dsb nsh 452alternative_else_nop_endif 453 eret 454 .else 455 ldr lr, [sp, #S_LR] 456 add sp, sp, #PT_REGS_SIZE // restore sp 457 458 /* Ensure any device/NC reads complete */ 459 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 460 461 eret 462 .endif 463 sb 464 .endm 465 466#ifdef CONFIG_ARM64_SW_TTBR0_PAN 467 /* 468 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 469 * EL0, there is no need to check the state of TTBR0_EL1 since 470 * accesses are always enabled. 471 * Note that the meaning of this bit differs from the ARMv8.1 PAN 472 * feature as all TTBR0_EL1 accesses are disabled, not just those to 473 * user mappings. 474 */ 475SYM_CODE_START_LOCAL(__swpan_entry_el1) 476 mrs x21, ttbr0_el1 477 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 478 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 479 b.eq 1f // TTBR0 access already disabled 480 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 481SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 482 __uaccess_ttbr0_disable x21 4831: ret 484SYM_CODE_END(__swpan_entry_el1) 485 486 /* 487 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 488 * PAN bit checking. 489 */ 490SYM_CODE_START_LOCAL(__swpan_exit_el1) 491 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 492 __uaccess_ttbr0_enable x0, x1 4931: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 494 ret 495SYM_CODE_END(__swpan_exit_el1) 496 497SYM_CODE_START_LOCAL(__swpan_exit_el0) 498 __uaccess_ttbr0_enable x0, x1 499 /* 500 * Enable errata workarounds only if returning to user. The only 501 * workaround currently required for TTBR0_EL1 changes are for the 502 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 503 * corruption). 504 */ 505 b post_ttbr_update_workaround 506SYM_CODE_END(__swpan_exit_el0) 507#endif 508 509/* GPRs used by entry code */ 510tsk .req x28 // current thread_info 511 512 .text 513 514/* 515 * Exception vectors. 516 */ 517 .pushsection ".entry.text", "ax" 518 519 .align 11 520SYM_CODE_START(vectors) 521 kernel_ventry 1, t, 64, sync // Synchronous EL1t 522 kernel_ventry 1, t, 64, irq // IRQ EL1t 523 kernel_ventry 1, t, 64, fiq // FIQ EL1t 524 kernel_ventry 1, t, 64, error // Error EL1t 525 526 kernel_ventry 1, h, 64, sync // Synchronous EL1h 527 kernel_ventry 1, h, 64, irq // IRQ EL1h 528 kernel_ventry 1, h, 64, fiq // FIQ EL1h 529 kernel_ventry 1, h, 64, error // Error EL1h 530 531 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0 532 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0 533 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0 534 kernel_ventry 0, t, 64, error // Error 64-bit EL0 535 536 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0 537 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0 538 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0 539 kernel_ventry 0, t, 32, error // Error 32-bit EL0 540SYM_CODE_END(vectors) 541 542#ifdef CONFIG_VMAP_STACK 543SYM_CODE_START_LOCAL(__bad_stack) 544 /* 545 * We detected an overflow in kernel_ventry, which switched to the 546 * overflow stack. Stash the exception regs, and head to our overflow 547 * handler. 548 */ 549 550 /* Restore the original x0 value */ 551 mrs x0, tpidrro_el0 552 553 /* 554 * Store the original GPRs to the new stack. The orginal SP (minus 555 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. 556 */ 557 sub sp, sp, #PT_REGS_SIZE 558 kernel_entry 1 559 mrs x0, tpidr_el0 560 add x0, x0, #PT_REGS_SIZE 561 str x0, [sp, #S_SP] 562 563 /* Stash the regs for handle_bad_stack */ 564 mov x0, sp 565 566 /* Time to die */ 567 bl handle_bad_stack 568 ASM_BUG() 569SYM_CODE_END(__bad_stack) 570#endif /* CONFIG_VMAP_STACK */ 571 572 573 .macro entry_handler el:req, ht:req, regsize:req, label:req 574SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label) 575 kernel_entry \el, \regsize 576 mov x0, sp 577 bl el\el\ht\()_\regsize\()_\label\()_handler 578 .if \el == 0 579 b ret_to_user 580 .else 581 b ret_to_kernel 582 .endif 583SYM_CODE_END(el\el\ht\()_\regsize\()_\label) 584 .endm 585 586/* 587 * Early exception handlers 588 */ 589 entry_handler 1, t, 64, sync 590 entry_handler 1, t, 64, irq 591 entry_handler 1, t, 64, fiq 592 entry_handler 1, t, 64, error 593 594 entry_handler 1, h, 64, sync 595 entry_handler 1, h, 64, irq 596 entry_handler 1, h, 64, fiq 597 entry_handler 1, h, 64, error 598 599 entry_handler 0, t, 64, sync 600 entry_handler 0, t, 64, irq 601 entry_handler 0, t, 64, fiq 602 entry_handler 0, t, 64, error 603 604 entry_handler 0, t, 32, sync 605 entry_handler 0, t, 32, irq 606 entry_handler 0, t, 32, fiq 607 entry_handler 0, t, 32, error 608 609SYM_CODE_START_LOCAL(ret_to_kernel) 610 kernel_exit 1 611SYM_CODE_END(ret_to_kernel) 612 613SYM_CODE_START_LOCAL(ret_to_user) 614 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 615 enable_step_tsk x19, x2 616#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 617 bl stackleak_erase_on_task_stack 618#endif 619 kernel_exit 0 620SYM_CODE_END(ret_to_user) 621 622 .popsection // .entry.text 623 624 // Move from tramp_pg_dir to swapper_pg_dir 625 .macro tramp_map_kernel, tmp 626 mrs \tmp, ttbr1_el1 627 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 628 bic \tmp, \tmp, #USER_ASID_FLAG 629 msr ttbr1_el1, \tmp 630#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 631alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 632 /* ASID already in \tmp[63:48] */ 633 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 634 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 635 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 636 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 637 isb 638 tlbi vae1, \tmp 639 dsb nsh 640alternative_else_nop_endif 641#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 642 .endm 643 644 // Move from swapper_pg_dir to tramp_pg_dir 645 .macro tramp_unmap_kernel, tmp 646 mrs \tmp, ttbr1_el1 647 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 648 orr \tmp, \tmp, #USER_ASID_FLAG 649 msr ttbr1_el1, \tmp 650 /* 651 * We avoid running the post_ttbr_update_workaround here because 652 * it's only needed by Cavium ThunderX, which requires KPTI to be 653 * disabled. 654 */ 655 .endm 656 657 .macro tramp_data_read_var dst, var 658#ifdef CONFIG_RELOCATABLE 659 ldr \dst, .L__tramp_data_\var 660 .ifndef .L__tramp_data_\var 661 .pushsection ".entry.tramp.rodata", "a", %progbits 662 .align 3 663.L__tramp_data_\var: 664 .quad \var 665 .popsection 666 .endif 667#else 668 /* 669 * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a 670 * compile time constant (and hence not secret and not worth hiding). 671 * 672 * As statically allocated kernel code and data always live in the top 673 * 47 bits of the address space we can sign-extend bit 47 and avoid an 674 * instruction to load the upper 16 bits (which must be 0xFFFF). 675 */ 676 movz \dst, :abs_g2_s:\var 677 movk \dst, :abs_g1_nc:\var 678 movk \dst, :abs_g0_nc:\var 679#endif 680 .endm 681 682#define BHB_MITIGATION_NONE 0 683#define BHB_MITIGATION_LOOP 1 684#define BHB_MITIGATION_FW 2 685#define BHB_MITIGATION_INSN 3 686 687 .macro tramp_ventry, vector_start, regsize, kpti, bhb 688 .align 7 6891: 690 .if \regsize == 64 691 msr tpidrro_el0, x30 // Restored in kernel_ventry 692 .endif 693 694 .if \bhb == BHB_MITIGATION_LOOP 695 /* 696 * This sequence must appear before the first indirect branch. i.e. the 697 * ret out of tramp_ventry. It appears here because x30 is free. 698 */ 699 __mitigate_spectre_bhb_loop x30 700 .endif // \bhb == BHB_MITIGATION_LOOP 701 702 .if \bhb == BHB_MITIGATION_INSN 703 clearbhb 704 isb 705 .endif // \bhb == BHB_MITIGATION_INSN 706 707 .if \kpti == 1 708 /* 709 * Defend against branch aliasing attacks by pushing a dummy 710 * entry onto the return stack and using a RET instruction to 711 * enter the full-fat kernel vectors. 712 */ 713 bl 2f 714 b . 7152: 716 tramp_map_kernel x30 717alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 718 tramp_data_read_var x30, vectors 719alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 720 prfm plil1strm, [x30, #(1b - \vector_start)] 721alternative_else_nop_endif 722 723 msr vbar_el1, x30 724 isb 725 .else 726 adr_l x30, vectors 727 .endif // \kpti == 1 728 729 .if \bhb == BHB_MITIGATION_FW 730 /* 731 * The firmware sequence must appear before the first indirect branch. 732 * i.e. the ret out of tramp_ventry. But it also needs the stack to be 733 * mapped to save/restore the registers the SMC clobbers. 734 */ 735 __mitigate_spectre_bhb_fw 736 .endif // \bhb == BHB_MITIGATION_FW 737 738 add x30, x30, #(1b - \vector_start + 4) 739 ret 740.org 1b + 128 // Did we overflow the ventry slot? 741 .endm 742 743 .macro generate_tramp_vector, kpti, bhb 744.Lvector_start\@: 745 .space 0x400 746 747 .rept 4 748 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb 749 .endr 750 .rept 4 751 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb 752 .endr 753 .endm 754 755#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 756/* 757 * Exception vectors trampoline. 758 * The order must match __bp_harden_el1_vectors and the 759 * arm64_bp_harden_el1_vectors enum. 760 */ 761 .pushsection ".entry.tramp.text", "ax" 762 .align 11 763SYM_CODE_START_LOCAL_NOALIGN(tramp_vectors) 764#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 765 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP 766 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW 767 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN 768#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 769 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE 770SYM_CODE_END(tramp_vectors) 771 772SYM_CODE_START_LOCAL(tramp_exit) 773 tramp_unmap_kernel x29 774 mrs x29, far_el1 // restore x29 775 eret 776 sb 777SYM_CODE_END(tramp_exit) 778 .popsection // .entry.tramp.text 779#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 780 781/* 782 * Exception vectors for spectre mitigations on entry from EL1 when 783 * kpti is not in use. 784 */ 785 .macro generate_el1_vector, bhb 786.Lvector_start\@: 787 kernel_ventry 1, t, 64, sync // Synchronous EL1t 788 kernel_ventry 1, t, 64, irq // IRQ EL1t 789 kernel_ventry 1, t, 64, fiq // FIQ EL1h 790 kernel_ventry 1, t, 64, error // Error EL1t 791 792 kernel_ventry 1, h, 64, sync // Synchronous EL1h 793 kernel_ventry 1, h, 64, irq // IRQ EL1h 794 kernel_ventry 1, h, 64, fiq // FIQ EL1h 795 kernel_ventry 1, h, 64, error // Error EL1h 796 797 .rept 4 798 tramp_ventry .Lvector_start\@, 64, 0, \bhb 799 .endr 800 .rept 4 801 tramp_ventry .Lvector_start\@, 32, 0, \bhb 802 .endr 803 .endm 804 805/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ 806 .pushsection ".entry.text", "ax" 807 .align 11 808SYM_CODE_START(__bp_harden_el1_vectors) 809#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 810 generate_el1_vector bhb=BHB_MITIGATION_LOOP 811 generate_el1_vector bhb=BHB_MITIGATION_FW 812 generate_el1_vector bhb=BHB_MITIGATION_INSN 813#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 814SYM_CODE_END(__bp_harden_el1_vectors) 815 .popsection 816 817 818/* 819 * Register switch for AArch64. The callee-saved registers need to be saved 820 * and restored. On entry: 821 * x0 = previous task_struct (must be preserved across the switch) 822 * x1 = next task_struct 823 * Previous and next are guaranteed not to be the same. 824 * 825 */ 826SYM_FUNC_START(cpu_switch_to) 827 mov x10, #THREAD_CPU_CONTEXT 828 add x8, x0, x10 829 mov x9, sp 830 stp x19, x20, [x8], #16 // store callee-saved registers 831 stp x21, x22, [x8], #16 832 stp x23, x24, [x8], #16 833 stp x25, x26, [x8], #16 834 stp x27, x28, [x8], #16 835 stp x29, x9, [x8], #16 836 str lr, [x8] 837 add x8, x1, x10 838 ldp x19, x20, [x8], #16 // restore callee-saved registers 839 ldp x21, x22, [x8], #16 840 ldp x23, x24, [x8], #16 841 ldp x25, x26, [x8], #16 842 ldp x27, x28, [x8], #16 843 ldp x29, x9, [x8], #16 844 ldr lr, [x8] 845 mov sp, x9 846 msr sp_el0, x1 847 ptrauth_keys_install_kernel x1, x8, x9, x10 848 scs_save x0 849 scs_load_current 850 ret 851SYM_FUNC_END(cpu_switch_to) 852NOKPROBE(cpu_switch_to) 853 854/* 855 * This is how we return from a fork. 856 */ 857SYM_CODE_START(ret_from_fork) 858 bl schedule_tail 859 cbz x19, 1f // not a kernel thread 860 mov x0, x20 861 blr x19 8621: get_current_task tsk 863 mov x0, sp 864 bl asm_exit_to_user_mode 865 b ret_to_user 866SYM_CODE_END(ret_from_fork) 867NOKPROBE(ret_from_fork) 868 869/* 870 * void call_on_irq_stack(struct pt_regs *regs, 871 * void (*func)(struct pt_regs *)); 872 * 873 * Calls func(regs) using this CPU's irq stack and shadow irq stack. 874 */ 875SYM_FUNC_START(call_on_irq_stack) 876#ifdef CONFIG_SHADOW_CALL_STACK 877 get_current_task x16 878 scs_save x16 879 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17 880#endif 881 882 /* Create a frame record to save our LR and SP (implicit in FP) */ 883 stp x29, x30, [sp, #-16]! 884 mov x29, sp 885 886 ldr_this_cpu x16, irq_stack_ptr, x17 887 888 /* Move to the new stack and call the function there */ 889 add sp, x16, #IRQ_STACK_SIZE 890 blr x1 891 892 /* 893 * Restore the SP from the FP, and restore the FP and LR from the frame 894 * record. 895 */ 896 mov sp, x29 897 ldp x29, x30, [sp], #16 898 scs_load_current 899 ret 900SYM_FUNC_END(call_on_irq_stack) 901NOKPROBE(call_on_irq_stack) 902 903#ifdef CONFIG_ARM_SDE_INTERFACE 904 905#include <asm/sdei.h> 906#include <uapi/linux/arm_sdei.h> 907 908.macro sdei_handler_exit exit_mode 909 /* On success, this call never returns... */ 910 cmp \exit_mode, #SDEI_EXIT_SMC 911 b.ne 99f 912 smc #0 913 b . 91499: hvc #0 915 b . 916.endm 917 918#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 919/* 920 * The regular SDEI entry point may have been unmapped along with the rest of 921 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 922 * argument accessible. 923 * 924 * This clobbers x4, __sdei_handler() will restore this from firmware's 925 * copy. 926 */ 927.pushsection ".entry.tramp.text", "ax" 928SYM_CODE_START(__sdei_asm_entry_trampoline) 929 mrs x4, ttbr1_el1 930 tbz x4, #USER_ASID_BIT, 1f 931 932 tramp_map_kernel tmp=x4 933 isb 934 mov x4, xzr 935 936 /* 937 * Remember whether to unmap the kernel on exit. 938 */ 9391: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 940 tramp_data_read_var x4, __sdei_asm_handler 941 br x4 942SYM_CODE_END(__sdei_asm_entry_trampoline) 943NOKPROBE(__sdei_asm_entry_trampoline) 944 945/* 946 * Make the exit call and restore the original ttbr1_el1 947 * 948 * x0 & x1: setup for the exit API call 949 * x2: exit_mode 950 * x4: struct sdei_registered_event argument from registration time. 951 */ 952SYM_CODE_START(__sdei_asm_exit_trampoline) 953 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 954 cbnz x4, 1f 955 956 tramp_unmap_kernel tmp=x4 957 9581: sdei_handler_exit exit_mode=x2 959SYM_CODE_END(__sdei_asm_exit_trampoline) 960NOKPROBE(__sdei_asm_exit_trampoline) 961.popsection // .entry.tramp.text 962#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 963 964/* 965 * Software Delegated Exception entry point. 966 * 967 * x0: Event number 968 * x1: struct sdei_registered_event argument from registration time. 969 * x2: interrupted PC 970 * x3: interrupted PSTATE 971 * x4: maybe clobbered by the trampoline 972 * 973 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 974 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 975 * want them. 976 */ 977SYM_CODE_START(__sdei_asm_handler) 978 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 979 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 980 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 981 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 982 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 983 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 984 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 985 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 986 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 987 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 988 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 989 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 990 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 991 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 992 mov x4, sp 993 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 994 995 mov x19, x1 996 997 /* Store the registered-event for crash_smp_send_stop() */ 998 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 999 cbnz w4, 1f 1000 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 1001 b 2f 10021: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10032: str x19, [x5] 1004 1005#ifdef CONFIG_VMAP_STACK 1006 /* 1007 * entry.S may have been using sp as a scratch register, find whether 1008 * this is a normal or critical event and switch to the appropriate 1009 * stack for this CPU. 1010 */ 1011 cbnz w4, 1f 1012 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1013 b 2f 10141: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10152: mov x6, #SDEI_STACK_SIZE 1016 add x5, x5, x6 1017 mov sp, x5 1018#endif 1019 1020#ifdef CONFIG_SHADOW_CALL_STACK 1021 /* Use a separate shadow call stack for normal and critical events */ 1022 cbnz w4, 3f 1023 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 1024 b 4f 10253: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 10264: 1027#endif 1028 1029 /* 1030 * We may have interrupted userspace, or a guest, or exit-from or 1031 * return-to either of these. We can't trust sp_el0, restore it. 1032 */ 1033 mrs x28, sp_el0 1034 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1035 msr sp_el0, x0 1036 1037 /* If we interrupted the kernel point to the previous stack/frame. */ 1038 and x0, x3, #0xc 1039 mrs x1, CurrentEL 1040 cmp x0, x1 1041 csel x29, x29, xzr, eq // fp, or zero 1042 csel x4, x2, xzr, eq // elr, or zero 1043 1044 stp x29, x4, [sp, #-16]! 1045 mov x29, sp 1046 1047 add x0, x19, #SDEI_EVENT_INTREGS 1048 mov x1, x19 1049 bl __sdei_handler 1050 1051 msr sp_el0, x28 1052 /* restore regs >x17 that we clobbered */ 1053 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1054 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1055 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1056 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1057 mov sp, x1 1058 1059 mov x1, x0 // address to complete_and_resume 1060 /* x0 = (x0 <= SDEI_EV_FAILED) ? 1061 * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME 1062 */ 1063 cmp x0, #SDEI_EV_FAILED 1064 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1065 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1066 csel x0, x2, x3, ls 1067 1068 ldr_l x2, sdei_exit_mode 1069 1070 /* Clear the registered-event seen by crash_smp_send_stop() */ 1071 ldrb w3, [x4, #SDEI_EVENT_PRIORITY] 1072 cbnz w3, 1f 1073 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 1074 b 2f 10751: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10762: str xzr, [x5] 1077 1078alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1079 sdei_handler_exit exit_mode=x2 1080alternative_else_nop_endif 1081 1082#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1083 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1084 br x5 1085#endif 1086SYM_CODE_END(__sdei_asm_handler) 1087NOKPROBE(__sdei_asm_handler) 1088 1089SYM_CODE_START(__sdei_handler_abort) 1090 mov_q x0, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1091 adr x1, 1f 1092 ldr_l x2, sdei_exit_mode 1093 sdei_handler_exit exit_mode=x2 1094 // exit the handler and jump to the next instruction. 1095 // Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx. 10961: ret 1097SYM_CODE_END(__sdei_handler_abort) 1098NOKPROBE(__sdei_handler_abort) 1099#endif /* CONFIG_ARM_SDE_INTERFACE */ 1100