1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32/* 33 * Context tracking and irqflag tracing need to instrument transitions between 34 * user and kernel mode. 35 */ 36 .macro user_exit_irqoff 37#if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS) 38 bl enter_from_user_mode 39#endif 40 .endm 41 42 .macro user_enter_irqoff 43#if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS) 44 bl exit_to_user_mode 45#endif 46 .endm 47 48 .macro clear_gp_regs 49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 50 mov x\n, xzr 51 .endr 52 .endm 53 54/* 55 * Bad Abort numbers 56 *----------------- 57 */ 58#define BAD_SYNC 0 59#define BAD_IRQ 1 60#define BAD_FIQ 2 61#define BAD_ERROR 3 62 63 .macro kernel_ventry, el, label, regsize = 64 64 .align 7 65#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 66 .if \el == 0 67alternative_if ARM64_UNMAP_KERNEL_AT_EL0 68 .if \regsize == 64 69 mrs x30, tpidrro_el0 70 msr tpidrro_el0, xzr 71 .else 72 mov x30, xzr 73 .endif 74alternative_else_nop_endif 75 .endif 76#endif 77 78 sub sp, sp, #S_FRAME_SIZE 79#ifdef CONFIG_VMAP_STACK 80 /* 81 * Test whether the SP has overflowed, without corrupting a GPR. 82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 83 * should always be zero. 84 */ 85 add sp, sp, x0 // sp' = sp + x0 86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 87 tbnz x0, #THREAD_SHIFT, 0f 88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 90 b el\()\el\()_\label 91 920: 93 /* 94 * Either we've just detected an overflow, or we've taken an exception 95 * while on the overflow stack. Either way, we won't return to 96 * userspace, and can clobber EL0 registers to free up GPRs. 97 */ 98 99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ 100 msr tpidr_el0, x0 101 102 /* Recover the original x0 value and stash it in tpidrro_el0 */ 103 sub x0, sp, x0 104 msr tpidrro_el0, x0 105 106 /* Switch to the overflow stack */ 107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 108 109 /* 110 * Check whether we were already on the overflow stack. This may happen 111 * after panic() re-enables interrupts. 112 */ 113 mrs x0, tpidr_el0 // sp of interrupted context 114 sub x0, sp, x0 // delta with top of overflow stack 115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 116 b.ne __bad_stack // no? -> bad stack pointer 117 118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 119 sub sp, sp, x0 120 mrs x0, tpidrro_el0 121#endif 122 b el\()\el\()_\label 123 .endm 124 125 .macro tramp_alias, dst, sym 126 mov_q \dst, TRAMP_VALIAS 127 add \dst, \dst, #(\sym - .entry.tramp.text) 128 .endm 129 130 /* 131 * This macro corrupts x0-x3. It is the caller's duty to save/restore 132 * them if required. 133 */ 134 .macro apply_ssbd, state, tmp1, tmp2 135alternative_cb spectre_v4_patch_fw_mitigation_enable 136 b .L__asm_ssbd_skip\@ // Patched to NOP 137alternative_cb_end 138 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 139 cbz \tmp2, .L__asm_ssbd_skip\@ 140 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 141 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 142 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 143 mov w1, #\state 144alternative_cb spectre_v4_patch_fw_mitigation_conduit 145 nop // Patched to SMC/HVC #0 146alternative_cb_end 147.L__asm_ssbd_skip\@: 148 .endm 149 150 /* Check for MTE asynchronous tag check faults */ 151 .macro check_mte_async_tcf, flgs, tmp 152#ifdef CONFIG_ARM64_MTE 153alternative_if_not ARM64_MTE 154 b 1f 155alternative_else_nop_endif 156 mrs_s \tmp, SYS_TFSRE0_EL1 157 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 158 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 159 orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT 160 str \flgs, [tsk, #TSK_TI_FLAGS] 161 msr_s SYS_TFSRE0_EL1, xzr 1621: 163#endif 164 .endm 165 166 /* Clear the MTE asynchronous tag check faults */ 167 .macro clear_mte_async_tcf 168#ifdef CONFIG_ARM64_MTE 169alternative_if ARM64_MTE 170 dsb ish 171 msr_s SYS_TFSRE0_EL1, xzr 172alternative_else_nop_endif 173#endif 174 .endm 175 176 .macro kernel_entry, el, regsize = 64 177 .if \regsize == 32 178 mov w0, w0 // zero upper 32 bits of x0 179 .endif 180 stp x0, x1, [sp, #16 * 0] 181 stp x2, x3, [sp, #16 * 1] 182 stp x4, x5, [sp, #16 * 2] 183 stp x6, x7, [sp, #16 * 3] 184 stp x8, x9, [sp, #16 * 4] 185 stp x10, x11, [sp, #16 * 5] 186 stp x12, x13, [sp, #16 * 6] 187 stp x14, x15, [sp, #16 * 7] 188 stp x16, x17, [sp, #16 * 8] 189 stp x18, x19, [sp, #16 * 9] 190 stp x20, x21, [sp, #16 * 10] 191 stp x22, x23, [sp, #16 * 11] 192 stp x24, x25, [sp, #16 * 12] 193 stp x26, x27, [sp, #16 * 13] 194 stp x28, x29, [sp, #16 * 14] 195 196 .if \el == 0 197 clear_gp_regs 198 mrs x21, sp_el0 199 ldr_this_cpu tsk, __entry_task, x20 200 msr sp_el0, tsk 201 202 /* 203 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 204 * when scheduling. 205 */ 206 ldr x19, [tsk, #TSK_TI_FLAGS] 207 disable_step_tsk x19, x20 208 209 /* Check for asynchronous tag check faults in user space */ 210 check_mte_async_tcf x19, x22 211 apply_ssbd 1, x22, x23 212 213 ptrauth_keys_install_kernel tsk, x20, x22, x23 214 215 scs_load tsk, x20 216 .else 217 add x21, sp, #S_FRAME_SIZE 218 get_current_task tsk 219 /* Save the task's original addr_limit and set USER_DS */ 220 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] 221 str x20, [sp, #S_ORIG_ADDR_LIMIT] 222 mov x20, #USER_DS 223 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 224 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ 225 .endif /* \el == 0 */ 226 mrs x22, elr_el1 227 mrs x23, spsr_el1 228 stp lr, x21, [sp, #S_LR] 229 230 /* 231 * In order to be able to dump the contents of struct pt_regs at the 232 * time the exception was taken (in case we attempt to walk the call 233 * stack later), chain it together with the stack frames. 234 */ 235 .if \el == 0 236 stp xzr, xzr, [sp, #S_STACKFRAME] 237 .else 238 stp x29, x22, [sp, #S_STACKFRAME] 239 .endif 240 add x29, sp, #S_STACKFRAME 241 242#ifdef CONFIG_ARM64_SW_TTBR0_PAN 243alternative_if_not ARM64_HAS_PAN 244 bl __swpan_entry_el\el 245alternative_else_nop_endif 246#endif 247 248 stp x22, x23, [sp, #S_PC] 249 250 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 251 .if \el == 0 252 mov w21, #NO_SYSCALL 253 str w21, [sp, #S_SYSCALLNO] 254 .endif 255 256 /* Save pmr */ 257alternative_if ARM64_HAS_IRQ_PRIO_MASKING 258 mrs_s x20, SYS_ICC_PMR_EL1 259 str x20, [sp, #S_PMR_SAVE] 260alternative_else_nop_endif 261 262 /* Re-enable tag checking (TCO set on exception entry) */ 263#ifdef CONFIG_ARM64_MTE 264alternative_if ARM64_MTE 265 SET_PSTATE_TCO(0) 266alternative_else_nop_endif 267#endif 268 269 /* 270 * Registers that may be useful after this macro is invoked: 271 * 272 * x20 - ICC_PMR_EL1 273 * x21 - aborted SP 274 * x22 - aborted PC 275 * x23 - aborted PSTATE 276 */ 277 .endm 278 279 .macro kernel_exit, el 280 .if \el != 0 281 disable_daif 282 283 /* Restore the task's original addr_limit. */ 284 ldr x20, [sp, #S_ORIG_ADDR_LIMIT] 285 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 286 287 /* No need to restore UAO, it will be restored from SPSR_EL1 */ 288 .endif 289 290 /* Restore pmr */ 291alternative_if ARM64_HAS_IRQ_PRIO_MASKING 292 ldr x20, [sp, #S_PMR_SAVE] 293 msr_s SYS_ICC_PMR_EL1, x20 294 mrs_s x21, SYS_ICC_CTLR_EL1 295 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 296 dsb sy // Ensure priority change is seen by redistributor 297.L__skip_pmr_sync\@: 298alternative_else_nop_endif 299 300 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 301 302#ifdef CONFIG_ARM64_SW_TTBR0_PAN 303alternative_if_not ARM64_HAS_PAN 304 bl __swpan_exit_el\el 305alternative_else_nop_endif 306#endif 307 308 .if \el == 0 309 ldr x23, [sp, #S_SP] // load return stack pointer 310 msr sp_el0, x23 311 tst x22, #PSR_MODE32_BIT // native task? 312 b.eq 3f 313 314#ifdef CONFIG_ARM64_ERRATUM_845719 315alternative_if ARM64_WORKAROUND_845719 316#ifdef CONFIG_PID_IN_CONTEXTIDR 317 mrs x29, contextidr_el1 318 msr contextidr_el1, x29 319#else 320 msr contextidr_el1, xzr 321#endif 322alternative_else_nop_endif 323#endif 3243: 325 scs_save tsk, x0 326 327 /* No kernel C function calls after this as user keys are set. */ 328 ptrauth_keys_install_user tsk, x0, x1, x2 329 330 apply_ssbd 0, x0, x1 331 .endif 332 333 msr elr_el1, x21 // set up the return data 334 msr spsr_el1, x22 335 ldp x0, x1, [sp, #16 * 0] 336 ldp x2, x3, [sp, #16 * 1] 337 ldp x4, x5, [sp, #16 * 2] 338 ldp x6, x7, [sp, #16 * 3] 339 ldp x8, x9, [sp, #16 * 4] 340 ldp x10, x11, [sp, #16 * 5] 341 ldp x12, x13, [sp, #16 * 6] 342 ldp x14, x15, [sp, #16 * 7] 343 ldp x16, x17, [sp, #16 * 8] 344 ldp x18, x19, [sp, #16 * 9] 345 ldp x20, x21, [sp, #16 * 10] 346 ldp x22, x23, [sp, #16 * 11] 347 ldp x24, x25, [sp, #16 * 12] 348 ldp x26, x27, [sp, #16 * 13] 349 ldp x28, x29, [sp, #16 * 14] 350 ldr lr, [sp, #S_LR] 351 add sp, sp, #S_FRAME_SIZE // restore sp 352 353 .if \el == 0 354alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 355#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 356 bne 4f 357 msr far_el1, x30 358 tramp_alias x30, tramp_exit_native 359 br x30 3604: 361 tramp_alias x30, tramp_exit_compat 362 br x30 363#endif 364 .else 365 /* Ensure any device/NC reads complete */ 366 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 367 368 eret 369 .endif 370 sb 371 .endm 372 373#ifdef CONFIG_ARM64_SW_TTBR0_PAN 374 /* 375 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 376 * EL0, there is no need to check the state of TTBR0_EL1 since 377 * accesses are always enabled. 378 * Note that the meaning of this bit differs from the ARMv8.1 PAN 379 * feature as all TTBR0_EL1 accesses are disabled, not just those to 380 * user mappings. 381 */ 382SYM_CODE_START_LOCAL(__swpan_entry_el1) 383 mrs x21, ttbr0_el1 384 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 385 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 386 b.eq 1f // TTBR0 access already disabled 387 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 388SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 389 __uaccess_ttbr0_disable x21 3901: ret 391SYM_CODE_END(__swpan_entry_el1) 392 393 /* 394 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 395 * PAN bit checking. 396 */ 397SYM_CODE_START_LOCAL(__swpan_exit_el1) 398 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 399 __uaccess_ttbr0_enable x0, x1 4001: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 401 ret 402SYM_CODE_END(__swpan_exit_el1) 403 404SYM_CODE_START_LOCAL(__swpan_exit_el0) 405 __uaccess_ttbr0_enable x0, x1 406 /* 407 * Enable errata workarounds only if returning to user. The only 408 * workaround currently required for TTBR0_EL1 changes are for the 409 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 410 * corruption). 411 */ 412 b post_ttbr_update_workaround 413SYM_CODE_END(__swpan_exit_el0) 414#endif 415 416 .macro irq_stack_entry 417 mov x19, sp // preserve the original sp 418#ifdef CONFIG_SHADOW_CALL_STACK 419 mov x24, scs_sp // preserve the original shadow stack 420#endif 421 422 /* 423 * Compare sp with the base of the task stack. 424 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, 425 * and should switch to the irq stack. 426 */ 427 ldr x25, [tsk, TSK_STACK] 428 eor x25, x25, x19 429 and x25, x25, #~(THREAD_SIZE - 1) 430 cbnz x25, 9998f 431 432 ldr_this_cpu x25, irq_stack_ptr, x26 433 mov x26, #IRQ_STACK_SIZE 434 add x26, x25, x26 435 436 /* switch to the irq stack */ 437 mov sp, x26 438 439#ifdef CONFIG_SHADOW_CALL_STACK 440 /* also switch to the irq shadow stack */ 441 adr_this_cpu scs_sp, irq_shadow_call_stack, x26 442#endif 443 4449998: 445 .endm 446 447 /* 448 * The callee-saved regs (x19-x29) should be preserved between 449 * irq_stack_entry and irq_stack_exit, but note that kernel_entry 450 * uses x20-x23 to store data for later use. 451 */ 452 .macro irq_stack_exit 453 mov sp, x19 454#ifdef CONFIG_SHADOW_CALL_STACK 455 mov scs_sp, x24 456#endif 457 .endm 458 459/* GPRs used by entry code */ 460tsk .req x28 // current thread_info 461 462/* 463 * Interrupt handling. 464 */ 465 .macro irq_handler 466 ldr_l x1, handle_arch_irq 467 mov x0, sp 468 irq_stack_entry 469 blr x1 470 irq_stack_exit 471 .endm 472 473#ifdef CONFIG_ARM64_PSEUDO_NMI 474 /* 475 * Set res to 0 if irqs were unmasked in interrupted context. 476 * Otherwise set res to non-0 value. 477 */ 478 .macro test_irqs_unmasked res:req, pmr:req 479alternative_if ARM64_HAS_IRQ_PRIO_MASKING 480 sub \res, \pmr, #GIC_PRIO_IRQON 481alternative_else 482 mov \res, xzr 483alternative_endif 484 .endm 485#endif 486 487 .macro gic_prio_kentry_setup, tmp:req 488#ifdef CONFIG_ARM64_PSEUDO_NMI 489 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 490 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON) 491 msr_s SYS_ICC_PMR_EL1, \tmp 492 alternative_else_nop_endif 493#endif 494 .endm 495 496 .macro gic_prio_irq_setup, pmr:req, tmp:req 497#ifdef CONFIG_ARM64_PSEUDO_NMI 498 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 499 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET 500 msr_s SYS_ICC_PMR_EL1, \tmp 501 alternative_else_nop_endif 502#endif 503 .endm 504 505 .text 506 507/* 508 * Exception vectors. 509 */ 510 .pushsection ".entry.text", "ax" 511 512 .align 11 513SYM_CODE_START(vectors) 514 kernel_ventry 1, sync_invalid // Synchronous EL1t 515 kernel_ventry 1, irq_invalid // IRQ EL1t 516 kernel_ventry 1, fiq_invalid // FIQ EL1t 517 kernel_ventry 1, error_invalid // Error EL1t 518 519 kernel_ventry 1, sync // Synchronous EL1h 520 kernel_ventry 1, irq // IRQ EL1h 521 kernel_ventry 1, fiq_invalid // FIQ EL1h 522 kernel_ventry 1, error // Error EL1h 523 524 kernel_ventry 0, sync // Synchronous 64-bit EL0 525 kernel_ventry 0, irq // IRQ 64-bit EL0 526 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 527 kernel_ventry 0, error // Error 64-bit EL0 528 529#ifdef CONFIG_COMPAT 530 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 531 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 532 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 533 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 534#else 535 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 536 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 537 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 538 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 539#endif 540SYM_CODE_END(vectors) 541 542#ifdef CONFIG_VMAP_STACK 543 /* 544 * We detected an overflow in kernel_ventry, which switched to the 545 * overflow stack. Stash the exception regs, and head to our overflow 546 * handler. 547 */ 548__bad_stack: 549 /* Restore the original x0 value */ 550 mrs x0, tpidrro_el0 551 552 /* 553 * Store the original GPRs to the new stack. The orginal SP (minus 554 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. 555 */ 556 sub sp, sp, #S_FRAME_SIZE 557 kernel_entry 1 558 mrs x0, tpidr_el0 559 add x0, x0, #S_FRAME_SIZE 560 str x0, [sp, #S_SP] 561 562 /* Stash the regs for handle_bad_stack */ 563 mov x0, sp 564 565 /* Time to die */ 566 bl handle_bad_stack 567 ASM_BUG() 568#endif /* CONFIG_VMAP_STACK */ 569 570/* 571 * Invalid mode handlers 572 */ 573 .macro inv_entry, el, reason, regsize = 64 574 kernel_entry \el, \regsize 575 mov x0, sp 576 mov x1, #\reason 577 mrs x2, esr_el1 578 bl bad_mode 579 ASM_BUG() 580 .endm 581 582SYM_CODE_START_LOCAL(el0_sync_invalid) 583 inv_entry 0, BAD_SYNC 584SYM_CODE_END(el0_sync_invalid) 585 586SYM_CODE_START_LOCAL(el0_irq_invalid) 587 inv_entry 0, BAD_IRQ 588SYM_CODE_END(el0_irq_invalid) 589 590SYM_CODE_START_LOCAL(el0_fiq_invalid) 591 inv_entry 0, BAD_FIQ 592SYM_CODE_END(el0_fiq_invalid) 593 594SYM_CODE_START_LOCAL(el0_error_invalid) 595 inv_entry 0, BAD_ERROR 596SYM_CODE_END(el0_error_invalid) 597 598#ifdef CONFIG_COMPAT 599SYM_CODE_START_LOCAL(el0_fiq_invalid_compat) 600 inv_entry 0, BAD_FIQ, 32 601SYM_CODE_END(el0_fiq_invalid_compat) 602#endif 603 604SYM_CODE_START_LOCAL(el1_sync_invalid) 605 inv_entry 1, BAD_SYNC 606SYM_CODE_END(el1_sync_invalid) 607 608SYM_CODE_START_LOCAL(el1_irq_invalid) 609 inv_entry 1, BAD_IRQ 610SYM_CODE_END(el1_irq_invalid) 611 612SYM_CODE_START_LOCAL(el1_fiq_invalid) 613 inv_entry 1, BAD_FIQ 614SYM_CODE_END(el1_fiq_invalid) 615 616SYM_CODE_START_LOCAL(el1_error_invalid) 617 inv_entry 1, BAD_ERROR 618SYM_CODE_END(el1_error_invalid) 619 620/* 621 * EL1 mode handlers. 622 */ 623 .align 6 624SYM_CODE_START_LOCAL_NOALIGN(el1_sync) 625 kernel_entry 1 626 mov x0, sp 627 bl el1_sync_handler 628 kernel_exit 1 629SYM_CODE_END(el1_sync) 630 631 .align 6 632SYM_CODE_START_LOCAL_NOALIGN(el1_irq) 633 kernel_entry 1 634 gic_prio_irq_setup pmr=x20, tmp=x1 635 enable_da_f 636 637 mov x0, sp 638 bl enter_el1_irq_or_nmi 639 640 irq_handler 641 642#ifdef CONFIG_PREEMPTION 643 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count 644alternative_if ARM64_HAS_IRQ_PRIO_MASKING 645 /* 646 * DA_F were cleared at start of handling. If anything is set in DAIF, 647 * we come back from an NMI, so skip preemption 648 */ 649 mrs x0, daif 650 orr x24, x24, x0 651alternative_else_nop_endif 652 cbnz x24, 1f // preempt count != 0 || NMI return path 653 bl arm64_preempt_schedule_irq // irq en/disable is done inside 6541: 655#endif 656 657 mov x0, sp 658 bl exit_el1_irq_or_nmi 659 660 kernel_exit 1 661SYM_CODE_END(el1_irq) 662 663/* 664 * EL0 mode handlers. 665 */ 666 .align 6 667SYM_CODE_START_LOCAL_NOALIGN(el0_sync) 668 kernel_entry 0 669 mov x0, sp 670 bl el0_sync_handler 671 b ret_to_user 672SYM_CODE_END(el0_sync) 673 674#ifdef CONFIG_COMPAT 675 .align 6 676SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat) 677 kernel_entry 0, 32 678 mov x0, sp 679 bl el0_sync_compat_handler 680 b ret_to_user 681SYM_CODE_END(el0_sync_compat) 682 683 .align 6 684SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) 685 kernel_entry 0, 32 686 b el0_irq_naked 687SYM_CODE_END(el0_irq_compat) 688 689SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) 690 kernel_entry 0, 32 691 b el0_error_naked 692SYM_CODE_END(el0_error_compat) 693#endif 694 695 .align 6 696SYM_CODE_START_LOCAL_NOALIGN(el0_irq) 697 kernel_entry 0 698el0_irq_naked: 699 gic_prio_irq_setup pmr=x20, tmp=x0 700 user_exit_irqoff 701 enable_da_f 702 703 tbz x22, #55, 1f 704 bl do_el0_irq_bp_hardening 7051: 706 irq_handler 707 708 b ret_to_user 709SYM_CODE_END(el0_irq) 710 711SYM_CODE_START_LOCAL(el1_error) 712 kernel_entry 1 713 mrs x1, esr_el1 714 gic_prio_kentry_setup tmp=x2 715 enable_dbg 716 mov x0, sp 717 bl do_serror 718 kernel_exit 1 719SYM_CODE_END(el1_error) 720 721SYM_CODE_START_LOCAL(el0_error) 722 kernel_entry 0 723el0_error_naked: 724 mrs x25, esr_el1 725 gic_prio_kentry_setup tmp=x2 726 user_exit_irqoff 727 enable_dbg 728 mov x0, sp 729 mov x1, x25 730 bl do_serror 731 enable_da_f 732 b ret_to_user 733SYM_CODE_END(el0_error) 734 735/* 736 * "slow" syscall return path. 737 */ 738SYM_CODE_START_LOCAL(ret_to_user) 739 disable_daif 740 gic_prio_kentry_setup tmp=x3 741#ifdef CONFIG_TRACE_IRQFLAGS 742 bl trace_hardirqs_off 743#endif 744 ldr x19, [tsk, #TSK_TI_FLAGS] 745 and x2, x19, #_TIF_WORK_MASK 746 cbnz x2, work_pending 747finish_ret_to_user: 748 user_enter_irqoff 749 /* Ignore asynchronous tag check faults in the uaccess routines */ 750 clear_mte_async_tcf 751 enable_step_tsk x19, x2 752#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 753 bl stackleak_erase 754#endif 755 kernel_exit 0 756 757/* 758 * Ok, we need to do extra processing, enter the slow path. 759 */ 760work_pending: 761 mov x0, sp // 'regs' 762 mov x1, x19 763 bl do_notify_resume 764 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 765 b finish_ret_to_user 766SYM_CODE_END(ret_to_user) 767 768 .popsection // .entry.text 769 770#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 771/* 772 * Exception vectors trampoline. 773 */ 774 .pushsection ".entry.tramp.text", "ax" 775 776 .macro tramp_map_kernel, tmp 777 mrs \tmp, ttbr1_el1 778 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 779 bic \tmp, \tmp, #USER_ASID_FLAG 780 msr ttbr1_el1, \tmp 781#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 782alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 783 /* ASID already in \tmp[63:48] */ 784 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 785 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 786 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 787 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 788 isb 789 tlbi vae1, \tmp 790 dsb nsh 791alternative_else_nop_endif 792#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 793 .endm 794 795 .macro tramp_unmap_kernel, tmp 796 mrs \tmp, ttbr1_el1 797 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 798 orr \tmp, \tmp, #USER_ASID_FLAG 799 msr ttbr1_el1, \tmp 800 /* 801 * We avoid running the post_ttbr_update_workaround here because 802 * it's only needed by Cavium ThunderX, which requires KPTI to be 803 * disabled. 804 */ 805 .endm 806 807 .macro tramp_ventry, regsize = 64 808 .align 7 8091: 810 .if \regsize == 64 811 msr tpidrro_el0, x30 // Restored in kernel_ventry 812 .endif 813 /* 814 * Defend against branch aliasing attacks by pushing a dummy 815 * entry onto the return stack and using a RET instruction to 816 * enter the full-fat kernel vectors. 817 */ 818 bl 2f 819 b . 8202: 821 tramp_map_kernel x30 822#ifdef CONFIG_RANDOMIZE_BASE 823 adr x30, tramp_vectors + PAGE_SIZE 824alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 825 ldr x30, [x30] 826#else 827 ldr x30, =vectors 828#endif 829alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 830 prfm plil1strm, [x30, #(1b - tramp_vectors)] 831alternative_else_nop_endif 832 msr vbar_el1, x30 833 add x30, x30, #(1b - tramp_vectors) 834 isb 835 ret 836 .endm 837 838 .macro tramp_exit, regsize = 64 839 adr x30, tramp_vectors 840 msr vbar_el1, x30 841 tramp_unmap_kernel x30 842 .if \regsize == 64 843 mrs x30, far_el1 844 .endif 845 eret 846 sb 847 .endm 848 849 .align 11 850SYM_CODE_START_NOALIGN(tramp_vectors) 851 .space 0x400 852 853 tramp_ventry 854 tramp_ventry 855 tramp_ventry 856 tramp_ventry 857 858 tramp_ventry 32 859 tramp_ventry 32 860 tramp_ventry 32 861 tramp_ventry 32 862SYM_CODE_END(tramp_vectors) 863 864SYM_CODE_START(tramp_exit_native) 865 tramp_exit 866SYM_CODE_END(tramp_exit_native) 867 868SYM_CODE_START(tramp_exit_compat) 869 tramp_exit 32 870SYM_CODE_END(tramp_exit_compat) 871 872 .ltorg 873 .popsection // .entry.tramp.text 874#ifdef CONFIG_RANDOMIZE_BASE 875 .pushsection ".rodata", "a" 876 .align PAGE_SHIFT 877SYM_DATA_START(__entry_tramp_data_start) 878 .quad vectors 879SYM_DATA_END(__entry_tramp_data_start) 880 .popsection // .rodata 881#endif /* CONFIG_RANDOMIZE_BASE */ 882#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 883 884/* 885 * Register switch for AArch64. The callee-saved registers need to be saved 886 * and restored. On entry: 887 * x0 = previous task_struct (must be preserved across the switch) 888 * x1 = next task_struct 889 * Previous and next are guaranteed not to be the same. 890 * 891 */ 892SYM_FUNC_START(cpu_switch_to) 893 mov x10, #THREAD_CPU_CONTEXT 894 add x8, x0, x10 895 mov x9, sp 896 stp x19, x20, [x8], #16 // store callee-saved registers 897 stp x21, x22, [x8], #16 898 stp x23, x24, [x8], #16 899 stp x25, x26, [x8], #16 900 stp x27, x28, [x8], #16 901 stp x29, x9, [x8], #16 902 str lr, [x8] 903 add x8, x1, x10 904 ldp x19, x20, [x8], #16 // restore callee-saved registers 905 ldp x21, x22, [x8], #16 906 ldp x23, x24, [x8], #16 907 ldp x25, x26, [x8], #16 908 ldp x27, x28, [x8], #16 909 ldp x29, x9, [x8], #16 910 ldr lr, [x8] 911 mov sp, x9 912 msr sp_el0, x1 913 ptrauth_keys_install_kernel x1, x8, x9, x10 914 scs_save x0, x8 915 scs_load x1, x8 916 ret 917SYM_FUNC_END(cpu_switch_to) 918NOKPROBE(cpu_switch_to) 919 920/* 921 * This is how we return from a fork. 922 */ 923SYM_CODE_START(ret_from_fork) 924 bl schedule_tail 925 cbz x19, 1f // not a kernel thread 926 mov x0, x20 927 blr x19 9281: get_current_task tsk 929 b ret_to_user 930SYM_CODE_END(ret_from_fork) 931NOKPROBE(ret_from_fork) 932 933#ifdef CONFIG_ARM_SDE_INTERFACE 934 935#include <asm/sdei.h> 936#include <uapi/linux/arm_sdei.h> 937 938.macro sdei_handler_exit exit_mode 939 /* On success, this call never returns... */ 940 cmp \exit_mode, #SDEI_EXIT_SMC 941 b.ne 99f 942 smc #0 943 b . 94499: hvc #0 945 b . 946.endm 947 948#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 949/* 950 * The regular SDEI entry point may have been unmapped along with the rest of 951 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 952 * argument accessible. 953 * 954 * This clobbers x4, __sdei_handler() will restore this from firmware's 955 * copy. 956 */ 957.ltorg 958.pushsection ".entry.tramp.text", "ax" 959SYM_CODE_START(__sdei_asm_entry_trampoline) 960 mrs x4, ttbr1_el1 961 tbz x4, #USER_ASID_BIT, 1f 962 963 tramp_map_kernel tmp=x4 964 isb 965 mov x4, xzr 966 967 /* 968 * Use reg->interrupted_regs.addr_limit to remember whether to unmap 969 * the kernel on exit. 970 */ 9711: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 972 973#ifdef CONFIG_RANDOMIZE_BASE 974 adr x4, tramp_vectors + PAGE_SIZE 975 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler 976 ldr x4, [x4] 977#else 978 ldr x4, =__sdei_asm_handler 979#endif 980 br x4 981SYM_CODE_END(__sdei_asm_entry_trampoline) 982NOKPROBE(__sdei_asm_entry_trampoline) 983 984/* 985 * Make the exit call and restore the original ttbr1_el1 986 * 987 * x0 & x1: setup for the exit API call 988 * x2: exit_mode 989 * x4: struct sdei_registered_event argument from registration time. 990 */ 991SYM_CODE_START(__sdei_asm_exit_trampoline) 992 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 993 cbnz x4, 1f 994 995 tramp_unmap_kernel tmp=x4 996 9971: sdei_handler_exit exit_mode=x2 998SYM_CODE_END(__sdei_asm_exit_trampoline) 999NOKPROBE(__sdei_asm_exit_trampoline) 1000 .ltorg 1001.popsection // .entry.tramp.text 1002#ifdef CONFIG_RANDOMIZE_BASE 1003.pushsection ".rodata", "a" 1004SYM_DATA_START(__sdei_asm_trampoline_next_handler) 1005 .quad __sdei_asm_handler 1006SYM_DATA_END(__sdei_asm_trampoline_next_handler) 1007.popsection // .rodata 1008#endif /* CONFIG_RANDOMIZE_BASE */ 1009#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1010 1011/* 1012 * Software Delegated Exception entry point. 1013 * 1014 * x0: Event number 1015 * x1: struct sdei_registered_event argument from registration time. 1016 * x2: interrupted PC 1017 * x3: interrupted PSTATE 1018 * x4: maybe clobbered by the trampoline 1019 * 1020 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 1021 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 1022 * want them. 1023 */ 1024SYM_CODE_START(__sdei_asm_handler) 1025 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 1026 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 1027 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 1028 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 1029 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 1030 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 1031 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 1032 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 1033 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 1034 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 1035 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 1036 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 1037 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1038 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1039 mov x4, sp 1040 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1041 1042 mov x19, x1 1043 1044#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1045 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1046#endif 1047 1048#ifdef CONFIG_VMAP_STACK 1049 /* 1050 * entry.S may have been using sp as a scratch register, find whether 1051 * this is a normal or critical event and switch to the appropriate 1052 * stack for this CPU. 1053 */ 1054 cbnz w4, 1f 1055 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1056 b 2f 10571: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10582: mov x6, #SDEI_STACK_SIZE 1059 add x5, x5, x6 1060 mov sp, x5 1061#endif 1062 1063#ifdef CONFIG_SHADOW_CALL_STACK 1064 /* Use a separate shadow call stack for normal and critical events */ 1065 cbnz w4, 3f 1066 adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6 1067 b 4f 10683: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6 10694: 1070#endif 1071 1072 /* 1073 * We may have interrupted userspace, or a guest, or exit-from or 1074 * return-to either of these. We can't trust sp_el0, restore it. 1075 */ 1076 mrs x28, sp_el0 1077 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1078 msr sp_el0, x0 1079 1080 /* If we interrupted the kernel point to the previous stack/frame. */ 1081 and x0, x3, #0xc 1082 mrs x1, CurrentEL 1083 cmp x0, x1 1084 csel x29, x29, xzr, eq // fp, or zero 1085 csel x4, x2, xzr, eq // elr, or zero 1086 1087 stp x29, x4, [sp, #-16]! 1088 mov x29, sp 1089 1090 add x0, x19, #SDEI_EVENT_INTREGS 1091 mov x1, x19 1092 bl __sdei_handler 1093 1094 msr sp_el0, x28 1095 /* restore regs >x17 that we clobbered */ 1096 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1097 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1098 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1099 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1100 mov sp, x1 1101 1102 mov x1, x0 // address to complete_and_resume 1103 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1104 cmp x0, #1 1105 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1106 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1107 csel x0, x2, x3, ls 1108 1109 ldr_l x2, sdei_exit_mode 1110 1111alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1112 sdei_handler_exit exit_mode=x2 1113alternative_else_nop_endif 1114 1115#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1116 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1117 br x5 1118#endif 1119SYM_CODE_END(__sdei_asm_handler) 1120NOKPROBE(__sdei_asm_handler) 1121#endif /* CONFIG_ARM_SDE_INTERFACE */ 1122