1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32/* 33 * Context tracking subsystem. Used to instrument transitions 34 * between user and kernel mode. 35 */ 36 .macro ct_user_exit_irqoff 37#ifdef CONFIG_CONTEXT_TRACKING 38 bl enter_from_user_mode 39#endif 40 .endm 41 42 .macro ct_user_enter 43#ifdef CONFIG_CONTEXT_TRACKING 44 bl context_tracking_user_enter 45#endif 46 .endm 47 48 .macro clear_gp_regs 49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 50 mov x\n, xzr 51 .endr 52 .endm 53 54/* 55 * Bad Abort numbers 56 *----------------- 57 */ 58#define BAD_SYNC 0 59#define BAD_IRQ 1 60#define BAD_FIQ 2 61#define BAD_ERROR 3 62 63 .macro kernel_ventry, el, label, regsize = 64 64 .align 7 65#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 66 .if \el == 0 67alternative_if ARM64_UNMAP_KERNEL_AT_EL0 68 .if \regsize == 64 69 mrs x30, tpidrro_el0 70 msr tpidrro_el0, xzr 71 .else 72 mov x30, xzr 73 .endif 74alternative_else_nop_endif 75 .endif 76#endif 77 78 sub sp, sp, #S_FRAME_SIZE 79#ifdef CONFIG_VMAP_STACK 80 /* 81 * Test whether the SP has overflowed, without corrupting a GPR. 82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 83 * should always be zero. 84 */ 85 add sp, sp, x0 // sp' = sp + x0 86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 87 tbnz x0, #THREAD_SHIFT, 0f 88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 90 b el\()\el\()_\label 91 920: 93 /* 94 * Either we've just detected an overflow, or we've taken an exception 95 * while on the overflow stack. Either way, we won't return to 96 * userspace, and can clobber EL0 registers to free up GPRs. 97 */ 98 99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ 100 msr tpidr_el0, x0 101 102 /* Recover the original x0 value and stash it in tpidrro_el0 */ 103 sub x0, sp, x0 104 msr tpidrro_el0, x0 105 106 /* Switch to the overflow stack */ 107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 108 109 /* 110 * Check whether we were already on the overflow stack. This may happen 111 * after panic() re-enables interrupts. 112 */ 113 mrs x0, tpidr_el0 // sp of interrupted context 114 sub x0, sp, x0 // delta with top of overflow stack 115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 116 b.ne __bad_stack // no? -> bad stack pointer 117 118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 119 sub sp, sp, x0 120 mrs x0, tpidrro_el0 121#endif 122 b el\()\el\()_\label 123 .endm 124 125 .macro tramp_alias, dst, sym 126 mov_q \dst, TRAMP_VALIAS 127 add \dst, \dst, #(\sym - .entry.tramp.text) 128 .endm 129 130 /* 131 * This macro corrupts x0-x3. It is the caller's duty to save/restore 132 * them if required. 133 */ 134 .macro apply_ssbd, state, tmp1, tmp2 135alternative_cb spectre_v4_patch_fw_mitigation_enable 136 b .L__asm_ssbd_skip\@ // Patched to NOP 137alternative_cb_end 138 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 139 cbz \tmp2, .L__asm_ssbd_skip\@ 140 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 141 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 142 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 143 mov w1, #\state 144alternative_cb spectre_v4_patch_fw_mitigation_conduit 145 nop // Patched to SMC/HVC #0 146alternative_cb_end 147.L__asm_ssbd_skip\@: 148 .endm 149 150 /* Check for MTE asynchronous tag check faults */ 151 .macro check_mte_async_tcf, flgs, tmp 152#ifdef CONFIG_ARM64_MTE 153alternative_if_not ARM64_MTE 154 b 1f 155alternative_else_nop_endif 156 mrs_s \tmp, SYS_TFSRE0_EL1 157 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 158 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 159 orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT 160 str \flgs, [tsk, #TSK_TI_FLAGS] 161 msr_s SYS_TFSRE0_EL1, xzr 1621: 163#endif 164 .endm 165 166 /* Clear the MTE asynchronous tag check faults */ 167 .macro clear_mte_async_tcf 168#ifdef CONFIG_ARM64_MTE 169alternative_if ARM64_MTE 170 dsb ish 171 msr_s SYS_TFSRE0_EL1, xzr 172alternative_else_nop_endif 173#endif 174 .endm 175 176 .macro kernel_entry, el, regsize = 64 177 .if \regsize == 32 178 mov w0, w0 // zero upper 32 bits of x0 179 .endif 180 stp x0, x1, [sp, #16 * 0] 181 stp x2, x3, [sp, #16 * 1] 182 stp x4, x5, [sp, #16 * 2] 183 stp x6, x7, [sp, #16 * 3] 184 stp x8, x9, [sp, #16 * 4] 185 stp x10, x11, [sp, #16 * 5] 186 stp x12, x13, [sp, #16 * 6] 187 stp x14, x15, [sp, #16 * 7] 188 stp x16, x17, [sp, #16 * 8] 189 stp x18, x19, [sp, #16 * 9] 190 stp x20, x21, [sp, #16 * 10] 191 stp x22, x23, [sp, #16 * 11] 192 stp x24, x25, [sp, #16 * 12] 193 stp x26, x27, [sp, #16 * 13] 194 stp x28, x29, [sp, #16 * 14] 195 196 .if \el == 0 197 clear_gp_regs 198 mrs x21, sp_el0 199 ldr_this_cpu tsk, __entry_task, x20 200 msr sp_el0, tsk 201 202 /* 203 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 204 * when scheduling. 205 */ 206 ldr x19, [tsk, #TSK_TI_FLAGS] 207 disable_step_tsk x19, x20 208 209 /* Check for asynchronous tag check faults in user space */ 210 check_mte_async_tcf x19, x22 211 apply_ssbd 1, x22, x23 212 213 ptrauth_keys_install_kernel tsk, x20, x22, x23 214 215 scs_load tsk, x20 216 .else 217 add x21, sp, #S_FRAME_SIZE 218 get_current_task tsk 219 /* Save the task's original addr_limit and set USER_DS */ 220 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] 221 str x20, [sp, #S_ORIG_ADDR_LIMIT] 222 mov x20, #USER_DS 223 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 224 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ 225 .endif /* \el == 0 */ 226 mrs x22, elr_el1 227 mrs x23, spsr_el1 228 stp lr, x21, [sp, #S_LR] 229 230 /* 231 * In order to be able to dump the contents of struct pt_regs at the 232 * time the exception was taken (in case we attempt to walk the call 233 * stack later), chain it together with the stack frames. 234 */ 235 .if \el == 0 236 stp xzr, xzr, [sp, #S_STACKFRAME] 237 .else 238 stp x29, x22, [sp, #S_STACKFRAME] 239 .endif 240 add x29, sp, #S_STACKFRAME 241 242#ifdef CONFIG_ARM64_SW_TTBR0_PAN 243alternative_if_not ARM64_HAS_PAN 244 bl __swpan_entry_el\el 245alternative_else_nop_endif 246#endif 247 248 stp x22, x23, [sp, #S_PC] 249 250 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 251 .if \el == 0 252 mov w21, #NO_SYSCALL 253 str w21, [sp, #S_SYSCALLNO] 254 .endif 255 256 /* Save pmr */ 257alternative_if ARM64_HAS_IRQ_PRIO_MASKING 258 mrs_s x20, SYS_ICC_PMR_EL1 259 str x20, [sp, #S_PMR_SAVE] 260alternative_else_nop_endif 261 262 /* Re-enable tag checking (TCO set on exception entry) */ 263#ifdef CONFIG_ARM64_MTE 264alternative_if ARM64_MTE 265 SET_PSTATE_TCO(0) 266alternative_else_nop_endif 267#endif 268 269 /* 270 * Registers that may be useful after this macro is invoked: 271 * 272 * x20 - ICC_PMR_EL1 273 * x21 - aborted SP 274 * x22 - aborted PC 275 * x23 - aborted PSTATE 276 */ 277 .endm 278 279 .macro kernel_exit, el 280 .if \el != 0 281 disable_daif 282 283 /* Restore the task's original addr_limit. */ 284 ldr x20, [sp, #S_ORIG_ADDR_LIMIT] 285 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 286 287 /* No need to restore UAO, it will be restored from SPSR_EL1 */ 288 .endif 289 290 /* Restore pmr */ 291alternative_if ARM64_HAS_IRQ_PRIO_MASKING 292 ldr x20, [sp, #S_PMR_SAVE] 293 msr_s SYS_ICC_PMR_EL1, x20 294 mrs_s x21, SYS_ICC_CTLR_EL1 295 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 296 dsb sy // Ensure priority change is seen by redistributor 297.L__skip_pmr_sync\@: 298alternative_else_nop_endif 299 300 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 301 .if \el == 0 302 ct_user_enter 303 .endif 304 305#ifdef CONFIG_ARM64_SW_TTBR0_PAN 306alternative_if_not ARM64_HAS_PAN 307 bl __swpan_exit_el\el 308alternative_else_nop_endif 309#endif 310 311 .if \el == 0 312 ldr x23, [sp, #S_SP] // load return stack pointer 313 msr sp_el0, x23 314 tst x22, #PSR_MODE32_BIT // native task? 315 b.eq 3f 316 317#ifdef CONFIG_ARM64_ERRATUM_845719 318alternative_if ARM64_WORKAROUND_845719 319#ifdef CONFIG_PID_IN_CONTEXTIDR 320 mrs x29, contextidr_el1 321 msr contextidr_el1, x29 322#else 323 msr contextidr_el1, xzr 324#endif 325alternative_else_nop_endif 326#endif 3273: 328 scs_save tsk, x0 329 330 /* No kernel C function calls after this as user keys are set. */ 331 ptrauth_keys_install_user tsk, x0, x1, x2 332 333 apply_ssbd 0, x0, x1 334 .endif 335 336 msr elr_el1, x21 // set up the return data 337 msr spsr_el1, x22 338 ldp x0, x1, [sp, #16 * 0] 339 ldp x2, x3, [sp, #16 * 1] 340 ldp x4, x5, [sp, #16 * 2] 341 ldp x6, x7, [sp, #16 * 3] 342 ldp x8, x9, [sp, #16 * 4] 343 ldp x10, x11, [sp, #16 * 5] 344 ldp x12, x13, [sp, #16 * 6] 345 ldp x14, x15, [sp, #16 * 7] 346 ldp x16, x17, [sp, #16 * 8] 347 ldp x18, x19, [sp, #16 * 9] 348 ldp x20, x21, [sp, #16 * 10] 349 ldp x22, x23, [sp, #16 * 11] 350 ldp x24, x25, [sp, #16 * 12] 351 ldp x26, x27, [sp, #16 * 13] 352 ldp x28, x29, [sp, #16 * 14] 353 ldr lr, [sp, #S_LR] 354 add sp, sp, #S_FRAME_SIZE // restore sp 355 356 .if \el == 0 357alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 358#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 359 bne 4f 360 msr far_el1, x30 361 tramp_alias x30, tramp_exit_native 362 br x30 3634: 364 tramp_alias x30, tramp_exit_compat 365 br x30 366#endif 367 .else 368 /* Ensure any device/NC reads complete */ 369 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 370 371 eret 372 .endif 373 sb 374 .endm 375 376#ifdef CONFIG_ARM64_SW_TTBR0_PAN 377 /* 378 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 379 * EL0, there is no need to check the state of TTBR0_EL1 since 380 * accesses are always enabled. 381 * Note that the meaning of this bit differs from the ARMv8.1 PAN 382 * feature as all TTBR0_EL1 accesses are disabled, not just those to 383 * user mappings. 384 */ 385SYM_CODE_START_LOCAL(__swpan_entry_el1) 386 mrs x21, ttbr0_el1 387 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 388 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 389 b.eq 1f // TTBR0 access already disabled 390 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 391SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 392 __uaccess_ttbr0_disable x21 3931: ret 394SYM_CODE_END(__swpan_entry_el1) 395 396 /* 397 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 398 * PAN bit checking. 399 */ 400SYM_CODE_START_LOCAL(__swpan_exit_el1) 401 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 402 __uaccess_ttbr0_enable x0, x1 4031: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 404 ret 405SYM_CODE_END(__swpan_exit_el1) 406 407SYM_CODE_START_LOCAL(__swpan_exit_el0) 408 __uaccess_ttbr0_enable x0, x1 409 /* 410 * Enable errata workarounds only if returning to user. The only 411 * workaround currently required for TTBR0_EL1 changes are for the 412 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 413 * corruption). 414 */ 415 b post_ttbr_update_workaround 416SYM_CODE_END(__swpan_exit_el0) 417#endif 418 419 .macro irq_stack_entry 420 mov x19, sp // preserve the original sp 421#ifdef CONFIG_SHADOW_CALL_STACK 422 mov x24, scs_sp // preserve the original shadow stack 423#endif 424 425 /* 426 * Compare sp with the base of the task stack. 427 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, 428 * and should switch to the irq stack. 429 */ 430 ldr x25, [tsk, TSK_STACK] 431 eor x25, x25, x19 432 and x25, x25, #~(THREAD_SIZE - 1) 433 cbnz x25, 9998f 434 435 ldr_this_cpu x25, irq_stack_ptr, x26 436 mov x26, #IRQ_STACK_SIZE 437 add x26, x25, x26 438 439 /* switch to the irq stack */ 440 mov sp, x26 441 442#ifdef CONFIG_SHADOW_CALL_STACK 443 /* also switch to the irq shadow stack */ 444 adr_this_cpu scs_sp, irq_shadow_call_stack, x26 445#endif 446 4479998: 448 .endm 449 450 /* 451 * The callee-saved regs (x19-x29) should be preserved between 452 * irq_stack_entry and irq_stack_exit, but note that kernel_entry 453 * uses x20-x23 to store data for later use. 454 */ 455 .macro irq_stack_exit 456 mov sp, x19 457#ifdef CONFIG_SHADOW_CALL_STACK 458 mov scs_sp, x24 459#endif 460 .endm 461 462/* GPRs used by entry code */ 463tsk .req x28 // current thread_info 464 465/* 466 * Interrupt handling. 467 */ 468 .macro irq_handler 469 ldr_l x1, handle_arch_irq 470 mov x0, sp 471 irq_stack_entry 472 blr x1 473 irq_stack_exit 474 .endm 475 476#ifdef CONFIG_ARM64_PSEUDO_NMI 477 /* 478 * Set res to 0 if irqs were unmasked in interrupted context. 479 * Otherwise set res to non-0 value. 480 */ 481 .macro test_irqs_unmasked res:req, pmr:req 482alternative_if ARM64_HAS_IRQ_PRIO_MASKING 483 sub \res, \pmr, #GIC_PRIO_IRQON 484alternative_else 485 mov \res, xzr 486alternative_endif 487 .endm 488#endif 489 490 .macro gic_prio_kentry_setup, tmp:req 491#ifdef CONFIG_ARM64_PSEUDO_NMI 492 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 493 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON) 494 msr_s SYS_ICC_PMR_EL1, \tmp 495 alternative_else_nop_endif 496#endif 497 .endm 498 499 .macro gic_prio_irq_setup, pmr:req, tmp:req 500#ifdef CONFIG_ARM64_PSEUDO_NMI 501 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 502 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET 503 msr_s SYS_ICC_PMR_EL1, \tmp 504 alternative_else_nop_endif 505#endif 506 .endm 507 508 .text 509 510/* 511 * Exception vectors. 512 */ 513 .pushsection ".entry.text", "ax" 514 515 .align 11 516SYM_CODE_START(vectors) 517 kernel_ventry 1, sync_invalid // Synchronous EL1t 518 kernel_ventry 1, irq_invalid // IRQ EL1t 519 kernel_ventry 1, fiq_invalid // FIQ EL1t 520 kernel_ventry 1, error_invalid // Error EL1t 521 522 kernel_ventry 1, sync // Synchronous EL1h 523 kernel_ventry 1, irq // IRQ EL1h 524 kernel_ventry 1, fiq_invalid // FIQ EL1h 525 kernel_ventry 1, error // Error EL1h 526 527 kernel_ventry 0, sync // Synchronous 64-bit EL0 528 kernel_ventry 0, irq // IRQ 64-bit EL0 529 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 530 kernel_ventry 0, error // Error 64-bit EL0 531 532#ifdef CONFIG_COMPAT 533 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 534 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 535 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 536 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 537#else 538 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 539 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 540 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 541 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 542#endif 543SYM_CODE_END(vectors) 544 545#ifdef CONFIG_VMAP_STACK 546 /* 547 * We detected an overflow in kernel_ventry, which switched to the 548 * overflow stack. Stash the exception regs, and head to our overflow 549 * handler. 550 */ 551__bad_stack: 552 /* Restore the original x0 value */ 553 mrs x0, tpidrro_el0 554 555 /* 556 * Store the original GPRs to the new stack. The orginal SP (minus 557 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. 558 */ 559 sub sp, sp, #S_FRAME_SIZE 560 kernel_entry 1 561 mrs x0, tpidr_el0 562 add x0, x0, #S_FRAME_SIZE 563 str x0, [sp, #S_SP] 564 565 /* Stash the regs for handle_bad_stack */ 566 mov x0, sp 567 568 /* Time to die */ 569 bl handle_bad_stack 570 ASM_BUG() 571#endif /* CONFIG_VMAP_STACK */ 572 573/* 574 * Invalid mode handlers 575 */ 576 .macro inv_entry, el, reason, regsize = 64 577 kernel_entry \el, \regsize 578 mov x0, sp 579 mov x1, #\reason 580 mrs x2, esr_el1 581 bl bad_mode 582 ASM_BUG() 583 .endm 584 585SYM_CODE_START_LOCAL(el0_sync_invalid) 586 inv_entry 0, BAD_SYNC 587SYM_CODE_END(el0_sync_invalid) 588 589SYM_CODE_START_LOCAL(el0_irq_invalid) 590 inv_entry 0, BAD_IRQ 591SYM_CODE_END(el0_irq_invalid) 592 593SYM_CODE_START_LOCAL(el0_fiq_invalid) 594 inv_entry 0, BAD_FIQ 595SYM_CODE_END(el0_fiq_invalid) 596 597SYM_CODE_START_LOCAL(el0_error_invalid) 598 inv_entry 0, BAD_ERROR 599SYM_CODE_END(el0_error_invalid) 600 601#ifdef CONFIG_COMPAT 602SYM_CODE_START_LOCAL(el0_fiq_invalid_compat) 603 inv_entry 0, BAD_FIQ, 32 604SYM_CODE_END(el0_fiq_invalid_compat) 605#endif 606 607SYM_CODE_START_LOCAL(el1_sync_invalid) 608 inv_entry 1, BAD_SYNC 609SYM_CODE_END(el1_sync_invalid) 610 611SYM_CODE_START_LOCAL(el1_irq_invalid) 612 inv_entry 1, BAD_IRQ 613SYM_CODE_END(el1_irq_invalid) 614 615SYM_CODE_START_LOCAL(el1_fiq_invalid) 616 inv_entry 1, BAD_FIQ 617SYM_CODE_END(el1_fiq_invalid) 618 619SYM_CODE_START_LOCAL(el1_error_invalid) 620 inv_entry 1, BAD_ERROR 621SYM_CODE_END(el1_error_invalid) 622 623/* 624 * EL1 mode handlers. 625 */ 626 .align 6 627SYM_CODE_START_LOCAL_NOALIGN(el1_sync) 628 kernel_entry 1 629 mov x0, sp 630 bl el1_sync_handler 631 kernel_exit 1 632SYM_CODE_END(el1_sync) 633 634 .align 6 635SYM_CODE_START_LOCAL_NOALIGN(el1_irq) 636 kernel_entry 1 637 gic_prio_irq_setup pmr=x20, tmp=x1 638 enable_da_f 639 640#ifdef CONFIG_ARM64_PSEUDO_NMI 641 test_irqs_unmasked res=x0, pmr=x20 642 cbz x0, 1f 643 bl asm_nmi_enter 6441: 645#endif 646 647#ifdef CONFIG_TRACE_IRQFLAGS 648 bl trace_hardirqs_off 649#endif 650 651 irq_handler 652 653#ifdef CONFIG_PREEMPTION 654 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count 655alternative_if ARM64_HAS_IRQ_PRIO_MASKING 656 /* 657 * DA_F were cleared at start of handling. If anything is set in DAIF, 658 * we come back from an NMI, so skip preemption 659 */ 660 mrs x0, daif 661 orr x24, x24, x0 662alternative_else_nop_endif 663 cbnz x24, 1f // preempt count != 0 || NMI return path 664 bl arm64_preempt_schedule_irq // irq en/disable is done inside 6651: 666#endif 667 668#ifdef CONFIG_ARM64_PSEUDO_NMI 669 /* 670 * When using IRQ priority masking, we can get spurious interrupts while 671 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a 672 * section with interrupts disabled. Skip tracing in those cases. 673 */ 674 test_irqs_unmasked res=x0, pmr=x20 675 cbz x0, 1f 676 bl asm_nmi_exit 6771: 678#endif 679 680#ifdef CONFIG_TRACE_IRQFLAGS 681#ifdef CONFIG_ARM64_PSEUDO_NMI 682 test_irqs_unmasked res=x0, pmr=x20 683 cbnz x0, 1f 684#endif 685 bl trace_hardirqs_on 6861: 687#endif 688 689 kernel_exit 1 690SYM_CODE_END(el1_irq) 691 692/* 693 * EL0 mode handlers. 694 */ 695 .align 6 696SYM_CODE_START_LOCAL_NOALIGN(el0_sync) 697 kernel_entry 0 698 mov x0, sp 699 bl el0_sync_handler 700 b ret_to_user 701SYM_CODE_END(el0_sync) 702 703#ifdef CONFIG_COMPAT 704 .align 6 705SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat) 706 kernel_entry 0, 32 707 mov x0, sp 708 bl el0_sync_compat_handler 709 b ret_to_user 710SYM_CODE_END(el0_sync_compat) 711 712 .align 6 713SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) 714 kernel_entry 0, 32 715 b el0_irq_naked 716SYM_CODE_END(el0_irq_compat) 717 718SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) 719 kernel_entry 0, 32 720 b el0_error_naked 721SYM_CODE_END(el0_error_compat) 722#endif 723 724 .align 6 725SYM_CODE_START_LOCAL_NOALIGN(el0_irq) 726 kernel_entry 0 727el0_irq_naked: 728 gic_prio_irq_setup pmr=x20, tmp=x0 729 ct_user_exit_irqoff 730 enable_da_f 731 732#ifdef CONFIG_TRACE_IRQFLAGS 733 bl trace_hardirqs_off 734#endif 735 736 tbz x22, #55, 1f 737 bl do_el0_irq_bp_hardening 7381: 739 irq_handler 740 741#ifdef CONFIG_TRACE_IRQFLAGS 742 bl trace_hardirqs_on 743#endif 744 b ret_to_user 745SYM_CODE_END(el0_irq) 746 747SYM_CODE_START_LOCAL(el1_error) 748 kernel_entry 1 749 mrs x1, esr_el1 750 gic_prio_kentry_setup tmp=x2 751 enable_dbg 752 mov x0, sp 753 bl do_serror 754 kernel_exit 1 755SYM_CODE_END(el1_error) 756 757SYM_CODE_START_LOCAL(el0_error) 758 kernel_entry 0 759el0_error_naked: 760 mrs x25, esr_el1 761 gic_prio_kentry_setup tmp=x2 762 ct_user_exit_irqoff 763 enable_dbg 764 mov x0, sp 765 mov x1, x25 766 bl do_serror 767 enable_da_f 768 b ret_to_user 769SYM_CODE_END(el0_error) 770 771/* 772 * "slow" syscall return path. 773 */ 774SYM_CODE_START_LOCAL(ret_to_user) 775 disable_daif 776 gic_prio_kentry_setup tmp=x3 777 ldr x1, [tsk, #TSK_TI_FLAGS] 778 and x2, x1, #_TIF_WORK_MASK 779 cbnz x2, work_pending 780finish_ret_to_user: 781 /* Ignore asynchronous tag check faults in the uaccess routines */ 782 clear_mte_async_tcf 783 enable_step_tsk x1, x2 784#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 785 bl stackleak_erase 786#endif 787 kernel_exit 0 788 789/* 790 * Ok, we need to do extra processing, enter the slow path. 791 */ 792work_pending: 793 mov x0, sp // 'regs' 794 bl do_notify_resume 795#ifdef CONFIG_TRACE_IRQFLAGS 796 bl trace_hardirqs_on // enabled while in userspace 797#endif 798 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step 799 b finish_ret_to_user 800SYM_CODE_END(ret_to_user) 801 802 .popsection // .entry.text 803 804#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 805/* 806 * Exception vectors trampoline. 807 */ 808 .pushsection ".entry.tramp.text", "ax" 809 810 .macro tramp_map_kernel, tmp 811 mrs \tmp, ttbr1_el1 812 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 813 bic \tmp, \tmp, #USER_ASID_FLAG 814 msr ttbr1_el1, \tmp 815#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 816alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 817 /* ASID already in \tmp[63:48] */ 818 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 819 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 820 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 821 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 822 isb 823 tlbi vae1, \tmp 824 dsb nsh 825alternative_else_nop_endif 826#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 827 .endm 828 829 .macro tramp_unmap_kernel, tmp 830 mrs \tmp, ttbr1_el1 831 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 832 orr \tmp, \tmp, #USER_ASID_FLAG 833 msr ttbr1_el1, \tmp 834 /* 835 * We avoid running the post_ttbr_update_workaround here because 836 * it's only needed by Cavium ThunderX, which requires KPTI to be 837 * disabled. 838 */ 839 .endm 840 841 .macro tramp_ventry, regsize = 64 842 .align 7 8431: 844 .if \regsize == 64 845 msr tpidrro_el0, x30 // Restored in kernel_ventry 846 .endif 847 /* 848 * Defend against branch aliasing attacks by pushing a dummy 849 * entry onto the return stack and using a RET instruction to 850 * enter the full-fat kernel vectors. 851 */ 852 bl 2f 853 b . 8542: 855 tramp_map_kernel x30 856#ifdef CONFIG_RANDOMIZE_BASE 857 adr x30, tramp_vectors + PAGE_SIZE 858alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 859 ldr x30, [x30] 860#else 861 ldr x30, =vectors 862#endif 863alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 864 prfm plil1strm, [x30, #(1b - tramp_vectors)] 865alternative_else_nop_endif 866 msr vbar_el1, x30 867 add x30, x30, #(1b - tramp_vectors) 868 isb 869 ret 870 .endm 871 872 .macro tramp_exit, regsize = 64 873 adr x30, tramp_vectors 874 msr vbar_el1, x30 875 tramp_unmap_kernel x30 876 .if \regsize == 64 877 mrs x30, far_el1 878 .endif 879 eret 880 sb 881 .endm 882 883 .align 11 884SYM_CODE_START_NOALIGN(tramp_vectors) 885 .space 0x400 886 887 tramp_ventry 888 tramp_ventry 889 tramp_ventry 890 tramp_ventry 891 892 tramp_ventry 32 893 tramp_ventry 32 894 tramp_ventry 32 895 tramp_ventry 32 896SYM_CODE_END(tramp_vectors) 897 898SYM_CODE_START(tramp_exit_native) 899 tramp_exit 900SYM_CODE_END(tramp_exit_native) 901 902SYM_CODE_START(tramp_exit_compat) 903 tramp_exit 32 904SYM_CODE_END(tramp_exit_compat) 905 906 .ltorg 907 .popsection // .entry.tramp.text 908#ifdef CONFIG_RANDOMIZE_BASE 909 .pushsection ".rodata", "a" 910 .align PAGE_SHIFT 911SYM_DATA_START(__entry_tramp_data_start) 912 .quad vectors 913SYM_DATA_END(__entry_tramp_data_start) 914 .popsection // .rodata 915#endif /* CONFIG_RANDOMIZE_BASE */ 916#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 917 918/* 919 * Register switch for AArch64. The callee-saved registers need to be saved 920 * and restored. On entry: 921 * x0 = previous task_struct (must be preserved across the switch) 922 * x1 = next task_struct 923 * Previous and next are guaranteed not to be the same. 924 * 925 */ 926SYM_FUNC_START(cpu_switch_to) 927 mov x10, #THREAD_CPU_CONTEXT 928 add x8, x0, x10 929 mov x9, sp 930 stp x19, x20, [x8], #16 // store callee-saved registers 931 stp x21, x22, [x8], #16 932 stp x23, x24, [x8], #16 933 stp x25, x26, [x8], #16 934 stp x27, x28, [x8], #16 935 stp x29, x9, [x8], #16 936 str lr, [x8] 937 add x8, x1, x10 938 ldp x19, x20, [x8], #16 // restore callee-saved registers 939 ldp x21, x22, [x8], #16 940 ldp x23, x24, [x8], #16 941 ldp x25, x26, [x8], #16 942 ldp x27, x28, [x8], #16 943 ldp x29, x9, [x8], #16 944 ldr lr, [x8] 945 mov sp, x9 946 msr sp_el0, x1 947 ptrauth_keys_install_kernel x1, x8, x9, x10 948 scs_save x0, x8 949 scs_load x1, x8 950 ret 951SYM_FUNC_END(cpu_switch_to) 952NOKPROBE(cpu_switch_to) 953 954/* 955 * This is how we return from a fork. 956 */ 957SYM_CODE_START(ret_from_fork) 958 bl schedule_tail 959 cbz x19, 1f // not a kernel thread 960 mov x0, x20 961 blr x19 9621: get_current_task tsk 963 b ret_to_user 964SYM_CODE_END(ret_from_fork) 965NOKPROBE(ret_from_fork) 966 967#ifdef CONFIG_ARM_SDE_INTERFACE 968 969#include <asm/sdei.h> 970#include <uapi/linux/arm_sdei.h> 971 972.macro sdei_handler_exit exit_mode 973 /* On success, this call never returns... */ 974 cmp \exit_mode, #SDEI_EXIT_SMC 975 b.ne 99f 976 smc #0 977 b . 97899: hvc #0 979 b . 980.endm 981 982#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 983/* 984 * The regular SDEI entry point may have been unmapped along with the rest of 985 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 986 * argument accessible. 987 * 988 * This clobbers x4, __sdei_handler() will restore this from firmware's 989 * copy. 990 */ 991.ltorg 992.pushsection ".entry.tramp.text", "ax" 993SYM_CODE_START(__sdei_asm_entry_trampoline) 994 mrs x4, ttbr1_el1 995 tbz x4, #USER_ASID_BIT, 1f 996 997 tramp_map_kernel tmp=x4 998 isb 999 mov x4, xzr 1000 1001 /* 1002 * Use reg->interrupted_regs.addr_limit to remember whether to unmap 1003 * the kernel on exit. 1004 */ 10051: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 1006 1007#ifdef CONFIG_RANDOMIZE_BASE 1008 adr x4, tramp_vectors + PAGE_SIZE 1009 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler 1010 ldr x4, [x4] 1011#else 1012 ldr x4, =__sdei_asm_handler 1013#endif 1014 br x4 1015SYM_CODE_END(__sdei_asm_entry_trampoline) 1016NOKPROBE(__sdei_asm_entry_trampoline) 1017 1018/* 1019 * Make the exit call and restore the original ttbr1_el1 1020 * 1021 * x0 & x1: setup for the exit API call 1022 * x2: exit_mode 1023 * x4: struct sdei_registered_event argument from registration time. 1024 */ 1025SYM_CODE_START(__sdei_asm_exit_trampoline) 1026 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 1027 cbnz x4, 1f 1028 1029 tramp_unmap_kernel tmp=x4 1030 10311: sdei_handler_exit exit_mode=x2 1032SYM_CODE_END(__sdei_asm_exit_trampoline) 1033NOKPROBE(__sdei_asm_exit_trampoline) 1034 .ltorg 1035.popsection // .entry.tramp.text 1036#ifdef CONFIG_RANDOMIZE_BASE 1037.pushsection ".rodata", "a" 1038SYM_DATA_START(__sdei_asm_trampoline_next_handler) 1039 .quad __sdei_asm_handler 1040SYM_DATA_END(__sdei_asm_trampoline_next_handler) 1041.popsection // .rodata 1042#endif /* CONFIG_RANDOMIZE_BASE */ 1043#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1044 1045/* 1046 * Software Delegated Exception entry point. 1047 * 1048 * x0: Event number 1049 * x1: struct sdei_registered_event argument from registration time. 1050 * x2: interrupted PC 1051 * x3: interrupted PSTATE 1052 * x4: maybe clobbered by the trampoline 1053 * 1054 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 1055 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 1056 * want them. 1057 */ 1058SYM_CODE_START(__sdei_asm_handler) 1059 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 1060 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 1061 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 1062 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 1063 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 1064 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 1065 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 1066 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 1067 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 1068 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 1069 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 1070 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 1071 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1072 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1073 mov x4, sp 1074 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1075 1076 mov x19, x1 1077 1078#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1079 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1080#endif 1081 1082#ifdef CONFIG_VMAP_STACK 1083 /* 1084 * entry.S may have been using sp as a scratch register, find whether 1085 * this is a normal or critical event and switch to the appropriate 1086 * stack for this CPU. 1087 */ 1088 cbnz w4, 1f 1089 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1090 b 2f 10911: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10922: mov x6, #SDEI_STACK_SIZE 1093 add x5, x5, x6 1094 mov sp, x5 1095#endif 1096 1097#ifdef CONFIG_SHADOW_CALL_STACK 1098 /* Use a separate shadow call stack for normal and critical events */ 1099 cbnz w4, 3f 1100 adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6 1101 b 4f 11023: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6 11034: 1104#endif 1105 1106 /* 1107 * We may have interrupted userspace, or a guest, or exit-from or 1108 * return-to either of these. We can't trust sp_el0, restore it. 1109 */ 1110 mrs x28, sp_el0 1111 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1112 msr sp_el0, x0 1113 1114 /* If we interrupted the kernel point to the previous stack/frame. */ 1115 and x0, x3, #0xc 1116 mrs x1, CurrentEL 1117 cmp x0, x1 1118 csel x29, x29, xzr, eq // fp, or zero 1119 csel x4, x2, xzr, eq // elr, or zero 1120 1121 stp x29, x4, [sp, #-16]! 1122 mov x29, sp 1123 1124 add x0, x19, #SDEI_EVENT_INTREGS 1125 mov x1, x19 1126 bl __sdei_handler 1127 1128 msr sp_el0, x28 1129 /* restore regs >x17 that we clobbered */ 1130 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1131 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1132 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1133 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1134 mov sp, x1 1135 1136 mov x1, x0 // address to complete_and_resume 1137 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1138 cmp x0, #1 1139 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1140 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1141 csel x0, x2, x3, ls 1142 1143 ldr_l x2, sdei_exit_mode 1144 1145alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1146 sdei_handler_exit exit_mode=x2 1147alternative_else_nop_endif 1148 1149#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1150 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1151 br x5 1152#endif 1153SYM_CODE_END(__sdei_asm_handler) 1154NOKPROBE(__sdei_asm_handler) 1155#endif /* CONFIG_ARM_SDE_INTERFACE */ 1156