1 /* 2 * ARMv8 single-step debug support and mdscr context switching. 3 * 4 * Copyright (C) 2012 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: Will Deacon <will.deacon@arm.com> 19 */ 20 21 #include <linux/cpu.h> 22 #include <linux/debugfs.h> 23 #include <linux/hardirq.h> 24 #include <linux/init.h> 25 #include <linux/ptrace.h> 26 #include <linux/stat.h> 27 #include <linux/uaccess.h> 28 29 #include <asm/debug-monitors.h> 30 #include <asm/local.h> 31 #include <asm/cputype.h> 32 #include <asm/system_misc.h> 33 34 /* Low-level stepping controls. */ 35 #define DBG_MDSCR_SS (1 << 0) 36 #define DBG_SPSR_SS (1 << 21) 37 38 /* MDSCR_EL1 enabling bits */ 39 #define DBG_MDSCR_KDE (1 << 13) 40 #define DBG_MDSCR_MDE (1 << 15) 41 #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) 42 43 /* Determine debug architecture. */ 44 u8 debug_monitors_arch(void) 45 { 46 return read_cpuid(ID_AA64DFR0_EL1) & 0xf; 47 } 48 49 /* 50 * MDSCR access routines. 51 */ 52 static void mdscr_write(u32 mdscr) 53 { 54 unsigned long flags; 55 local_dbg_save(flags); 56 asm volatile("msr mdscr_el1, %0" :: "r" (mdscr)); 57 local_dbg_restore(flags); 58 } 59 60 static u32 mdscr_read(void) 61 { 62 u32 mdscr; 63 asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); 64 return mdscr; 65 } 66 67 /* 68 * Allow root to disable self-hosted debug from userspace. 69 * This is useful if you want to connect an external JTAG debugger. 70 */ 71 static u32 debug_enabled = 1; 72 73 static int create_debug_debugfs_entry(void) 74 { 75 debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled); 76 return 0; 77 } 78 fs_initcall(create_debug_debugfs_entry); 79 80 static int __init early_debug_disable(char *buf) 81 { 82 debug_enabled = 0; 83 return 0; 84 } 85 86 early_param("nodebugmon", early_debug_disable); 87 88 /* 89 * Keep track of debug users on each core. 90 * The ref counts are per-cpu so we use a local_t type. 91 */ 92 static DEFINE_PER_CPU(local_t, mde_ref_count); 93 static DEFINE_PER_CPU(local_t, kde_ref_count); 94 95 void enable_debug_monitors(enum debug_el el) 96 { 97 u32 mdscr, enable = 0; 98 99 WARN_ON(preemptible()); 100 101 if (local_inc_return(&__get_cpu_var(mde_ref_count)) == 1) 102 enable = DBG_MDSCR_MDE; 103 104 if (el == DBG_ACTIVE_EL1 && 105 local_inc_return(&__get_cpu_var(kde_ref_count)) == 1) 106 enable |= DBG_MDSCR_KDE; 107 108 if (enable && debug_enabled) { 109 mdscr = mdscr_read(); 110 mdscr |= enable; 111 mdscr_write(mdscr); 112 } 113 } 114 115 void disable_debug_monitors(enum debug_el el) 116 { 117 u32 mdscr, disable = 0; 118 119 WARN_ON(preemptible()); 120 121 if (local_dec_and_test(&__get_cpu_var(mde_ref_count))) 122 disable = ~DBG_MDSCR_MDE; 123 124 if (el == DBG_ACTIVE_EL1 && 125 local_dec_and_test(&__get_cpu_var(kde_ref_count))) 126 disable &= ~DBG_MDSCR_KDE; 127 128 if (disable) { 129 mdscr = mdscr_read(); 130 mdscr &= disable; 131 mdscr_write(mdscr); 132 } 133 } 134 135 /* 136 * OS lock clearing. 137 */ 138 static void clear_os_lock(void *unused) 139 { 140 asm volatile("msr oslar_el1, %0" : : "r" (0)); 141 isb(); 142 } 143 144 static int os_lock_notify(struct notifier_block *self, 145 unsigned long action, void *data) 146 { 147 int cpu = (unsigned long)data; 148 if (action == CPU_ONLINE) 149 smp_call_function_single(cpu, clear_os_lock, NULL, 1); 150 return NOTIFY_OK; 151 } 152 153 static struct notifier_block os_lock_nb = { 154 .notifier_call = os_lock_notify, 155 }; 156 157 static int debug_monitors_init(void) 158 { 159 /* Clear the OS lock. */ 160 smp_call_function(clear_os_lock, NULL, 1); 161 clear_os_lock(NULL); 162 163 /* Register hotplug handler. */ 164 register_cpu_notifier(&os_lock_nb); 165 return 0; 166 } 167 postcore_initcall(debug_monitors_init); 168 169 /* 170 * Single step API and exception handling. 171 */ 172 static void set_regs_spsr_ss(struct pt_regs *regs) 173 { 174 unsigned long spsr; 175 176 spsr = regs->pstate; 177 spsr &= ~DBG_SPSR_SS; 178 spsr |= DBG_SPSR_SS; 179 regs->pstate = spsr; 180 } 181 182 static void clear_regs_spsr_ss(struct pt_regs *regs) 183 { 184 unsigned long spsr; 185 186 spsr = regs->pstate; 187 spsr &= ~DBG_SPSR_SS; 188 regs->pstate = spsr; 189 } 190 191 static int single_step_handler(unsigned long addr, unsigned int esr, 192 struct pt_regs *regs) 193 { 194 siginfo_t info; 195 196 /* 197 * If we are stepping a pending breakpoint, call the hw_breakpoint 198 * handler first. 199 */ 200 if (!reinstall_suspended_bps(regs)) 201 return 0; 202 203 if (user_mode(regs)) { 204 info.si_signo = SIGTRAP; 205 info.si_errno = 0; 206 info.si_code = TRAP_HWBKPT; 207 info.si_addr = (void __user *)instruction_pointer(regs); 208 force_sig_info(SIGTRAP, &info, current); 209 210 /* 211 * ptrace will disable single step unless explicitly 212 * asked to re-enable it. For other clients, it makes 213 * sense to leave it enabled (i.e. rewind the controls 214 * to the active-not-pending state). 215 */ 216 user_rewind_single_step(current); 217 } else { 218 /* TODO: route to KGDB */ 219 pr_warning("Unexpected kernel single-step exception at EL1\n"); 220 /* 221 * Re-enable stepping since we know that we will be 222 * returning to regs. 223 */ 224 set_regs_spsr_ss(regs); 225 } 226 227 return 0; 228 } 229 230 static int brk_handler(unsigned long addr, unsigned int esr, 231 struct pt_regs *regs) 232 { 233 siginfo_t info; 234 235 if (!user_mode(regs)) 236 return -EFAULT; 237 238 info = (siginfo_t) { 239 .si_signo = SIGTRAP, 240 .si_errno = 0, 241 .si_code = TRAP_BRKPT, 242 .si_addr = (void __user *)instruction_pointer(regs), 243 }; 244 245 force_sig_info(SIGTRAP, &info, current); 246 return 0; 247 } 248 249 int aarch32_break_handler(struct pt_regs *regs) 250 { 251 siginfo_t info; 252 unsigned int instr; 253 bool bp = false; 254 void __user *pc = (void __user *)instruction_pointer(regs); 255 256 if (!compat_user_mode(regs)) 257 return -EFAULT; 258 259 if (compat_thumb_mode(regs)) { 260 /* get 16-bit Thumb instruction */ 261 get_user(instr, (u16 __user *)pc); 262 if (instr == AARCH32_BREAK_THUMB2_LO) { 263 /* get second half of 32-bit Thumb-2 instruction */ 264 get_user(instr, (u16 __user *)(pc + 2)); 265 bp = instr == AARCH32_BREAK_THUMB2_HI; 266 } else { 267 bp = instr == AARCH32_BREAK_THUMB; 268 } 269 } else { 270 /* 32-bit ARM instruction */ 271 get_user(instr, (u32 __user *)pc); 272 bp = (instr & ~0xf0000000) == AARCH32_BREAK_ARM; 273 } 274 275 if (!bp) 276 return -EFAULT; 277 278 info = (siginfo_t) { 279 .si_signo = SIGTRAP, 280 .si_errno = 0, 281 .si_code = TRAP_BRKPT, 282 .si_addr = pc, 283 }; 284 285 force_sig_info(SIGTRAP, &info, current); 286 return 0; 287 } 288 289 static int __init debug_traps_init(void) 290 { 291 hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP, 292 TRAP_HWBKPT, "single-step handler"); 293 hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP, 294 TRAP_BRKPT, "ptrace BRK handler"); 295 return 0; 296 } 297 arch_initcall(debug_traps_init); 298 299 /* Re-enable single step for syscall restarting. */ 300 void user_rewind_single_step(struct task_struct *task) 301 { 302 /* 303 * If single step is active for this thread, then set SPSR.SS 304 * to 1 to avoid returning to the active-pending state. 305 */ 306 if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) 307 set_regs_spsr_ss(task_pt_regs(task)); 308 } 309 310 void user_fastforward_single_step(struct task_struct *task) 311 { 312 if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) 313 clear_regs_spsr_ss(task_pt_regs(task)); 314 } 315 316 /* Kernel API */ 317 void kernel_enable_single_step(struct pt_regs *regs) 318 { 319 WARN_ON(!irqs_disabled()); 320 set_regs_spsr_ss(regs); 321 mdscr_write(mdscr_read() | DBG_MDSCR_SS); 322 enable_debug_monitors(DBG_ACTIVE_EL1); 323 } 324 325 void kernel_disable_single_step(void) 326 { 327 WARN_ON(!irqs_disabled()); 328 mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); 329 disable_debug_monitors(DBG_ACTIVE_EL1); 330 } 331 332 int kernel_active_single_step(void) 333 { 334 WARN_ON(!irqs_disabled()); 335 return mdscr_read() & DBG_MDSCR_SS; 336 } 337 338 /* ptrace API */ 339 void user_enable_single_step(struct task_struct *task) 340 { 341 set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); 342 set_regs_spsr_ss(task_pt_regs(task)); 343 } 344 345 void user_disable_single_step(struct task_struct *task) 346 { 347 clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); 348 } 349