1 /* 2 * Record and handle CPU attributes. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 #include <asm/arch_timer.h> 18 #include <asm/cachetype.h> 19 #include <asm/cpu.h> 20 #include <asm/cputype.h> 21 #include <asm/cpufeature.h> 22 23 #include <linux/bitops.h> 24 #include <linux/bug.h> 25 #include <linux/compat.h> 26 #include <linux/elf.h> 27 #include <linux/init.h> 28 #include <linux/kernel.h> 29 #include <linux/personality.h> 30 #include <linux/preempt.h> 31 #include <linux/printk.h> 32 #include <linux/seq_file.h> 33 #include <linux/sched.h> 34 #include <linux/smp.h> 35 #include <linux/delay.h> 36 37 /* 38 * In case the boot CPU is hotpluggable, we record its initial state and 39 * current state separately. Certain system registers may contain different 40 * values depending on configuration at or after reset. 41 */ 42 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 43 static struct cpuinfo_arm64 boot_cpu_data; 44 45 static char *icache_policy_str[] = { 46 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", 47 [ICACHE_POLICY_AIVIVT] = "AIVIVT", 48 [ICACHE_POLICY_VIPT] = "VIPT", 49 [ICACHE_POLICY_PIPT] = "PIPT", 50 }; 51 52 unsigned long __icache_flags; 53 54 static const char *const hwcap_str[] = { 55 "fp", 56 "asimd", 57 "evtstrm", 58 "aes", 59 "pmull", 60 "sha1", 61 "sha2", 62 "crc32", 63 "atomics", 64 "fphp", 65 "asimdhp", 66 "cpuid", 67 "asimdrdm", 68 NULL 69 }; 70 71 #ifdef CONFIG_COMPAT 72 static const char *const compat_hwcap_str[] = { 73 "swp", 74 "half", 75 "thumb", 76 "26bit", 77 "fastmult", 78 "fpa", 79 "vfp", 80 "edsp", 81 "java", 82 "iwmmxt", 83 "crunch", 84 "thumbee", 85 "neon", 86 "vfpv3", 87 "vfpv3d16", 88 "tls", 89 "vfpv4", 90 "idiva", 91 "idivt", 92 "vfpd32", 93 "lpae", 94 "evtstrm", 95 NULL 96 }; 97 98 static const char *const compat_hwcap2_str[] = { 99 "aes", 100 "pmull", 101 "sha1", 102 "sha2", 103 "crc32", 104 NULL 105 }; 106 #endif /* CONFIG_COMPAT */ 107 108 static int c_show(struct seq_file *m, void *v) 109 { 110 int i, j; 111 bool compat = personality(current->personality) == PER_LINUX32; 112 113 for_each_online_cpu(i) { 114 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 115 u32 midr = cpuinfo->reg_midr; 116 117 /* 118 * glibc reads /proc/cpuinfo to determine the number of 119 * online processors, looking for lines beginning with 120 * "processor". Give glibc what it expects. 121 */ 122 seq_printf(m, "processor\t: %d\n", i); 123 if (compat) 124 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 125 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 126 127 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 128 loops_per_jiffy / (500000UL/HZ), 129 loops_per_jiffy / (5000UL/HZ) % 100); 130 131 /* 132 * Dump out the common processor features in a single line. 133 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 134 * rather than attempting to parse this, but there's a body of 135 * software which does already (at least for 32-bit). 136 */ 137 seq_puts(m, "Features\t:"); 138 if (compat) { 139 #ifdef CONFIG_COMPAT 140 for (j = 0; compat_hwcap_str[j]; j++) 141 if (compat_elf_hwcap & (1 << j)) 142 seq_printf(m, " %s", compat_hwcap_str[j]); 143 144 for (j = 0; compat_hwcap2_str[j]; j++) 145 if (compat_elf_hwcap2 & (1 << j)) 146 seq_printf(m, " %s", compat_hwcap2_str[j]); 147 #endif /* CONFIG_COMPAT */ 148 } else { 149 for (j = 0; hwcap_str[j]; j++) 150 if (elf_hwcap & (1 << j)) 151 seq_printf(m, " %s", hwcap_str[j]); 152 } 153 seq_puts(m, "\n"); 154 155 seq_printf(m, "CPU implementer\t: 0x%02x\n", 156 MIDR_IMPLEMENTOR(midr)); 157 seq_printf(m, "CPU architecture: 8\n"); 158 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 159 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 160 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 161 } 162 163 return 0; 164 } 165 166 static void *c_start(struct seq_file *m, loff_t *pos) 167 { 168 return *pos < 1 ? (void *)1 : NULL; 169 } 170 171 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 172 { 173 ++*pos; 174 return NULL; 175 } 176 177 static void c_stop(struct seq_file *m, void *v) 178 { 179 } 180 181 const struct seq_operations cpuinfo_op = { 182 .start = c_start, 183 .next = c_next, 184 .stop = c_stop, 185 .show = c_show 186 }; 187 188 189 static struct kobj_type cpuregs_kobj_type = { 190 .sysfs_ops = &kobj_sysfs_ops, 191 }; 192 193 /* 194 * The ARM ARM uses the phrase "32-bit register" to describe a register 195 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 196 * no statement is made as to whether the upper 32 bits will or will not 197 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 198 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 199 * 200 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 201 * registers, we expose them both as 64 bit values to cater for possible 202 * future expansion without an ABI break. 203 */ 204 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 205 #define CPUREGS_ATTR_RO(_name, _field) \ 206 static ssize_t _name##_show(struct kobject *kobj, \ 207 struct kobj_attribute *attr, char *buf) \ 208 { \ 209 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 210 \ 211 if (info->reg_midr) \ 212 return sprintf(buf, "0x%016x\n", info->reg_##_field); \ 213 else \ 214 return 0; \ 215 } \ 216 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 217 218 CPUREGS_ATTR_RO(midr_el1, midr); 219 CPUREGS_ATTR_RO(revidr_el1, revidr); 220 221 static struct attribute *cpuregs_id_attrs[] = { 222 &cpuregs_attr_midr_el1.attr, 223 &cpuregs_attr_revidr_el1.attr, 224 NULL 225 }; 226 227 static struct attribute_group cpuregs_attr_group = { 228 .attrs = cpuregs_id_attrs, 229 .name = "identification" 230 }; 231 232 static int cpuid_cpu_online(unsigned int cpu) 233 { 234 int rc; 235 struct device *dev; 236 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 237 238 dev = get_cpu_device(cpu); 239 if (!dev) { 240 rc = -ENODEV; 241 goto out; 242 } 243 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 244 if (rc) 245 goto out; 246 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 247 if (rc) 248 kobject_del(&info->kobj); 249 out: 250 return rc; 251 } 252 253 static int cpuid_cpu_offline(unsigned int cpu) 254 { 255 struct device *dev; 256 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 257 258 dev = get_cpu_device(cpu); 259 if (!dev) 260 return -ENODEV; 261 if (info->kobj.parent) { 262 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 263 kobject_del(&info->kobj); 264 } 265 266 return 0; 267 } 268 269 static int __init cpuinfo_regs_init(void) 270 { 271 int cpu, ret; 272 273 for_each_possible_cpu(cpu) { 274 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 275 276 kobject_init(&info->kobj, &cpuregs_kobj_type); 277 } 278 279 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 280 cpuid_cpu_online, cpuid_cpu_offline); 281 if (ret < 0) { 282 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 283 return ret; 284 } 285 return 0; 286 } 287 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 288 { 289 unsigned int cpu = smp_processor_id(); 290 u32 l1ip = CTR_L1IP(info->reg_ctr); 291 292 if (l1ip != ICACHE_POLICY_PIPT) { 293 /* 294 * VIPT caches are non-aliasing if the VA always equals the PA 295 * in all bit positions that are covered by the index. This is 296 * the case if the size of a way (# of sets * line size) does 297 * not exceed PAGE_SIZE. 298 */ 299 u32 waysize = icache_get_numsets() * icache_get_linesize(); 300 301 if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE) 302 set_bit(ICACHEF_ALIASING, &__icache_flags); 303 } 304 if (l1ip == ICACHE_POLICY_AIVIVT) 305 set_bit(ICACHEF_AIVIVT, &__icache_flags); 306 307 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); 308 } 309 310 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 311 { 312 info->reg_cntfrq = arch_timer_get_cntfrq(); 313 info->reg_ctr = read_cpuid_cachetype(); 314 info->reg_dczid = read_cpuid(DCZID_EL0); 315 info->reg_midr = read_cpuid_id(); 316 info->reg_revidr = read_cpuid(REVIDR_EL1); 317 318 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 319 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 320 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 321 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 322 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 323 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 324 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 325 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 326 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 327 328 /* Update the 32bit ID registers only if AArch32 is implemented */ 329 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 330 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 331 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 332 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 333 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 334 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 335 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 336 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 337 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 338 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 339 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 340 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 341 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 342 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 343 344 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 345 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 346 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 347 } 348 349 cpuinfo_detect_icache_policy(info); 350 } 351 352 void cpuinfo_store_cpu(void) 353 { 354 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 355 __cpuinfo_store_cpu(info); 356 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 357 } 358 359 void __init cpuinfo_store_boot_cpu(void) 360 { 361 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 362 __cpuinfo_store_cpu(info); 363 364 boot_cpu_data = *info; 365 init_cpu_features(&boot_cpu_data); 366 } 367 368 device_initcall(cpuinfo_regs_init); 369