1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static const char *icache_policy_str[] = { 37 [ICACHE_POLICY_VPIPT] = "VPIPT", 38 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", 39 [ICACHE_POLICY_VIPT] = "VIPT", 40 [ICACHE_POLICY_PIPT] = "PIPT", 41 }; 42 43 unsigned long __icache_flags; 44 45 static const char *const hwcap_str[] = { 46 [KERNEL_HWCAP_FP] = "fp", 47 [KERNEL_HWCAP_ASIMD] = "asimd", 48 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 49 [KERNEL_HWCAP_AES] = "aes", 50 [KERNEL_HWCAP_PMULL] = "pmull", 51 [KERNEL_HWCAP_SHA1] = "sha1", 52 [KERNEL_HWCAP_SHA2] = "sha2", 53 [KERNEL_HWCAP_CRC32] = "crc32", 54 [KERNEL_HWCAP_ATOMICS] = "atomics", 55 [KERNEL_HWCAP_FPHP] = "fphp", 56 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 57 [KERNEL_HWCAP_CPUID] = "cpuid", 58 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 59 [KERNEL_HWCAP_JSCVT] = "jscvt", 60 [KERNEL_HWCAP_FCMA] = "fcma", 61 [KERNEL_HWCAP_LRCPC] = "lrcpc", 62 [KERNEL_HWCAP_DCPOP] = "dcpop", 63 [KERNEL_HWCAP_SHA3] = "sha3", 64 [KERNEL_HWCAP_SM3] = "sm3", 65 [KERNEL_HWCAP_SM4] = "sm4", 66 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 67 [KERNEL_HWCAP_SHA512] = "sha512", 68 [KERNEL_HWCAP_SVE] = "sve", 69 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 70 [KERNEL_HWCAP_DIT] = "dit", 71 [KERNEL_HWCAP_USCAT] = "uscat", 72 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 73 [KERNEL_HWCAP_FLAGM] = "flagm", 74 [KERNEL_HWCAP_SSBS] = "ssbs", 75 [KERNEL_HWCAP_SB] = "sb", 76 [KERNEL_HWCAP_PACA] = "paca", 77 [KERNEL_HWCAP_PACG] = "pacg", 78 [KERNEL_HWCAP_DCPODP] = "dcpodp", 79 [KERNEL_HWCAP_SVE2] = "sve2", 80 [KERNEL_HWCAP_SVEAES] = "sveaes", 81 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 82 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 83 [KERNEL_HWCAP_SVESHA3] = "svesha3", 84 [KERNEL_HWCAP_SVESM4] = "svesm4", 85 [KERNEL_HWCAP_FLAGM2] = "flagm2", 86 [KERNEL_HWCAP_FRINT] = "frint", 87 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 88 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 89 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 90 [KERNEL_HWCAP_SVEBF16] = "svebf16", 91 [KERNEL_HWCAP_I8MM] = "i8mm", 92 [KERNEL_HWCAP_BF16] = "bf16", 93 [KERNEL_HWCAP_DGH] = "dgh", 94 [KERNEL_HWCAP_RNG] = "rng", 95 [KERNEL_HWCAP_BTI] = "bti", 96 [KERNEL_HWCAP_MTE] = "mte", 97 [KERNEL_HWCAP_ECV] = "ecv", 98 [KERNEL_HWCAP_AFP] = "afp", 99 [KERNEL_HWCAP_RPRES] = "rpres", 100 [KERNEL_HWCAP_MTE3] = "mte3", 101 [KERNEL_HWCAP_SME] = "sme", 102 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 103 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 104 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 105 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 106 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 107 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 108 [KERNEL_HWCAP_SME_FA64] = "smefa64", 109 }; 110 111 #ifdef CONFIG_COMPAT 112 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 113 static const char *const compat_hwcap_str[] = { 114 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 115 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 116 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 117 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 118 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 119 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 120 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 121 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 122 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 123 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 124 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 125 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 126 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 127 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 128 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 129 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 130 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 131 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 132 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 133 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 134 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 135 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 136 }; 137 138 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 139 static const char *const compat_hwcap2_str[] = { 140 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 141 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 142 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 143 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 144 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 145 }; 146 #endif /* CONFIG_COMPAT */ 147 148 static int c_show(struct seq_file *m, void *v) 149 { 150 int i, j; 151 bool compat = personality(current->personality) == PER_LINUX32; 152 153 for_each_online_cpu(i) { 154 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 155 u32 midr = cpuinfo->reg_midr; 156 157 /* 158 * glibc reads /proc/cpuinfo to determine the number of 159 * online processors, looking for lines beginning with 160 * "processor". Give glibc what it expects. 161 */ 162 seq_printf(m, "processor\t: %d\n", i); 163 if (compat) 164 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 165 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 166 167 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 168 loops_per_jiffy / (500000UL/HZ), 169 loops_per_jiffy / (5000UL/HZ) % 100); 170 171 /* 172 * Dump out the common processor features in a single line. 173 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 174 * rather than attempting to parse this, but there's a body of 175 * software which does already (at least for 32-bit). 176 */ 177 seq_puts(m, "Features\t:"); 178 if (compat) { 179 #ifdef CONFIG_COMPAT 180 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 181 if (compat_elf_hwcap & (1 << j)) { 182 /* 183 * Warn once if any feature should not 184 * have been present on arm64 platform. 185 */ 186 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 187 continue; 188 189 seq_printf(m, " %s", compat_hwcap_str[j]); 190 } 191 } 192 193 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 194 if (compat_elf_hwcap2 & (1 << j)) 195 seq_printf(m, " %s", compat_hwcap2_str[j]); 196 #endif /* CONFIG_COMPAT */ 197 } else { 198 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 199 if (cpu_have_feature(j)) 200 seq_printf(m, " %s", hwcap_str[j]); 201 } 202 seq_puts(m, "\n"); 203 204 seq_printf(m, "CPU implementer\t: 0x%02x\n", 205 MIDR_IMPLEMENTOR(midr)); 206 seq_printf(m, "CPU architecture: 8\n"); 207 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 208 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 209 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 210 } 211 212 return 0; 213 } 214 215 static void *c_start(struct seq_file *m, loff_t *pos) 216 { 217 return *pos < 1 ? (void *)1 : NULL; 218 } 219 220 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 221 { 222 ++*pos; 223 return NULL; 224 } 225 226 static void c_stop(struct seq_file *m, void *v) 227 { 228 } 229 230 const struct seq_operations cpuinfo_op = { 231 .start = c_start, 232 .next = c_next, 233 .stop = c_stop, 234 .show = c_show 235 }; 236 237 238 static struct kobj_type cpuregs_kobj_type = { 239 .sysfs_ops = &kobj_sysfs_ops, 240 }; 241 242 /* 243 * The ARM ARM uses the phrase "32-bit register" to describe a register 244 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 245 * no statement is made as to whether the upper 32 bits will or will not 246 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 247 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 248 * 249 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 250 * registers, we expose them both as 64 bit values to cater for possible 251 * future expansion without an ABI break. 252 */ 253 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 254 #define CPUREGS_ATTR_RO(_name, _field) \ 255 static ssize_t _name##_show(struct kobject *kobj, \ 256 struct kobj_attribute *attr, char *buf) \ 257 { \ 258 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 259 \ 260 if (info->reg_midr) \ 261 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 262 else \ 263 return 0; \ 264 } \ 265 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 266 267 CPUREGS_ATTR_RO(midr_el1, midr); 268 CPUREGS_ATTR_RO(revidr_el1, revidr); 269 270 static struct attribute *cpuregs_id_attrs[] = { 271 &cpuregs_attr_midr_el1.attr, 272 &cpuregs_attr_revidr_el1.attr, 273 NULL 274 }; 275 276 static const struct attribute_group cpuregs_attr_group = { 277 .attrs = cpuregs_id_attrs, 278 .name = "identification" 279 }; 280 281 static int cpuid_cpu_online(unsigned int cpu) 282 { 283 int rc; 284 struct device *dev; 285 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 286 287 dev = get_cpu_device(cpu); 288 if (!dev) { 289 rc = -ENODEV; 290 goto out; 291 } 292 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 293 if (rc) 294 goto out; 295 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 296 if (rc) 297 kobject_del(&info->kobj); 298 out: 299 return rc; 300 } 301 302 static int cpuid_cpu_offline(unsigned int cpu) 303 { 304 struct device *dev; 305 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 306 307 dev = get_cpu_device(cpu); 308 if (!dev) 309 return -ENODEV; 310 if (info->kobj.parent) { 311 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 312 kobject_del(&info->kobj); 313 } 314 315 return 0; 316 } 317 318 static int __init cpuinfo_regs_init(void) 319 { 320 int cpu, ret; 321 322 for_each_possible_cpu(cpu) { 323 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 324 325 kobject_init(&info->kobj, &cpuregs_kobj_type); 326 } 327 328 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 329 cpuid_cpu_online, cpuid_cpu_offline); 330 if (ret < 0) { 331 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 332 return ret; 333 } 334 return 0; 335 } 336 device_initcall(cpuinfo_regs_init); 337 338 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 339 { 340 unsigned int cpu = smp_processor_id(); 341 u32 l1ip = CTR_L1IP(info->reg_ctr); 342 343 switch (l1ip) { 344 case ICACHE_POLICY_PIPT: 345 break; 346 case ICACHE_POLICY_VPIPT: 347 set_bit(ICACHEF_VPIPT, &__icache_flags); 348 break; 349 case ICACHE_POLICY_RESERVED: 350 case ICACHE_POLICY_VIPT: 351 /* Assume aliasing */ 352 set_bit(ICACHEF_ALIASING, &__icache_flags); 353 break; 354 } 355 356 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); 357 } 358 359 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 360 { 361 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 362 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 363 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 364 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 365 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 366 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 367 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 368 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 369 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 370 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 371 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 372 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 373 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 374 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 375 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 376 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 377 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 378 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 379 380 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 381 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 382 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 383 } 384 385 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 386 { 387 info->reg_cntfrq = arch_timer_get_cntfrq(); 388 /* 389 * Use the effective value of the CTR_EL0 than the raw value 390 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 391 * with the CLIDR_EL1 fields to avoid triggering false warnings 392 * when there is a mismatch across the CPUs. Keep track of the 393 * effective value of the CTR_EL0 in our internal records for 394 * accurate sanity check and feature enablement. 395 */ 396 info->reg_ctr = read_cpuid_effective_cachetype(); 397 info->reg_dczid = read_cpuid(DCZID_EL0); 398 info->reg_midr = read_cpuid_id(); 399 info->reg_revidr = read_cpuid(REVIDR_EL1); 400 401 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 402 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 403 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 404 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 405 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 406 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 407 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 408 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 409 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 410 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 411 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 412 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); 413 414 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 415 info->reg_gmid = read_cpuid(GMID_EL1); 416 417 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 418 __cpuinfo_store_cpu_32bit(&info->aarch32); 419 420 if (IS_ENABLED(CONFIG_ARM64_SVE) && 421 id_aa64pfr0_sve(info->reg_id_aa64pfr0)) 422 info->reg_zcr = read_zcr_features(); 423 424 if (IS_ENABLED(CONFIG_ARM64_SME) && 425 id_aa64pfr1_sme(info->reg_id_aa64pfr1)) 426 info->reg_smcr = read_smcr_features(); 427 428 cpuinfo_detect_icache_policy(info); 429 } 430 431 void cpuinfo_store_cpu(void) 432 { 433 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 434 __cpuinfo_store_cpu(info); 435 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 436 } 437 438 void __init cpuinfo_store_boot_cpu(void) 439 { 440 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 441 __cpuinfo_store_cpu(info); 442 443 boot_cpu_data = *info; 444 init_cpu_features(&boot_cpu_data); 445 } 446