1 /* 2 * Record and handle CPU attributes. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 #include <asm/arch_timer.h> 18 #include <asm/cache.h> 19 #include <asm/cpu.h> 20 #include <asm/cputype.h> 21 #include <asm/cpufeature.h> 22 #include <asm/fpsimd.h> 23 24 #include <linux/bitops.h> 25 #include <linux/bug.h> 26 #include <linux/compat.h> 27 #include <linux/elf.h> 28 #include <linux/init.h> 29 #include <linux/kernel.h> 30 #include <linux/personality.h> 31 #include <linux/preempt.h> 32 #include <linux/printk.h> 33 #include <linux/seq_file.h> 34 #include <linux/sched.h> 35 #include <linux/smp.h> 36 #include <linux/delay.h> 37 38 /* 39 * In case the boot CPU is hotpluggable, we record its initial state and 40 * current state separately. Certain system registers may contain different 41 * values depending on configuration at or after reset. 42 */ 43 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 44 static struct cpuinfo_arm64 boot_cpu_data; 45 46 static char *icache_policy_str[] = { 47 [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN", 48 [ICACHE_POLICY_VIPT] = "VIPT", 49 [ICACHE_POLICY_PIPT] = "PIPT", 50 [ICACHE_POLICY_VPIPT] = "VPIPT", 51 }; 52 53 unsigned long __icache_flags; 54 55 static const char *const hwcap_str[] = { 56 "fp", 57 "asimd", 58 "evtstrm", 59 "aes", 60 "pmull", 61 "sha1", 62 "sha2", 63 "crc32", 64 "atomics", 65 "fphp", 66 "asimdhp", 67 "cpuid", 68 "asimdrdm", 69 "jscvt", 70 "fcma", 71 "lrcpc", 72 "dcpop", 73 "sha3", 74 "sm3", 75 "sm4", 76 "asimddp", 77 "sha512", 78 "sve", 79 NULL 80 }; 81 82 #ifdef CONFIG_COMPAT 83 static const char *const compat_hwcap_str[] = { 84 "swp", 85 "half", 86 "thumb", 87 "26bit", 88 "fastmult", 89 "fpa", 90 "vfp", 91 "edsp", 92 "java", 93 "iwmmxt", 94 "crunch", 95 "thumbee", 96 "neon", 97 "vfpv3", 98 "vfpv3d16", 99 "tls", 100 "vfpv4", 101 "idiva", 102 "idivt", 103 "vfpd32", 104 "lpae", 105 "evtstrm", 106 NULL 107 }; 108 109 static const char *const compat_hwcap2_str[] = { 110 "aes", 111 "pmull", 112 "sha1", 113 "sha2", 114 "crc32", 115 NULL 116 }; 117 #endif /* CONFIG_COMPAT */ 118 119 static int c_show(struct seq_file *m, void *v) 120 { 121 int i, j; 122 bool compat = personality(current->personality) == PER_LINUX32; 123 124 for_each_online_cpu(i) { 125 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 126 u32 midr = cpuinfo->reg_midr; 127 128 /* 129 * glibc reads /proc/cpuinfo to determine the number of 130 * online processors, looking for lines beginning with 131 * "processor". Give glibc what it expects. 132 */ 133 seq_printf(m, "processor\t: %d\n", i); 134 if (compat) 135 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 136 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 137 138 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 139 loops_per_jiffy / (500000UL/HZ), 140 loops_per_jiffy / (5000UL/HZ) % 100); 141 142 /* 143 * Dump out the common processor features in a single line. 144 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 145 * rather than attempting to parse this, but there's a body of 146 * software which does already (at least for 32-bit). 147 */ 148 seq_puts(m, "Features\t:"); 149 if (compat) { 150 #ifdef CONFIG_COMPAT 151 for (j = 0; compat_hwcap_str[j]; j++) 152 if (compat_elf_hwcap & (1 << j)) 153 seq_printf(m, " %s", compat_hwcap_str[j]); 154 155 for (j = 0; compat_hwcap2_str[j]; j++) 156 if (compat_elf_hwcap2 & (1 << j)) 157 seq_printf(m, " %s", compat_hwcap2_str[j]); 158 #endif /* CONFIG_COMPAT */ 159 } else { 160 for (j = 0; hwcap_str[j]; j++) 161 if (elf_hwcap & (1 << j)) 162 seq_printf(m, " %s", hwcap_str[j]); 163 } 164 seq_puts(m, "\n"); 165 166 seq_printf(m, "CPU implementer\t: 0x%02x\n", 167 MIDR_IMPLEMENTOR(midr)); 168 seq_printf(m, "CPU architecture: 8\n"); 169 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 170 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 171 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 172 } 173 174 return 0; 175 } 176 177 static void *c_start(struct seq_file *m, loff_t *pos) 178 { 179 return *pos < 1 ? (void *)1 : NULL; 180 } 181 182 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 183 { 184 ++*pos; 185 return NULL; 186 } 187 188 static void c_stop(struct seq_file *m, void *v) 189 { 190 } 191 192 const struct seq_operations cpuinfo_op = { 193 .start = c_start, 194 .next = c_next, 195 .stop = c_stop, 196 .show = c_show 197 }; 198 199 200 static struct kobj_type cpuregs_kobj_type = { 201 .sysfs_ops = &kobj_sysfs_ops, 202 }; 203 204 /* 205 * The ARM ARM uses the phrase "32-bit register" to describe a register 206 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 207 * no statement is made as to whether the upper 32 bits will or will not 208 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 209 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 210 * 211 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 212 * registers, we expose them both as 64 bit values to cater for possible 213 * future expansion without an ABI break. 214 */ 215 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 216 #define CPUREGS_ATTR_RO(_name, _field) \ 217 static ssize_t _name##_show(struct kobject *kobj, \ 218 struct kobj_attribute *attr, char *buf) \ 219 { \ 220 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 221 \ 222 if (info->reg_midr) \ 223 return sprintf(buf, "0x%016x\n", info->reg_##_field); \ 224 else \ 225 return 0; \ 226 } \ 227 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 228 229 CPUREGS_ATTR_RO(midr_el1, midr); 230 CPUREGS_ATTR_RO(revidr_el1, revidr); 231 232 static struct attribute *cpuregs_id_attrs[] = { 233 &cpuregs_attr_midr_el1.attr, 234 &cpuregs_attr_revidr_el1.attr, 235 NULL 236 }; 237 238 static const struct attribute_group cpuregs_attr_group = { 239 .attrs = cpuregs_id_attrs, 240 .name = "identification" 241 }; 242 243 static int cpuid_cpu_online(unsigned int cpu) 244 { 245 int rc; 246 struct device *dev; 247 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 248 249 dev = get_cpu_device(cpu); 250 if (!dev) { 251 rc = -ENODEV; 252 goto out; 253 } 254 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 255 if (rc) 256 goto out; 257 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 258 if (rc) 259 kobject_del(&info->kobj); 260 out: 261 return rc; 262 } 263 264 static int cpuid_cpu_offline(unsigned int cpu) 265 { 266 struct device *dev; 267 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 268 269 dev = get_cpu_device(cpu); 270 if (!dev) 271 return -ENODEV; 272 if (info->kobj.parent) { 273 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 274 kobject_del(&info->kobj); 275 } 276 277 return 0; 278 } 279 280 static int __init cpuinfo_regs_init(void) 281 { 282 int cpu, ret; 283 284 for_each_possible_cpu(cpu) { 285 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 286 287 kobject_init(&info->kobj, &cpuregs_kobj_type); 288 } 289 290 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 291 cpuid_cpu_online, cpuid_cpu_offline); 292 if (ret < 0) { 293 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 294 return ret; 295 } 296 return 0; 297 } 298 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 299 { 300 unsigned int cpu = smp_processor_id(); 301 u32 l1ip = CTR_L1IP(info->reg_ctr); 302 303 switch (l1ip) { 304 case ICACHE_POLICY_PIPT: 305 break; 306 case ICACHE_POLICY_VPIPT: 307 set_bit(ICACHEF_VPIPT, &__icache_flags); 308 break; 309 default: 310 /* Fallthrough */ 311 case ICACHE_POLICY_VIPT: 312 /* Assume aliasing */ 313 set_bit(ICACHEF_ALIASING, &__icache_flags); 314 } 315 316 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); 317 } 318 319 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 320 { 321 info->reg_cntfrq = arch_timer_get_cntfrq(); 322 info->reg_ctr = read_cpuid_cachetype(); 323 info->reg_dczid = read_cpuid(DCZID_EL0); 324 info->reg_midr = read_cpuid_id(); 325 info->reg_revidr = read_cpuid(REVIDR_EL1); 326 327 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 328 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 329 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 330 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 331 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 332 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 333 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 334 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 335 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 336 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 337 338 /* Update the 32bit ID registers only if AArch32 is implemented */ 339 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 340 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 341 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 342 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 343 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 344 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 345 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 346 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 347 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 348 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 349 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 350 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 351 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 352 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 353 354 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 355 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 356 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 357 } 358 359 if (IS_ENABLED(CONFIG_ARM64_SVE) && 360 id_aa64pfr0_sve(info->reg_id_aa64pfr0)) 361 info->reg_zcr = read_zcr_features(); 362 363 cpuinfo_detect_icache_policy(info); 364 } 365 366 void cpuinfo_store_cpu(void) 367 { 368 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 369 __cpuinfo_store_cpu(info); 370 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 371 } 372 373 void __init cpuinfo_store_boot_cpu(void) 374 { 375 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 376 __cpuinfo_store_cpu(info); 377 378 boot_cpu_data = *info; 379 init_cpu_features(&boot_cpu_data); 380 } 381 382 device_initcall(cpuinfo_regs_init); 383