1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static inline const char *icache_policy_str(int l1ip) 37 { 38 switch (l1ip) { 39 case CTR_EL0_L1Ip_VPIPT: 40 return "VPIPT"; 41 case CTR_EL0_L1Ip_VIPT: 42 return "VIPT"; 43 case CTR_EL0_L1Ip_PIPT: 44 return "PIPT"; 45 default: 46 return "RESERVED/UNKNOWN"; 47 } 48 } 49 50 unsigned long __icache_flags; 51 52 static const char *const hwcap_str[] = { 53 [KERNEL_HWCAP_FP] = "fp", 54 [KERNEL_HWCAP_ASIMD] = "asimd", 55 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 56 [KERNEL_HWCAP_AES] = "aes", 57 [KERNEL_HWCAP_PMULL] = "pmull", 58 [KERNEL_HWCAP_SHA1] = "sha1", 59 [KERNEL_HWCAP_SHA2] = "sha2", 60 [KERNEL_HWCAP_CRC32] = "crc32", 61 [KERNEL_HWCAP_ATOMICS] = "atomics", 62 [KERNEL_HWCAP_FPHP] = "fphp", 63 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 64 [KERNEL_HWCAP_CPUID] = "cpuid", 65 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 66 [KERNEL_HWCAP_JSCVT] = "jscvt", 67 [KERNEL_HWCAP_FCMA] = "fcma", 68 [KERNEL_HWCAP_LRCPC] = "lrcpc", 69 [KERNEL_HWCAP_DCPOP] = "dcpop", 70 [KERNEL_HWCAP_SHA3] = "sha3", 71 [KERNEL_HWCAP_SM3] = "sm3", 72 [KERNEL_HWCAP_SM4] = "sm4", 73 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 74 [KERNEL_HWCAP_SHA512] = "sha512", 75 [KERNEL_HWCAP_SVE] = "sve", 76 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 77 [KERNEL_HWCAP_DIT] = "dit", 78 [KERNEL_HWCAP_USCAT] = "uscat", 79 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 80 [KERNEL_HWCAP_FLAGM] = "flagm", 81 [KERNEL_HWCAP_SSBS] = "ssbs", 82 [KERNEL_HWCAP_SB] = "sb", 83 [KERNEL_HWCAP_PACA] = "paca", 84 [KERNEL_HWCAP_PACG] = "pacg", 85 [KERNEL_HWCAP_DCPODP] = "dcpodp", 86 [KERNEL_HWCAP_SVE2] = "sve2", 87 [KERNEL_HWCAP_SVEAES] = "sveaes", 88 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 90 [KERNEL_HWCAP_SVESHA3] = "svesha3", 91 [KERNEL_HWCAP_SVESM4] = "svesm4", 92 [KERNEL_HWCAP_FLAGM2] = "flagm2", 93 [KERNEL_HWCAP_FRINT] = "frint", 94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 97 [KERNEL_HWCAP_SVEBF16] = "svebf16", 98 [KERNEL_HWCAP_I8MM] = "i8mm", 99 [KERNEL_HWCAP_BF16] = "bf16", 100 [KERNEL_HWCAP_DGH] = "dgh", 101 [KERNEL_HWCAP_RNG] = "rng", 102 [KERNEL_HWCAP_BTI] = "bti", 103 [KERNEL_HWCAP_MTE] = "mte", 104 [KERNEL_HWCAP_ECV] = "ecv", 105 [KERNEL_HWCAP_AFP] = "afp", 106 [KERNEL_HWCAP_RPRES] = "rpres", 107 [KERNEL_HWCAP_MTE3] = "mte3", 108 [KERNEL_HWCAP_SME] = "sme", 109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 115 [KERNEL_HWCAP_SME_FA64] = "smefa64", 116 [KERNEL_HWCAP_WFXT] = "wfxt", 117 [KERNEL_HWCAP_EBF16] = "ebf16", 118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", 119 [KERNEL_HWCAP_CSSC] = "cssc", 120 [KERNEL_HWCAP_RPRFM] = "rprfm", 121 }; 122 123 #ifdef CONFIG_COMPAT 124 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 125 static const char *const compat_hwcap_str[] = { 126 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 127 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 128 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 129 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 130 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 131 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 132 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 133 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 134 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 135 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 136 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 137 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 138 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 139 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 140 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 141 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 142 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 143 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 144 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 145 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 146 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 147 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 148 }; 149 150 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 151 static const char *const compat_hwcap2_str[] = { 152 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 153 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 154 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 155 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 156 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 157 }; 158 #endif /* CONFIG_COMPAT */ 159 160 static int c_show(struct seq_file *m, void *v) 161 { 162 int i, j; 163 bool compat = personality(current->personality) == PER_LINUX32; 164 165 for_each_online_cpu(i) { 166 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 167 u32 midr = cpuinfo->reg_midr; 168 169 /* 170 * glibc reads /proc/cpuinfo to determine the number of 171 * online processors, looking for lines beginning with 172 * "processor". Give glibc what it expects. 173 */ 174 seq_printf(m, "processor\t: %d\n", i); 175 if (compat) 176 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 177 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 178 179 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 180 loops_per_jiffy / (500000UL/HZ), 181 loops_per_jiffy / (5000UL/HZ) % 100); 182 183 /* 184 * Dump out the common processor features in a single line. 185 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 186 * rather than attempting to parse this, but there's a body of 187 * software which does already (at least for 32-bit). 188 */ 189 seq_puts(m, "Features\t:"); 190 if (compat) { 191 #ifdef CONFIG_COMPAT 192 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 193 if (compat_elf_hwcap & (1 << j)) { 194 /* 195 * Warn once if any feature should not 196 * have been present on arm64 platform. 197 */ 198 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 199 continue; 200 201 seq_printf(m, " %s", compat_hwcap_str[j]); 202 } 203 } 204 205 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 206 if (compat_elf_hwcap2 & (1 << j)) 207 seq_printf(m, " %s", compat_hwcap2_str[j]); 208 #endif /* CONFIG_COMPAT */ 209 } else { 210 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 211 if (cpu_have_feature(j)) 212 seq_printf(m, " %s", hwcap_str[j]); 213 } 214 seq_puts(m, "\n"); 215 216 seq_printf(m, "CPU implementer\t: 0x%02x\n", 217 MIDR_IMPLEMENTOR(midr)); 218 seq_printf(m, "CPU architecture: 8\n"); 219 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 220 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 221 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 222 } 223 224 return 0; 225 } 226 227 static void *c_start(struct seq_file *m, loff_t *pos) 228 { 229 return *pos < 1 ? (void *)1 : NULL; 230 } 231 232 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 233 { 234 ++*pos; 235 return NULL; 236 } 237 238 static void c_stop(struct seq_file *m, void *v) 239 { 240 } 241 242 const struct seq_operations cpuinfo_op = { 243 .start = c_start, 244 .next = c_next, 245 .stop = c_stop, 246 .show = c_show 247 }; 248 249 250 static struct kobj_type cpuregs_kobj_type = { 251 .sysfs_ops = &kobj_sysfs_ops, 252 }; 253 254 /* 255 * The ARM ARM uses the phrase "32-bit register" to describe a register 256 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 257 * no statement is made as to whether the upper 32 bits will or will not 258 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 259 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 260 * 261 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 262 * registers, we expose them both as 64 bit values to cater for possible 263 * future expansion without an ABI break. 264 */ 265 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 266 #define CPUREGS_ATTR_RO(_name, _field) \ 267 static ssize_t _name##_show(struct kobject *kobj, \ 268 struct kobj_attribute *attr, char *buf) \ 269 { \ 270 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 271 \ 272 if (info->reg_midr) \ 273 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 274 else \ 275 return 0; \ 276 } \ 277 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 278 279 CPUREGS_ATTR_RO(midr_el1, midr); 280 CPUREGS_ATTR_RO(revidr_el1, revidr); 281 CPUREGS_ATTR_RO(smidr_el1, smidr); 282 283 static struct attribute *cpuregs_id_attrs[] = { 284 &cpuregs_attr_midr_el1.attr, 285 &cpuregs_attr_revidr_el1.attr, 286 NULL 287 }; 288 289 static const struct attribute_group cpuregs_attr_group = { 290 .attrs = cpuregs_id_attrs, 291 .name = "identification" 292 }; 293 294 static struct attribute *sme_cpuregs_id_attrs[] = { 295 &cpuregs_attr_smidr_el1.attr, 296 NULL 297 }; 298 299 static const struct attribute_group sme_cpuregs_attr_group = { 300 .attrs = sme_cpuregs_id_attrs, 301 .name = "identification" 302 }; 303 304 static int cpuid_cpu_online(unsigned int cpu) 305 { 306 int rc; 307 struct device *dev; 308 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 309 310 dev = get_cpu_device(cpu); 311 if (!dev) { 312 rc = -ENODEV; 313 goto out; 314 } 315 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 316 if (rc) 317 goto out; 318 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 319 if (rc) 320 kobject_del(&info->kobj); 321 if (system_supports_sme()) 322 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group); 323 out: 324 return rc; 325 } 326 327 static int cpuid_cpu_offline(unsigned int cpu) 328 { 329 struct device *dev; 330 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 331 332 dev = get_cpu_device(cpu); 333 if (!dev) 334 return -ENODEV; 335 if (info->kobj.parent) { 336 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 337 kobject_del(&info->kobj); 338 } 339 340 return 0; 341 } 342 343 static int __init cpuinfo_regs_init(void) 344 { 345 int cpu, ret; 346 347 for_each_possible_cpu(cpu) { 348 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 349 350 kobject_init(&info->kobj, &cpuregs_kobj_type); 351 } 352 353 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 354 cpuid_cpu_online, cpuid_cpu_offline); 355 if (ret < 0) { 356 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 357 return ret; 358 } 359 return 0; 360 } 361 device_initcall(cpuinfo_regs_init); 362 363 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 364 { 365 unsigned int cpu = smp_processor_id(); 366 u32 l1ip = CTR_L1IP(info->reg_ctr); 367 368 switch (l1ip) { 369 case CTR_EL0_L1Ip_PIPT: 370 break; 371 case CTR_EL0_L1Ip_VPIPT: 372 set_bit(ICACHEF_VPIPT, &__icache_flags); 373 break; 374 case CTR_EL0_L1Ip_VIPT: 375 default: 376 /* Assume aliasing */ 377 set_bit(ICACHEF_ALIASING, &__icache_flags); 378 break; 379 } 380 381 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); 382 } 383 384 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 385 { 386 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 387 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 388 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 389 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 390 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 391 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 392 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 393 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 394 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 395 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 396 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 397 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 398 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 399 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 400 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 401 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 402 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 403 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 404 405 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 406 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 407 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 408 } 409 410 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 411 { 412 info->reg_cntfrq = arch_timer_get_cntfrq(); 413 /* 414 * Use the effective value of the CTR_EL0 than the raw value 415 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 416 * with the CLIDR_EL1 fields to avoid triggering false warnings 417 * when there is a mismatch across the CPUs. Keep track of the 418 * effective value of the CTR_EL0 in our internal records for 419 * accurate sanity check and feature enablement. 420 */ 421 info->reg_ctr = read_cpuid_effective_cachetype(); 422 info->reg_dczid = read_cpuid(DCZID_EL0); 423 info->reg_midr = read_cpuid_id(); 424 info->reg_revidr = read_cpuid(REVIDR_EL1); 425 426 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 427 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 428 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 429 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 430 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 431 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 432 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 433 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 434 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 435 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 436 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 437 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); 438 439 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 440 info->reg_gmid = read_cpuid(GMID_EL1); 441 442 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 443 __cpuinfo_store_cpu_32bit(&info->aarch32); 444 445 cpuinfo_detect_icache_policy(info); 446 } 447 448 void cpuinfo_store_cpu(void) 449 { 450 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 451 __cpuinfo_store_cpu(info); 452 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 453 } 454 455 void __init cpuinfo_store_boot_cpu(void) 456 { 457 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 458 __cpuinfo_store_cpu(info); 459 460 boot_cpu_data = *info; 461 init_cpu_features(&boot_cpu_data); 462 } 463