1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static inline const char *icache_policy_str(int l1ip) 37 { 38 switch (l1ip) { 39 case CTR_EL0_L1Ip_VPIPT: 40 return "VPIPT"; 41 case CTR_EL0_L1Ip_VIPT: 42 return "VIPT"; 43 case CTR_EL0_L1Ip_PIPT: 44 return "PIPT"; 45 default: 46 return "RESERVED/UNKNOWN"; 47 } 48 } 49 50 unsigned long __icache_flags; 51 52 static const char *const hwcap_str[] = { 53 [KERNEL_HWCAP_FP] = "fp", 54 [KERNEL_HWCAP_ASIMD] = "asimd", 55 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 56 [KERNEL_HWCAP_AES] = "aes", 57 [KERNEL_HWCAP_PMULL] = "pmull", 58 [KERNEL_HWCAP_SHA1] = "sha1", 59 [KERNEL_HWCAP_SHA2] = "sha2", 60 [KERNEL_HWCAP_CRC32] = "crc32", 61 [KERNEL_HWCAP_ATOMICS] = "atomics", 62 [KERNEL_HWCAP_FPHP] = "fphp", 63 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 64 [KERNEL_HWCAP_CPUID] = "cpuid", 65 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 66 [KERNEL_HWCAP_JSCVT] = "jscvt", 67 [KERNEL_HWCAP_FCMA] = "fcma", 68 [KERNEL_HWCAP_LRCPC] = "lrcpc", 69 [KERNEL_HWCAP_DCPOP] = "dcpop", 70 [KERNEL_HWCAP_SHA3] = "sha3", 71 [KERNEL_HWCAP_SM3] = "sm3", 72 [KERNEL_HWCAP_SM4] = "sm4", 73 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 74 [KERNEL_HWCAP_SHA512] = "sha512", 75 [KERNEL_HWCAP_SVE] = "sve", 76 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 77 [KERNEL_HWCAP_DIT] = "dit", 78 [KERNEL_HWCAP_USCAT] = "uscat", 79 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 80 [KERNEL_HWCAP_FLAGM] = "flagm", 81 [KERNEL_HWCAP_SSBS] = "ssbs", 82 [KERNEL_HWCAP_SB] = "sb", 83 [KERNEL_HWCAP_PACA] = "paca", 84 [KERNEL_HWCAP_PACG] = "pacg", 85 [KERNEL_HWCAP_DCPODP] = "dcpodp", 86 [KERNEL_HWCAP_SVE2] = "sve2", 87 [KERNEL_HWCAP_SVEAES] = "sveaes", 88 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 90 [KERNEL_HWCAP_SVESHA3] = "svesha3", 91 [KERNEL_HWCAP_SVESM4] = "svesm4", 92 [KERNEL_HWCAP_FLAGM2] = "flagm2", 93 [KERNEL_HWCAP_FRINT] = "frint", 94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 97 [KERNEL_HWCAP_SVEBF16] = "svebf16", 98 [KERNEL_HWCAP_I8MM] = "i8mm", 99 [KERNEL_HWCAP_BF16] = "bf16", 100 [KERNEL_HWCAP_DGH] = "dgh", 101 [KERNEL_HWCAP_RNG] = "rng", 102 [KERNEL_HWCAP_BTI] = "bti", 103 [KERNEL_HWCAP_MTE] = "mte", 104 [KERNEL_HWCAP_ECV] = "ecv", 105 [KERNEL_HWCAP_AFP] = "afp", 106 [KERNEL_HWCAP_RPRES] = "rpres", 107 [KERNEL_HWCAP_MTE3] = "mte3", 108 [KERNEL_HWCAP_SME] = "sme", 109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 115 [KERNEL_HWCAP_SME_FA64] = "smefa64", 116 [KERNEL_HWCAP_WFXT] = "wfxt", 117 [KERNEL_HWCAP_EBF16] = "ebf16", 118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", 119 [KERNEL_HWCAP_CSSC] = "cssc", 120 [KERNEL_HWCAP_RPRFM] = "rprfm", 121 [KERNEL_HWCAP_SVE2P1] = "sve2p1", 122 [KERNEL_HWCAP_SME2] = "sme2", 123 [KERNEL_HWCAP_SME2P1] = "sme2p1", 124 [KERNEL_HWCAP_SME_I16I32] = "smei16i32", 125 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32", 126 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", 127 [KERNEL_HWCAP_SME_F16F16] = "smef16f16", 128 [KERNEL_HWCAP_MOPS] = "mops", 129 }; 130 131 #ifdef CONFIG_COMPAT 132 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 133 static const char *const compat_hwcap_str[] = { 134 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 135 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 136 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 137 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 138 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 139 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 140 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 141 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 142 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 143 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 144 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 145 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 146 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 147 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 148 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 149 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 150 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 151 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 152 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 153 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 154 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 155 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 156 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp", 157 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp", 158 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp", 159 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm", 160 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16", 161 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm", 162 }; 163 164 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 165 static const char *const compat_hwcap2_str[] = { 166 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 167 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 168 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 169 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 170 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 171 [COMPAT_KERNEL_HWCAP2(SB)] = "sb", 172 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs", 173 }; 174 #endif /* CONFIG_COMPAT */ 175 176 static int c_show(struct seq_file *m, void *v) 177 { 178 int i, j; 179 bool compat = personality(current->personality) == PER_LINUX32; 180 181 for_each_online_cpu(i) { 182 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 183 u32 midr = cpuinfo->reg_midr; 184 185 /* 186 * glibc reads /proc/cpuinfo to determine the number of 187 * online processors, looking for lines beginning with 188 * "processor". Give glibc what it expects. 189 */ 190 seq_printf(m, "processor\t: %d\n", i); 191 if (compat) 192 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 193 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 194 195 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 196 loops_per_jiffy / (500000UL/HZ), 197 loops_per_jiffy / (5000UL/HZ) % 100); 198 199 /* 200 * Dump out the common processor features in a single line. 201 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 202 * rather than attempting to parse this, but there's a body of 203 * software which does already (at least for 32-bit). 204 */ 205 seq_puts(m, "Features\t:"); 206 if (compat) { 207 #ifdef CONFIG_COMPAT 208 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 209 if (compat_elf_hwcap & (1 << j)) { 210 /* 211 * Warn once if any feature should not 212 * have been present on arm64 platform. 213 */ 214 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 215 continue; 216 217 seq_printf(m, " %s", compat_hwcap_str[j]); 218 } 219 } 220 221 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 222 if (compat_elf_hwcap2 & (1 << j)) 223 seq_printf(m, " %s", compat_hwcap2_str[j]); 224 #endif /* CONFIG_COMPAT */ 225 } else { 226 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 227 if (cpu_have_feature(j)) 228 seq_printf(m, " %s", hwcap_str[j]); 229 } 230 seq_puts(m, "\n"); 231 232 seq_printf(m, "CPU implementer\t: 0x%02x\n", 233 MIDR_IMPLEMENTOR(midr)); 234 seq_printf(m, "CPU architecture: 8\n"); 235 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 236 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 237 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 238 } 239 240 return 0; 241 } 242 243 static void *c_start(struct seq_file *m, loff_t *pos) 244 { 245 return *pos < 1 ? (void *)1 : NULL; 246 } 247 248 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 249 { 250 ++*pos; 251 return NULL; 252 } 253 254 static void c_stop(struct seq_file *m, void *v) 255 { 256 } 257 258 const struct seq_operations cpuinfo_op = { 259 .start = c_start, 260 .next = c_next, 261 .stop = c_stop, 262 .show = c_show 263 }; 264 265 266 static struct kobj_type cpuregs_kobj_type = { 267 .sysfs_ops = &kobj_sysfs_ops, 268 }; 269 270 /* 271 * The ARM ARM uses the phrase "32-bit register" to describe a register 272 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 273 * no statement is made as to whether the upper 32 bits will or will not 274 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 275 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 276 * 277 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 278 * registers, we expose them both as 64 bit values to cater for possible 279 * future expansion without an ABI break. 280 */ 281 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 282 #define CPUREGS_ATTR_RO(_name, _field) \ 283 static ssize_t _name##_show(struct kobject *kobj, \ 284 struct kobj_attribute *attr, char *buf) \ 285 { \ 286 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 287 \ 288 if (info->reg_midr) \ 289 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 290 else \ 291 return 0; \ 292 } \ 293 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 294 295 CPUREGS_ATTR_RO(midr_el1, midr); 296 CPUREGS_ATTR_RO(revidr_el1, revidr); 297 CPUREGS_ATTR_RO(smidr_el1, smidr); 298 299 static struct attribute *cpuregs_id_attrs[] = { 300 &cpuregs_attr_midr_el1.attr, 301 &cpuregs_attr_revidr_el1.attr, 302 NULL 303 }; 304 305 static const struct attribute_group cpuregs_attr_group = { 306 .attrs = cpuregs_id_attrs, 307 .name = "identification" 308 }; 309 310 static struct attribute *sme_cpuregs_id_attrs[] = { 311 &cpuregs_attr_smidr_el1.attr, 312 NULL 313 }; 314 315 static const struct attribute_group sme_cpuregs_attr_group = { 316 .attrs = sme_cpuregs_id_attrs, 317 .name = "identification" 318 }; 319 320 static int cpuid_cpu_online(unsigned int cpu) 321 { 322 int rc; 323 struct device *dev; 324 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 325 326 dev = get_cpu_device(cpu); 327 if (!dev) { 328 rc = -ENODEV; 329 goto out; 330 } 331 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 332 if (rc) 333 goto out; 334 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 335 if (rc) 336 kobject_del(&info->kobj); 337 if (system_supports_sme()) 338 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group); 339 out: 340 return rc; 341 } 342 343 static int cpuid_cpu_offline(unsigned int cpu) 344 { 345 struct device *dev; 346 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 347 348 dev = get_cpu_device(cpu); 349 if (!dev) 350 return -ENODEV; 351 if (info->kobj.parent) { 352 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 353 kobject_del(&info->kobj); 354 } 355 356 return 0; 357 } 358 359 static int __init cpuinfo_regs_init(void) 360 { 361 int cpu, ret; 362 363 for_each_possible_cpu(cpu) { 364 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 365 366 kobject_init(&info->kobj, &cpuregs_kobj_type); 367 } 368 369 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 370 cpuid_cpu_online, cpuid_cpu_offline); 371 if (ret < 0) { 372 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 373 return ret; 374 } 375 return 0; 376 } 377 device_initcall(cpuinfo_regs_init); 378 379 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 380 { 381 unsigned int cpu = smp_processor_id(); 382 u32 l1ip = CTR_L1IP(info->reg_ctr); 383 384 switch (l1ip) { 385 case CTR_EL0_L1Ip_PIPT: 386 break; 387 case CTR_EL0_L1Ip_VPIPT: 388 set_bit(ICACHEF_VPIPT, &__icache_flags); 389 break; 390 case CTR_EL0_L1Ip_VIPT: 391 default: 392 /* Assume aliasing */ 393 set_bit(ICACHEF_ALIASING, &__icache_flags); 394 break; 395 } 396 397 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); 398 } 399 400 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 401 { 402 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 403 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 404 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 405 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 406 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 407 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 408 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 409 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 410 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 411 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 412 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 413 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 414 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 415 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 416 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 417 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 418 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 419 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 420 421 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 422 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 423 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 424 } 425 426 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 427 { 428 info->reg_cntfrq = arch_timer_get_cntfrq(); 429 /* 430 * Use the effective value of the CTR_EL0 than the raw value 431 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 432 * with the CLIDR_EL1 fields to avoid triggering false warnings 433 * when there is a mismatch across the CPUs. Keep track of the 434 * effective value of the CTR_EL0 in our internal records for 435 * accurate sanity check and feature enablement. 436 */ 437 info->reg_ctr = read_cpuid_effective_cachetype(); 438 info->reg_dczid = read_cpuid(DCZID_EL0); 439 info->reg_midr = read_cpuid_id(); 440 info->reg_revidr = read_cpuid(REVIDR_EL1); 441 442 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 443 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 444 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 445 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 446 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 447 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 448 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 449 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 450 info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1); 451 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 452 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 453 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 454 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); 455 456 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 457 info->reg_gmid = read_cpuid(GMID_EL1); 458 459 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 460 __cpuinfo_store_cpu_32bit(&info->aarch32); 461 462 cpuinfo_detect_icache_policy(info); 463 } 464 465 void cpuinfo_store_cpu(void) 466 { 467 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 468 __cpuinfo_store_cpu(info); 469 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 470 } 471 472 void __init cpuinfo_store_boot_cpu(void) 473 { 474 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 475 __cpuinfo_store_cpu(info); 476 477 boot_cpu_data = *info; 478 init_cpu_features(&boot_cpu_data); 479 } 480