1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static const char *icache_policy_str[] = { 37 [ICACHE_POLICY_VPIPT] = "VPIPT", 38 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", 39 [ICACHE_POLICY_VIPT] = "VIPT", 40 [ICACHE_POLICY_PIPT] = "PIPT", 41 }; 42 43 unsigned long __icache_flags; 44 45 static const char *const hwcap_str[] = { 46 [KERNEL_HWCAP_FP] = "fp", 47 [KERNEL_HWCAP_ASIMD] = "asimd", 48 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 49 [KERNEL_HWCAP_AES] = "aes", 50 [KERNEL_HWCAP_PMULL] = "pmull", 51 [KERNEL_HWCAP_SHA1] = "sha1", 52 [KERNEL_HWCAP_SHA2] = "sha2", 53 [KERNEL_HWCAP_CRC32] = "crc32", 54 [KERNEL_HWCAP_ATOMICS] = "atomics", 55 [KERNEL_HWCAP_FPHP] = "fphp", 56 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 57 [KERNEL_HWCAP_CPUID] = "cpuid", 58 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 59 [KERNEL_HWCAP_JSCVT] = "jscvt", 60 [KERNEL_HWCAP_FCMA] = "fcma", 61 [KERNEL_HWCAP_LRCPC] = "lrcpc", 62 [KERNEL_HWCAP_DCPOP] = "dcpop", 63 [KERNEL_HWCAP_SHA3] = "sha3", 64 [KERNEL_HWCAP_SM3] = "sm3", 65 [KERNEL_HWCAP_SM4] = "sm4", 66 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 67 [KERNEL_HWCAP_SHA512] = "sha512", 68 [KERNEL_HWCAP_SVE] = "sve", 69 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 70 [KERNEL_HWCAP_DIT] = "dit", 71 [KERNEL_HWCAP_USCAT] = "uscat", 72 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 73 [KERNEL_HWCAP_FLAGM] = "flagm", 74 [KERNEL_HWCAP_SSBS] = "ssbs", 75 [KERNEL_HWCAP_SB] = "sb", 76 [KERNEL_HWCAP_PACA] = "paca", 77 [KERNEL_HWCAP_PACG] = "pacg", 78 [KERNEL_HWCAP_DCPODP] = "dcpodp", 79 [KERNEL_HWCAP_SVE2] = "sve2", 80 [KERNEL_HWCAP_SVEAES] = "sveaes", 81 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 82 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 83 [KERNEL_HWCAP_SVESHA3] = "svesha3", 84 [KERNEL_HWCAP_SVESM4] = "svesm4", 85 [KERNEL_HWCAP_FLAGM2] = "flagm2", 86 [KERNEL_HWCAP_FRINT] = "frint", 87 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 88 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 89 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 90 [KERNEL_HWCAP_SVEBF16] = "svebf16", 91 [KERNEL_HWCAP_I8MM] = "i8mm", 92 [KERNEL_HWCAP_BF16] = "bf16", 93 [KERNEL_HWCAP_DGH] = "dgh", 94 [KERNEL_HWCAP_RNG] = "rng", 95 [KERNEL_HWCAP_BTI] = "bti", 96 [KERNEL_HWCAP_MTE] = "mte", 97 [KERNEL_HWCAP_ECV] = "ecv", 98 [KERNEL_HWCAP_AFP] = "afp", 99 [KERNEL_HWCAP_RPRES] = "rpres", 100 }; 101 102 #ifdef CONFIG_COMPAT 103 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 104 static const char *const compat_hwcap_str[] = { 105 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 106 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 107 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 108 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 109 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 110 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 111 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 112 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 113 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 114 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 115 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 116 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 117 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 118 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 119 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 120 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 121 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 122 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 123 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 124 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 125 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 126 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 127 }; 128 129 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 130 static const char *const compat_hwcap2_str[] = { 131 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 132 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 133 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 134 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 135 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 136 }; 137 #endif /* CONFIG_COMPAT */ 138 139 static int c_show(struct seq_file *m, void *v) 140 { 141 int i, j; 142 bool compat = personality(current->personality) == PER_LINUX32; 143 144 for_each_online_cpu(i) { 145 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 146 u32 midr = cpuinfo->reg_midr; 147 148 /* 149 * glibc reads /proc/cpuinfo to determine the number of 150 * online processors, looking for lines beginning with 151 * "processor". Give glibc what it expects. 152 */ 153 seq_printf(m, "processor\t: %d\n", i); 154 if (compat) 155 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 156 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 157 158 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 159 loops_per_jiffy / (500000UL/HZ), 160 loops_per_jiffy / (5000UL/HZ) % 100); 161 162 /* 163 * Dump out the common processor features in a single line. 164 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 165 * rather than attempting to parse this, but there's a body of 166 * software which does already (at least for 32-bit). 167 */ 168 seq_puts(m, "Features\t:"); 169 if (compat) { 170 #ifdef CONFIG_COMPAT 171 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 172 if (compat_elf_hwcap & (1 << j)) { 173 /* 174 * Warn once if any feature should not 175 * have been present on arm64 platform. 176 */ 177 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 178 continue; 179 180 seq_printf(m, " %s", compat_hwcap_str[j]); 181 } 182 } 183 184 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 185 if (compat_elf_hwcap2 & (1 << j)) 186 seq_printf(m, " %s", compat_hwcap2_str[j]); 187 #endif /* CONFIG_COMPAT */ 188 } else { 189 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 190 if (cpu_have_feature(j)) 191 seq_printf(m, " %s", hwcap_str[j]); 192 } 193 seq_puts(m, "\n"); 194 195 seq_printf(m, "CPU implementer\t: 0x%02x\n", 196 MIDR_IMPLEMENTOR(midr)); 197 seq_printf(m, "CPU architecture: 8\n"); 198 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 199 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 200 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 201 } 202 203 return 0; 204 } 205 206 static void *c_start(struct seq_file *m, loff_t *pos) 207 { 208 return *pos < 1 ? (void *)1 : NULL; 209 } 210 211 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 212 { 213 ++*pos; 214 return NULL; 215 } 216 217 static void c_stop(struct seq_file *m, void *v) 218 { 219 } 220 221 const struct seq_operations cpuinfo_op = { 222 .start = c_start, 223 .next = c_next, 224 .stop = c_stop, 225 .show = c_show 226 }; 227 228 229 static struct kobj_type cpuregs_kobj_type = { 230 .sysfs_ops = &kobj_sysfs_ops, 231 }; 232 233 /* 234 * The ARM ARM uses the phrase "32-bit register" to describe a register 235 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 236 * no statement is made as to whether the upper 32 bits will or will not 237 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 238 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 239 * 240 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 241 * registers, we expose them both as 64 bit values to cater for possible 242 * future expansion without an ABI break. 243 */ 244 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 245 #define CPUREGS_ATTR_RO(_name, _field) \ 246 static ssize_t _name##_show(struct kobject *kobj, \ 247 struct kobj_attribute *attr, char *buf) \ 248 { \ 249 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 250 \ 251 if (info->reg_midr) \ 252 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 253 else \ 254 return 0; \ 255 } \ 256 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 257 258 CPUREGS_ATTR_RO(midr_el1, midr); 259 CPUREGS_ATTR_RO(revidr_el1, revidr); 260 261 static struct attribute *cpuregs_id_attrs[] = { 262 &cpuregs_attr_midr_el1.attr, 263 &cpuregs_attr_revidr_el1.attr, 264 NULL 265 }; 266 267 static const struct attribute_group cpuregs_attr_group = { 268 .attrs = cpuregs_id_attrs, 269 .name = "identification" 270 }; 271 272 static int cpuid_cpu_online(unsigned int cpu) 273 { 274 int rc; 275 struct device *dev; 276 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 277 278 dev = get_cpu_device(cpu); 279 if (!dev) { 280 rc = -ENODEV; 281 goto out; 282 } 283 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 284 if (rc) 285 goto out; 286 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 287 if (rc) 288 kobject_del(&info->kobj); 289 out: 290 return rc; 291 } 292 293 static int cpuid_cpu_offline(unsigned int cpu) 294 { 295 struct device *dev; 296 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 297 298 dev = get_cpu_device(cpu); 299 if (!dev) 300 return -ENODEV; 301 if (info->kobj.parent) { 302 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 303 kobject_del(&info->kobj); 304 } 305 306 return 0; 307 } 308 309 static int __init cpuinfo_regs_init(void) 310 { 311 int cpu, ret; 312 313 for_each_possible_cpu(cpu) { 314 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 315 316 kobject_init(&info->kobj, &cpuregs_kobj_type); 317 } 318 319 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 320 cpuid_cpu_online, cpuid_cpu_offline); 321 if (ret < 0) { 322 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 323 return ret; 324 } 325 return 0; 326 } 327 device_initcall(cpuinfo_regs_init); 328 329 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 330 { 331 unsigned int cpu = smp_processor_id(); 332 u32 l1ip = CTR_L1IP(info->reg_ctr); 333 334 switch (l1ip) { 335 case ICACHE_POLICY_PIPT: 336 break; 337 case ICACHE_POLICY_VPIPT: 338 set_bit(ICACHEF_VPIPT, &__icache_flags); 339 break; 340 case ICACHE_POLICY_RESERVED: 341 case ICACHE_POLICY_VIPT: 342 /* Assume aliasing */ 343 set_bit(ICACHEF_ALIASING, &__icache_flags); 344 break; 345 } 346 347 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); 348 } 349 350 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 351 { 352 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 353 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 354 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 355 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 356 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 357 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 358 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 359 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 360 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 361 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 362 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 363 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 364 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 365 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 366 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 367 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 368 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 369 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 370 371 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 372 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 373 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 374 } 375 376 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 377 { 378 info->reg_cntfrq = arch_timer_get_cntfrq(); 379 /* 380 * Use the effective value of the CTR_EL0 than the raw value 381 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 382 * with the CLIDR_EL1 fields to avoid triggering false warnings 383 * when there is a mismatch across the CPUs. Keep track of the 384 * effective value of the CTR_EL0 in our internal records for 385 * accurate sanity check and feature enablement. 386 */ 387 info->reg_ctr = read_cpuid_effective_cachetype(); 388 info->reg_dczid = read_cpuid(DCZID_EL0); 389 info->reg_midr = read_cpuid_id(); 390 info->reg_revidr = read_cpuid(REVIDR_EL1); 391 392 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 393 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 394 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 395 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 396 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 397 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 398 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 399 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 400 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 401 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 402 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 403 404 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 405 info->reg_gmid = read_cpuid(GMID_EL1); 406 407 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 408 __cpuinfo_store_cpu_32bit(&info->aarch32); 409 410 if (IS_ENABLED(CONFIG_ARM64_SVE) && 411 id_aa64pfr0_sve(info->reg_id_aa64pfr0)) 412 info->reg_zcr = read_zcr_features(); 413 414 cpuinfo_detect_icache_policy(info); 415 } 416 417 void cpuinfo_store_cpu(void) 418 { 419 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 420 __cpuinfo_store_cpu(info); 421 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 422 } 423 424 void __init cpuinfo_store_boot_cpu(void) 425 { 426 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 427 __cpuinfo_store_cpu(info); 428 429 boot_cpu_data = *info; 430 init_cpu_features(&boot_cpu_data); 431 } 432