xref: /openbmc/linux/arch/arm64/kernel/cpuinfo.c (revision 407e7517)
1 /*
2  * Record and handle CPU attributes.
3  *
4  * Copyright (C) 2014 ARM Ltd.
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17 #include <asm/arch_timer.h>
18 #include <asm/cache.h>
19 #include <asm/cpu.h>
20 #include <asm/cputype.h>
21 #include <asm/cpufeature.h>
22 #include <asm/fpsimd.h>
23 
24 #include <linux/bitops.h>
25 #include <linux/bug.h>
26 #include <linux/compat.h>
27 #include <linux/elf.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/personality.h>
31 #include <linux/preempt.h>
32 #include <linux/printk.h>
33 #include <linux/seq_file.h>
34 #include <linux/sched.h>
35 #include <linux/smp.h>
36 #include <linux/delay.h>
37 
38 /*
39  * In case the boot CPU is hotpluggable, we record its initial state and
40  * current state separately. Certain system registers may contain different
41  * values depending on configuration at or after reset.
42  */
43 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
44 static struct cpuinfo_arm64 boot_cpu_data;
45 
46 static char *icache_policy_str[] = {
47 	[0 ... ICACHE_POLICY_PIPT]	= "RESERVED/UNKNOWN",
48 	[ICACHE_POLICY_VIPT]		= "VIPT",
49 	[ICACHE_POLICY_PIPT]		= "PIPT",
50 	[ICACHE_POLICY_VPIPT]		= "VPIPT",
51 };
52 
53 unsigned long __icache_flags;
54 
55 static const char *const hwcap_str[] = {
56 	"fp",
57 	"asimd",
58 	"evtstrm",
59 	"aes",
60 	"pmull",
61 	"sha1",
62 	"sha2",
63 	"crc32",
64 	"atomics",
65 	"fphp",
66 	"asimdhp",
67 	"cpuid",
68 	"asimdrdm",
69 	"jscvt",
70 	"fcma",
71 	"lrcpc",
72 	"dcpop",
73 	"sha3",
74 	"sm3",
75 	"sm4",
76 	"asimddp",
77 	"sha512",
78 	"sve",
79 	"asimdfhm",
80 	NULL
81 };
82 
83 #ifdef CONFIG_COMPAT
84 static const char *const compat_hwcap_str[] = {
85 	"swp",
86 	"half",
87 	"thumb",
88 	"26bit",
89 	"fastmult",
90 	"fpa",
91 	"vfp",
92 	"edsp",
93 	"java",
94 	"iwmmxt",
95 	"crunch",
96 	"thumbee",
97 	"neon",
98 	"vfpv3",
99 	"vfpv3d16",
100 	"tls",
101 	"vfpv4",
102 	"idiva",
103 	"idivt",
104 	"vfpd32",
105 	"lpae",
106 	"evtstrm",
107 	NULL
108 };
109 
110 static const char *const compat_hwcap2_str[] = {
111 	"aes",
112 	"pmull",
113 	"sha1",
114 	"sha2",
115 	"crc32",
116 	NULL
117 };
118 #endif /* CONFIG_COMPAT */
119 
120 static int c_show(struct seq_file *m, void *v)
121 {
122 	int i, j;
123 	bool compat = personality(current->personality) == PER_LINUX32;
124 
125 	for_each_online_cpu(i) {
126 		struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
127 		u32 midr = cpuinfo->reg_midr;
128 
129 		/*
130 		 * glibc reads /proc/cpuinfo to determine the number of
131 		 * online processors, looking for lines beginning with
132 		 * "processor".  Give glibc what it expects.
133 		 */
134 		seq_printf(m, "processor\t: %d\n", i);
135 		if (compat)
136 			seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
137 				   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
138 
139 		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
140 			   loops_per_jiffy / (500000UL/HZ),
141 			   loops_per_jiffy / (5000UL/HZ) % 100);
142 
143 		/*
144 		 * Dump out the common processor features in a single line.
145 		 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
146 		 * rather than attempting to parse this, but there's a body of
147 		 * software which does already (at least for 32-bit).
148 		 */
149 		seq_puts(m, "Features\t:");
150 		if (compat) {
151 #ifdef CONFIG_COMPAT
152 			for (j = 0; compat_hwcap_str[j]; j++)
153 				if (compat_elf_hwcap & (1 << j))
154 					seq_printf(m, " %s", compat_hwcap_str[j]);
155 
156 			for (j = 0; compat_hwcap2_str[j]; j++)
157 				if (compat_elf_hwcap2 & (1 << j))
158 					seq_printf(m, " %s", compat_hwcap2_str[j]);
159 #endif /* CONFIG_COMPAT */
160 		} else {
161 			for (j = 0; hwcap_str[j]; j++)
162 				if (elf_hwcap & (1 << j))
163 					seq_printf(m, " %s", hwcap_str[j]);
164 		}
165 		seq_puts(m, "\n");
166 
167 		seq_printf(m, "CPU implementer\t: 0x%02x\n",
168 			   MIDR_IMPLEMENTOR(midr));
169 		seq_printf(m, "CPU architecture: 8\n");
170 		seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
171 		seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
172 		seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
173 	}
174 
175 	return 0;
176 }
177 
178 static void *c_start(struct seq_file *m, loff_t *pos)
179 {
180 	return *pos < 1 ? (void *)1 : NULL;
181 }
182 
183 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
184 {
185 	++*pos;
186 	return NULL;
187 }
188 
189 static void c_stop(struct seq_file *m, void *v)
190 {
191 }
192 
193 const struct seq_operations cpuinfo_op = {
194 	.start	= c_start,
195 	.next	= c_next,
196 	.stop	= c_stop,
197 	.show	= c_show
198 };
199 
200 
201 static struct kobj_type cpuregs_kobj_type = {
202 	.sysfs_ops = &kobj_sysfs_ops,
203 };
204 
205 /*
206  * The ARM ARM uses the phrase "32-bit register" to describe a register
207  * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
208  * no statement is made as to whether the upper 32 bits will or will not
209  * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
210  * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
211  *
212  * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
213  * registers, we expose them both as 64 bit values to cater for possible
214  * future expansion without an ABI break.
215  */
216 #define kobj_to_cpuinfo(kobj)	container_of(kobj, struct cpuinfo_arm64, kobj)
217 #define CPUREGS_ATTR_RO(_name, _field)						\
218 	static ssize_t _name##_show(struct kobject *kobj,			\
219 			struct kobj_attribute *attr, char *buf)			\
220 	{									\
221 		struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);		\
222 										\
223 		if (info->reg_midr)						\
224 			return sprintf(buf, "0x%016x\n", info->reg_##_field);	\
225 		else								\
226 			return 0;						\
227 	}									\
228 	static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
229 
230 CPUREGS_ATTR_RO(midr_el1, midr);
231 CPUREGS_ATTR_RO(revidr_el1, revidr);
232 
233 static struct attribute *cpuregs_id_attrs[] = {
234 	&cpuregs_attr_midr_el1.attr,
235 	&cpuregs_attr_revidr_el1.attr,
236 	NULL
237 };
238 
239 static const struct attribute_group cpuregs_attr_group = {
240 	.attrs = cpuregs_id_attrs,
241 	.name = "identification"
242 };
243 
244 static int cpuid_cpu_online(unsigned int cpu)
245 {
246 	int rc;
247 	struct device *dev;
248 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
249 
250 	dev = get_cpu_device(cpu);
251 	if (!dev) {
252 		rc = -ENODEV;
253 		goto out;
254 	}
255 	rc = kobject_add(&info->kobj, &dev->kobj, "regs");
256 	if (rc)
257 		goto out;
258 	rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
259 	if (rc)
260 		kobject_del(&info->kobj);
261 out:
262 	return rc;
263 }
264 
265 static int cpuid_cpu_offline(unsigned int cpu)
266 {
267 	struct device *dev;
268 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
269 
270 	dev = get_cpu_device(cpu);
271 	if (!dev)
272 		return -ENODEV;
273 	if (info->kobj.parent) {
274 		sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
275 		kobject_del(&info->kobj);
276 	}
277 
278 	return 0;
279 }
280 
281 static int __init cpuinfo_regs_init(void)
282 {
283 	int cpu, ret;
284 
285 	for_each_possible_cpu(cpu) {
286 		struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
287 
288 		kobject_init(&info->kobj, &cpuregs_kobj_type);
289 	}
290 
291 	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
292 				cpuid_cpu_online, cpuid_cpu_offline);
293 	if (ret < 0) {
294 		pr_err("cpuinfo: failed to register hotplug callbacks.\n");
295 		return ret;
296 	}
297 	return 0;
298 }
299 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
300 {
301 	unsigned int cpu = smp_processor_id();
302 	u32 l1ip = CTR_L1IP(info->reg_ctr);
303 
304 	switch (l1ip) {
305 	case ICACHE_POLICY_PIPT:
306 		break;
307 	case ICACHE_POLICY_VPIPT:
308 		set_bit(ICACHEF_VPIPT, &__icache_flags);
309 		break;
310 	default:
311 		/* Fallthrough */
312 	case ICACHE_POLICY_VIPT:
313 		/* Assume aliasing */
314 		set_bit(ICACHEF_ALIASING, &__icache_flags);
315 	}
316 
317 	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
318 }
319 
320 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
321 {
322 	info->reg_cntfrq = arch_timer_get_cntfrq();
323 	info->reg_ctr = read_cpuid_cachetype();
324 	info->reg_dczid = read_cpuid(DCZID_EL0);
325 	info->reg_midr = read_cpuid_id();
326 	info->reg_revidr = read_cpuid(REVIDR_EL1);
327 
328 	info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
329 	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
330 	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
331 	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
332 	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
333 	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
334 	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
335 	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
336 	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
337 	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
338 
339 	/* Update the 32bit ID registers only if AArch32 is implemented */
340 	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
341 		info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
342 		info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
343 		info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
344 		info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
345 		info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
346 		info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
347 		info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
348 		info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
349 		info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
350 		info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
351 		info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
352 		info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
353 		info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
354 
355 		info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
356 		info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
357 		info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
358 	}
359 
360 	if (IS_ENABLED(CONFIG_ARM64_SVE) &&
361 	    id_aa64pfr0_sve(info->reg_id_aa64pfr0))
362 		info->reg_zcr = read_zcr_features();
363 
364 	cpuinfo_detect_icache_policy(info);
365 }
366 
367 void cpuinfo_store_cpu(void)
368 {
369 	struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
370 	__cpuinfo_store_cpu(info);
371 	update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
372 }
373 
374 void __init cpuinfo_store_boot_cpu(void)
375 {
376 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
377 	__cpuinfo_store_cpu(info);
378 
379 	boot_cpu_data = *info;
380 	init_cpu_features(&boot_cpu_data);
381 }
382 
383 device_initcall(cpuinfo_regs_init);
384