1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static inline const char *icache_policy_str(int l1ip) 37 { 38 switch (l1ip) { 39 case CTR_EL0_L1Ip_VPIPT: 40 return "VPIPT"; 41 case CTR_EL0_L1Ip_VIPT: 42 return "VIPT"; 43 case CTR_EL0_L1Ip_PIPT: 44 return "PIPT"; 45 default: 46 return "RESERVED/UNKNOWN"; 47 } 48 } 49 50 unsigned long __icache_flags; 51 52 static const char *const hwcap_str[] = { 53 [KERNEL_HWCAP_FP] = "fp", 54 [KERNEL_HWCAP_ASIMD] = "asimd", 55 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 56 [KERNEL_HWCAP_AES] = "aes", 57 [KERNEL_HWCAP_PMULL] = "pmull", 58 [KERNEL_HWCAP_SHA1] = "sha1", 59 [KERNEL_HWCAP_SHA2] = "sha2", 60 [KERNEL_HWCAP_CRC32] = "crc32", 61 [KERNEL_HWCAP_ATOMICS] = "atomics", 62 [KERNEL_HWCAP_FPHP] = "fphp", 63 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 64 [KERNEL_HWCAP_CPUID] = "cpuid", 65 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 66 [KERNEL_HWCAP_JSCVT] = "jscvt", 67 [KERNEL_HWCAP_FCMA] = "fcma", 68 [KERNEL_HWCAP_LRCPC] = "lrcpc", 69 [KERNEL_HWCAP_DCPOP] = "dcpop", 70 [KERNEL_HWCAP_SHA3] = "sha3", 71 [KERNEL_HWCAP_SM3] = "sm3", 72 [KERNEL_HWCAP_SM4] = "sm4", 73 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 74 [KERNEL_HWCAP_SHA512] = "sha512", 75 [KERNEL_HWCAP_SVE] = "sve", 76 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 77 [KERNEL_HWCAP_DIT] = "dit", 78 [KERNEL_HWCAP_USCAT] = "uscat", 79 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 80 [KERNEL_HWCAP_FLAGM] = "flagm", 81 [KERNEL_HWCAP_SSBS] = "ssbs", 82 [KERNEL_HWCAP_SB] = "sb", 83 [KERNEL_HWCAP_PACA] = "paca", 84 [KERNEL_HWCAP_PACG] = "pacg", 85 [KERNEL_HWCAP_DCPODP] = "dcpodp", 86 [KERNEL_HWCAP_SVE2] = "sve2", 87 [KERNEL_HWCAP_SVEAES] = "sveaes", 88 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 90 [KERNEL_HWCAP_SVESHA3] = "svesha3", 91 [KERNEL_HWCAP_SVESM4] = "svesm4", 92 [KERNEL_HWCAP_FLAGM2] = "flagm2", 93 [KERNEL_HWCAP_FRINT] = "frint", 94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 97 [KERNEL_HWCAP_SVEBF16] = "svebf16", 98 [KERNEL_HWCAP_I8MM] = "i8mm", 99 [KERNEL_HWCAP_BF16] = "bf16", 100 [KERNEL_HWCAP_DGH] = "dgh", 101 [KERNEL_HWCAP_RNG] = "rng", 102 [KERNEL_HWCAP_BTI] = "bti", 103 [KERNEL_HWCAP_MTE] = "mte", 104 [KERNEL_HWCAP_ECV] = "ecv", 105 [KERNEL_HWCAP_AFP] = "afp", 106 [KERNEL_HWCAP_RPRES] = "rpres", 107 [KERNEL_HWCAP_MTE3] = "mte3", 108 [KERNEL_HWCAP_SME] = "sme", 109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 115 [KERNEL_HWCAP_SME_FA64] = "smefa64", 116 [KERNEL_HWCAP_WFXT] = "wfxt", 117 [KERNEL_HWCAP_EBF16] = "ebf16", 118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", 119 [KERNEL_HWCAP_CSSC] = "cssc", 120 [KERNEL_HWCAP_RPRFM] = "rprfm", 121 [KERNEL_HWCAP_SVE2P1] = "sve2p1", 122 }; 123 124 #ifdef CONFIG_COMPAT 125 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 126 static const char *const compat_hwcap_str[] = { 127 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 128 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 129 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 130 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 131 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 132 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 133 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 134 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 135 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 136 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 137 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 138 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 139 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 140 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 141 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 142 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 143 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 144 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 145 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 146 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 147 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 148 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 149 }; 150 151 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 152 static const char *const compat_hwcap2_str[] = { 153 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 154 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 155 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 156 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 157 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 158 }; 159 #endif /* CONFIG_COMPAT */ 160 161 static int c_show(struct seq_file *m, void *v) 162 { 163 int i, j; 164 bool compat = personality(current->personality) == PER_LINUX32; 165 166 for_each_online_cpu(i) { 167 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 168 u32 midr = cpuinfo->reg_midr; 169 170 /* 171 * glibc reads /proc/cpuinfo to determine the number of 172 * online processors, looking for lines beginning with 173 * "processor". Give glibc what it expects. 174 */ 175 seq_printf(m, "processor\t: %d\n", i); 176 if (compat) 177 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 178 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 179 180 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 181 loops_per_jiffy / (500000UL/HZ), 182 loops_per_jiffy / (5000UL/HZ) % 100); 183 184 /* 185 * Dump out the common processor features in a single line. 186 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 187 * rather than attempting to parse this, but there's a body of 188 * software which does already (at least for 32-bit). 189 */ 190 seq_puts(m, "Features\t:"); 191 if (compat) { 192 #ifdef CONFIG_COMPAT 193 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 194 if (compat_elf_hwcap & (1 << j)) { 195 /* 196 * Warn once if any feature should not 197 * have been present on arm64 platform. 198 */ 199 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 200 continue; 201 202 seq_printf(m, " %s", compat_hwcap_str[j]); 203 } 204 } 205 206 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 207 if (compat_elf_hwcap2 & (1 << j)) 208 seq_printf(m, " %s", compat_hwcap2_str[j]); 209 #endif /* CONFIG_COMPAT */ 210 } else { 211 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 212 if (cpu_have_feature(j)) 213 seq_printf(m, " %s", hwcap_str[j]); 214 } 215 seq_puts(m, "\n"); 216 217 seq_printf(m, "CPU implementer\t: 0x%02x\n", 218 MIDR_IMPLEMENTOR(midr)); 219 seq_printf(m, "CPU architecture: 8\n"); 220 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 221 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 222 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 223 } 224 225 return 0; 226 } 227 228 static void *c_start(struct seq_file *m, loff_t *pos) 229 { 230 return *pos < 1 ? (void *)1 : NULL; 231 } 232 233 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 234 { 235 ++*pos; 236 return NULL; 237 } 238 239 static void c_stop(struct seq_file *m, void *v) 240 { 241 } 242 243 const struct seq_operations cpuinfo_op = { 244 .start = c_start, 245 .next = c_next, 246 .stop = c_stop, 247 .show = c_show 248 }; 249 250 251 static struct kobj_type cpuregs_kobj_type = { 252 .sysfs_ops = &kobj_sysfs_ops, 253 }; 254 255 /* 256 * The ARM ARM uses the phrase "32-bit register" to describe a register 257 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 258 * no statement is made as to whether the upper 32 bits will or will not 259 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 260 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 261 * 262 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 263 * registers, we expose them both as 64 bit values to cater for possible 264 * future expansion without an ABI break. 265 */ 266 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 267 #define CPUREGS_ATTR_RO(_name, _field) \ 268 static ssize_t _name##_show(struct kobject *kobj, \ 269 struct kobj_attribute *attr, char *buf) \ 270 { \ 271 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 272 \ 273 if (info->reg_midr) \ 274 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 275 else \ 276 return 0; \ 277 } \ 278 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 279 280 CPUREGS_ATTR_RO(midr_el1, midr); 281 CPUREGS_ATTR_RO(revidr_el1, revidr); 282 CPUREGS_ATTR_RO(smidr_el1, smidr); 283 284 static struct attribute *cpuregs_id_attrs[] = { 285 &cpuregs_attr_midr_el1.attr, 286 &cpuregs_attr_revidr_el1.attr, 287 NULL 288 }; 289 290 static const struct attribute_group cpuregs_attr_group = { 291 .attrs = cpuregs_id_attrs, 292 .name = "identification" 293 }; 294 295 static struct attribute *sme_cpuregs_id_attrs[] = { 296 &cpuregs_attr_smidr_el1.attr, 297 NULL 298 }; 299 300 static const struct attribute_group sme_cpuregs_attr_group = { 301 .attrs = sme_cpuregs_id_attrs, 302 .name = "identification" 303 }; 304 305 static int cpuid_cpu_online(unsigned int cpu) 306 { 307 int rc; 308 struct device *dev; 309 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 310 311 dev = get_cpu_device(cpu); 312 if (!dev) { 313 rc = -ENODEV; 314 goto out; 315 } 316 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 317 if (rc) 318 goto out; 319 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 320 if (rc) 321 kobject_del(&info->kobj); 322 if (system_supports_sme()) 323 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group); 324 out: 325 return rc; 326 } 327 328 static int cpuid_cpu_offline(unsigned int cpu) 329 { 330 struct device *dev; 331 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 332 333 dev = get_cpu_device(cpu); 334 if (!dev) 335 return -ENODEV; 336 if (info->kobj.parent) { 337 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 338 kobject_del(&info->kobj); 339 } 340 341 return 0; 342 } 343 344 static int __init cpuinfo_regs_init(void) 345 { 346 int cpu, ret; 347 348 for_each_possible_cpu(cpu) { 349 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 350 351 kobject_init(&info->kobj, &cpuregs_kobj_type); 352 } 353 354 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 355 cpuid_cpu_online, cpuid_cpu_offline); 356 if (ret < 0) { 357 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 358 return ret; 359 } 360 return 0; 361 } 362 device_initcall(cpuinfo_regs_init); 363 364 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 365 { 366 unsigned int cpu = smp_processor_id(); 367 u32 l1ip = CTR_L1IP(info->reg_ctr); 368 369 switch (l1ip) { 370 case CTR_EL0_L1Ip_PIPT: 371 break; 372 case CTR_EL0_L1Ip_VPIPT: 373 set_bit(ICACHEF_VPIPT, &__icache_flags); 374 break; 375 case CTR_EL0_L1Ip_VIPT: 376 default: 377 /* Assume aliasing */ 378 set_bit(ICACHEF_ALIASING, &__icache_flags); 379 break; 380 } 381 382 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); 383 } 384 385 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 386 { 387 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 388 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 389 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 390 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 391 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 392 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 393 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 394 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 395 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 396 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 397 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 398 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 399 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 400 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 401 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 402 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 403 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 404 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 405 406 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 407 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 408 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 409 } 410 411 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 412 { 413 info->reg_cntfrq = arch_timer_get_cntfrq(); 414 /* 415 * Use the effective value of the CTR_EL0 than the raw value 416 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 417 * with the CLIDR_EL1 fields to avoid triggering false warnings 418 * when there is a mismatch across the CPUs. Keep track of the 419 * effective value of the CTR_EL0 in our internal records for 420 * accurate sanity check and feature enablement. 421 */ 422 info->reg_ctr = read_cpuid_effective_cachetype(); 423 info->reg_dczid = read_cpuid(DCZID_EL0); 424 info->reg_midr = read_cpuid_id(); 425 info->reg_revidr = read_cpuid(REVIDR_EL1); 426 427 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 428 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 429 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 430 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 431 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 432 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 433 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 434 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 435 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 436 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 437 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 438 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); 439 440 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 441 info->reg_gmid = read_cpuid(GMID_EL1); 442 443 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 444 __cpuinfo_store_cpu_32bit(&info->aarch32); 445 446 cpuinfo_detect_icache_policy(info); 447 } 448 449 void cpuinfo_store_cpu(void) 450 { 451 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 452 __cpuinfo_store_cpu(info); 453 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 454 } 455 456 void __init cpuinfo_store_boot_cpu(void) 457 { 458 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 459 __cpuinfo_store_cpu(info); 460 461 boot_cpu_data = *info; 462 init_cpu_features(&boot_cpu_data); 463 } 464