1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/mm.h> 72 #include <linux/cpu.h> 73 #include <asm/cpu.h> 74 #include <asm/cpufeature.h> 75 #include <asm/cpu_ops.h> 76 #include <asm/fpsimd.h> 77 #include <asm/mmu_context.h> 78 #include <asm/mte.h> 79 #include <asm/processor.h> 80 #include <asm/sysreg.h> 81 #include <asm/traps.h> 82 #include <asm/virt.h> 83 84 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 85 static unsigned long elf_hwcap __read_mostly; 86 87 #ifdef CONFIG_COMPAT 88 #define COMPAT_ELF_HWCAP_DEFAULT \ 89 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 90 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 91 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 92 COMPAT_HWCAP_LPAE) 93 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 94 unsigned int compat_elf_hwcap2 __read_mostly; 95 #endif 96 97 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 98 EXPORT_SYMBOL(cpu_hwcaps); 99 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 100 101 /* Need also bit for ARM64_CB_PATCH */ 102 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 103 104 bool arm64_use_ng_mappings = false; 105 EXPORT_SYMBOL(arm64_use_ng_mappings); 106 107 /* 108 * Flag to indicate if we have computed the system wide 109 * capabilities based on the boot time active CPUs. This 110 * will be used to determine if a new booting CPU should 111 * go through the verification process to make sure that it 112 * supports the system capabilities, without using a hotplug 113 * notifier. This is also used to decide if we could use 114 * the fast path for checking constant CPU caps. 115 */ 116 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 117 EXPORT_SYMBOL(arm64_const_caps_ready); 118 static inline void finalize_system_capabilities(void) 119 { 120 static_branch_enable(&arm64_const_caps_ready); 121 } 122 123 void dump_cpu_features(void) 124 { 125 /* file-wide pr_fmt adds "CPU features: " prefix */ 126 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 127 } 128 129 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 130 EXPORT_SYMBOL(cpu_hwcap_keys); 131 132 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 133 { \ 134 .sign = SIGNED, \ 135 .visible = VISIBLE, \ 136 .strict = STRICT, \ 137 .type = TYPE, \ 138 .shift = SHIFT, \ 139 .width = WIDTH, \ 140 .safe_val = SAFE_VAL, \ 141 } 142 143 /* Define a feature with unsigned values */ 144 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 145 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 146 147 /* Define a feature with a signed value */ 148 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 149 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 150 151 #define ARM64_FTR_END \ 152 { \ 153 .width = 0, \ 154 } 155 156 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 157 158 static bool __system_matches_cap(unsigned int n); 159 160 /* 161 * NOTE: Any changes to the visibility of features should be kept in 162 * sync with the documentation of the CPU feature register ABI. 163 */ 164 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 165 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 179 ARM64_FTR_END, 180 }; 181 182 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 190 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 192 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 197 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 199 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 201 ARM64_FTR_END, 202 }; 203 204 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 212 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 215 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 216 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 221 ARM64_FTR_END, 222 }; 223 224 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 228 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 230 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 231 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 232 ARM64_FTR_END, 233 }; 234 235 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 236 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 237 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 254 ARM64_FTR_END, 255 }; 256 257 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 261 /* 262 * Page size not being supported at Stage-2 is not fatal. You 263 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 264 * your favourite nesting hypervisor. 265 * 266 * There is a small corner case where the hypervisor explicitly 267 * advertises a given granule size at Stage-2 (value 2) on some 268 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 269 * vCPUs. Although this is not forbidden by the architecture, it 270 * indicates that the hypervisor is being silly (or buggy). 271 * 272 * We make no effort to cope with this and pretend that if these 273 * fields are inconsistent across vCPUs, then it isn't worth 274 * trying to bring KVM up. 275 */ 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 279 /* 280 * We already refuse to boot CPUs that don't support our configured 281 * page size, so we can only detect mismatches for a page size other 282 * than the one we're currently using. Unfortunately, SoCs like this 283 * exist in the wild so, even though we don't like it, we'll have to go 284 * along with it and treat them as non-strict. 285 */ 286 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 287 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 289 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 291 /* Linux shouldn't care about secure memory */ 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 295 /* 296 * Differing PARange is fine as long as all peripherals and memory are mapped 297 * within the minimum PARange of all CPUs 298 */ 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 300 ARM64_FTR_END, 301 }; 302 303 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 314 ARM64_FTR_END, 315 }; 316 317 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 333 ARM64_FTR_END, 334 }; 335 336 static const struct arm64_ftr_bits ftr_ctr[] = { 337 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 338 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 343 /* 344 * Linux can handle differing I-cache policies. Userspace JITs will 345 * make use of *minLine. 346 * If we have differing I-cache policies, report it as the weakest - VIPT. 347 */ 348 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 349 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 350 ARM64_FTR_END, 351 }; 352 353 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 354 .name = "SYS_CTR_EL0", 355 .ftr_bits = ftr_ctr 356 }; 357 358 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 359 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 364 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 367 ARM64_FTR_END, 368 }; 369 370 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 371 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 376 /* 377 * We can instantiate multiple PMU instances with different levels 378 * of support. 379 */ 380 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 383 ARM64_FTR_END, 384 }; 385 386 static const struct arm64_ftr_bits ftr_mvfr2[] = { 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 389 ARM64_FTR_END, 390 }; 391 392 static const struct arm64_ftr_bits ftr_dczid[] = { 393 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 394 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 395 ARM64_FTR_END, 396 }; 397 398 static const struct arm64_ftr_bits ftr_id_isar0[] = { 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 406 ARM64_FTR_END, 407 }; 408 409 static const struct arm64_ftr_bits ftr_id_isar5[] = { 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 416 ARM64_FTR_END, 417 }; 418 419 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 427 428 /* 429 * SpecSEI = 1 indicates that the PE might generate an SError on an 430 * external abort on speculative read. It is safe to assume that an 431 * SError might be generated than it will not be. Hence it has been 432 * classified as FTR_HIGHER_SAFE. 433 */ 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 435 ARM64_FTR_END, 436 }; 437 438 static const struct arm64_ftr_bits ftr_id_isar4[] = { 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 447 ARM64_FTR_END, 448 }; 449 450 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 452 ARM64_FTR_END, 453 }; 454 455 static const struct arm64_ftr_bits ftr_id_isar6[] = { 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 463 ARM64_FTR_END, 464 }; 465 466 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 473 ARM64_FTR_END, 474 }; 475 476 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 485 ARM64_FTR_END, 486 }; 487 488 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 491 ARM64_FTR_END, 492 }; 493 494 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 495 /* [31:28] TraceFilt */ 496 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 503 ARM64_FTR_END, 504 }; 505 506 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 507 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 508 ARM64_FTR_END, 509 }; 510 511 static const struct arm64_ftr_bits ftr_zcr[] = { 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 513 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 514 ARM64_FTR_END, 515 }; 516 517 /* 518 * Common ftr bits for a 32bit register with all hidden, strict 519 * attributes, with 4bit feature fields and a default safe value of 520 * 0. Covers the following 32bit registers: 521 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 522 */ 523 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 532 ARM64_FTR_END, 533 }; 534 535 /* Table for a single 32bit feature value */ 536 static const struct arm64_ftr_bits ftr_single32[] = { 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 538 ARM64_FTR_END, 539 }; 540 541 static const struct arm64_ftr_bits ftr_raz[] = { 542 ARM64_FTR_END, 543 }; 544 545 #define ARM64_FTR_REG(id, table) { \ 546 .sys_id = id, \ 547 .reg = &(struct arm64_ftr_reg){ \ 548 .name = #id, \ 549 .ftr_bits = &((table)[0]), \ 550 }} 551 552 static const struct __ftr_reg_entry { 553 u32 sys_id; 554 struct arm64_ftr_reg *reg; 555 } arm64_ftr_regs[] = { 556 557 /* Op1 = 0, CRn = 0, CRm = 1 */ 558 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 559 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 560 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 561 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 562 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 563 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 564 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 565 566 /* Op1 = 0, CRn = 0, CRm = 2 */ 567 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 568 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 569 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 570 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 571 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 572 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 573 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 574 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 575 576 /* Op1 = 0, CRn = 0, CRm = 3 */ 577 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 578 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 579 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 580 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 581 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 582 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 583 584 /* Op1 = 0, CRn = 0, CRm = 4 */ 585 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 586 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 587 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 588 589 /* Op1 = 0, CRn = 0, CRm = 5 */ 590 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 591 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 592 593 /* Op1 = 0, CRn = 0, CRm = 6 */ 594 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 595 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 596 597 /* Op1 = 0, CRn = 0, CRm = 7 */ 598 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 599 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 600 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 601 602 /* Op1 = 0, CRn = 1, CRm = 2 */ 603 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 604 605 /* Op1 = 3, CRn = 0, CRm = 0 */ 606 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 607 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 608 609 /* Op1 = 3, CRn = 14, CRm = 0 */ 610 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 611 }; 612 613 static int search_cmp_ftr_reg(const void *id, const void *regp) 614 { 615 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 616 } 617 618 /* 619 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 620 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 621 * ascending order of sys_id, we use binary search to find a matching 622 * entry. 623 * 624 * returns - Upon success, matching ftr_reg entry for id. 625 * - NULL on failure. It is upto the caller to decide 626 * the impact of a failure. 627 */ 628 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 629 { 630 const struct __ftr_reg_entry *ret; 631 632 ret = bsearch((const void *)(unsigned long)sys_id, 633 arm64_ftr_regs, 634 ARRAY_SIZE(arm64_ftr_regs), 635 sizeof(arm64_ftr_regs[0]), 636 search_cmp_ftr_reg); 637 if (ret) 638 return ret->reg; 639 return NULL; 640 } 641 642 /* 643 * get_arm64_ftr_reg - Looks up a feature register entry using 644 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 645 * 646 * returns - Upon success, matching ftr_reg entry for id. 647 * - NULL on failure but with an WARN_ON(). 648 */ 649 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 650 { 651 struct arm64_ftr_reg *reg; 652 653 reg = get_arm64_ftr_reg_nowarn(sys_id); 654 655 /* 656 * Requesting a non-existent register search is an error. Warn 657 * and let the caller handle it. 658 */ 659 WARN_ON(!reg); 660 return reg; 661 } 662 663 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 664 s64 ftr_val) 665 { 666 u64 mask = arm64_ftr_mask(ftrp); 667 668 reg &= ~mask; 669 reg |= (ftr_val << ftrp->shift) & mask; 670 return reg; 671 } 672 673 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 674 s64 cur) 675 { 676 s64 ret = 0; 677 678 switch (ftrp->type) { 679 case FTR_EXACT: 680 ret = ftrp->safe_val; 681 break; 682 case FTR_LOWER_SAFE: 683 ret = new < cur ? new : cur; 684 break; 685 case FTR_HIGHER_OR_ZERO_SAFE: 686 if (!cur || !new) 687 break; 688 fallthrough; 689 case FTR_HIGHER_SAFE: 690 ret = new > cur ? new : cur; 691 break; 692 default: 693 BUG(); 694 } 695 696 return ret; 697 } 698 699 static void __init sort_ftr_regs(void) 700 { 701 unsigned int i; 702 703 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 704 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 705 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 706 unsigned int j = 0; 707 708 /* 709 * Features here must be sorted in descending order with respect 710 * to their shift values and should not overlap with each other. 711 */ 712 for (; ftr_bits->width != 0; ftr_bits++, j++) { 713 unsigned int width = ftr_reg->ftr_bits[j].width; 714 unsigned int shift = ftr_reg->ftr_bits[j].shift; 715 unsigned int prev_shift; 716 717 WARN((shift + width) > 64, 718 "%s has invalid feature at shift %d\n", 719 ftr_reg->name, shift); 720 721 /* 722 * Skip the first feature. There is nothing to 723 * compare against for now. 724 */ 725 if (j == 0) 726 continue; 727 728 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 729 WARN((shift + width) > prev_shift, 730 "%s has feature overlap at shift %d\n", 731 ftr_reg->name, shift); 732 } 733 734 /* 735 * Skip the first register. There is nothing to 736 * compare against for now. 737 */ 738 if (i == 0) 739 continue; 740 /* 741 * Registers here must be sorted in ascending order with respect 742 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 743 * to work correctly. 744 */ 745 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 746 } 747 } 748 749 /* 750 * Initialise the CPU feature register from Boot CPU values. 751 * Also initiliases the strict_mask for the register. 752 * Any bits that are not covered by an arm64_ftr_bits entry are considered 753 * RES0 for the system-wide value, and must strictly match. 754 */ 755 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 756 { 757 u64 val = 0; 758 u64 strict_mask = ~0x0ULL; 759 u64 user_mask = 0; 760 u64 valid_mask = 0; 761 762 const struct arm64_ftr_bits *ftrp; 763 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 764 765 if (!reg) 766 return; 767 768 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 769 u64 ftr_mask = arm64_ftr_mask(ftrp); 770 s64 ftr_new = arm64_ftr_value(ftrp, new); 771 772 val = arm64_ftr_set_value(ftrp, val, ftr_new); 773 774 valid_mask |= ftr_mask; 775 if (!ftrp->strict) 776 strict_mask &= ~ftr_mask; 777 if (ftrp->visible) 778 user_mask |= ftr_mask; 779 else 780 reg->user_val = arm64_ftr_set_value(ftrp, 781 reg->user_val, 782 ftrp->safe_val); 783 } 784 785 val &= valid_mask; 786 787 reg->sys_val = val; 788 reg->strict_mask = strict_mask; 789 reg->user_mask = user_mask; 790 } 791 792 extern const struct arm64_cpu_capabilities arm64_errata[]; 793 static const struct arm64_cpu_capabilities arm64_features[]; 794 795 static void __init 796 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 797 { 798 for (; caps->matches; caps++) { 799 if (WARN(caps->capability >= ARM64_NCAPS, 800 "Invalid capability %d\n", caps->capability)) 801 continue; 802 if (WARN(cpu_hwcaps_ptrs[caps->capability], 803 "Duplicate entry for capability %d\n", 804 caps->capability)) 805 continue; 806 cpu_hwcaps_ptrs[caps->capability] = caps; 807 } 808 } 809 810 static void __init init_cpu_hwcaps_indirect_list(void) 811 { 812 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 813 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 814 } 815 816 static void __init setup_boot_cpu_capabilities(void); 817 818 void __init init_cpu_features(struct cpuinfo_arm64 *info) 819 { 820 /* Before we start using the tables, make sure it is sorted */ 821 sort_ftr_regs(); 822 823 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 824 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 825 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 826 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 827 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 828 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 829 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 830 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 831 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 832 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 833 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 834 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 835 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 836 837 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 838 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 839 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 840 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 841 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 842 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 843 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 844 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 845 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 846 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 847 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 848 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 849 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 850 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 851 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 852 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 853 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 854 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 855 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 856 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 857 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 858 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 859 } 860 861 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 862 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 863 sve_init_vq_map(); 864 } 865 866 /* 867 * Initialize the indirect array of CPU hwcaps capabilities pointers 868 * before we handle the boot CPU below. 869 */ 870 init_cpu_hwcaps_indirect_list(); 871 872 /* 873 * Detect and enable early CPU capabilities based on the boot CPU, 874 * after we have initialised the CPU feature infrastructure. 875 */ 876 setup_boot_cpu_capabilities(); 877 } 878 879 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 880 { 881 const struct arm64_ftr_bits *ftrp; 882 883 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 884 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 885 s64 ftr_new = arm64_ftr_value(ftrp, new); 886 887 if (ftr_cur == ftr_new) 888 continue; 889 /* Find a safe value */ 890 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 891 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 892 } 893 894 } 895 896 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 897 { 898 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 899 900 if (!regp) 901 return 0; 902 903 update_cpu_ftr_reg(regp, val); 904 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 905 return 0; 906 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 907 regp->name, boot, cpu, val); 908 return 1; 909 } 910 911 static void relax_cpu_ftr_reg(u32 sys_id, int field) 912 { 913 const struct arm64_ftr_bits *ftrp; 914 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 915 916 if (!regp) 917 return; 918 919 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 920 if (ftrp->shift == field) { 921 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 922 break; 923 } 924 } 925 926 /* Bogus field? */ 927 WARN_ON(!ftrp->width); 928 } 929 930 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 931 struct cpuinfo_arm64 *boot) 932 { 933 int taint = 0; 934 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 935 936 /* 937 * If we don't have AArch32 at all then skip the checks entirely 938 * as the register values may be UNKNOWN and we're not going to be 939 * using them for anything. 940 */ 941 if (!id_aa64pfr0_32bit_el0(pfr0)) 942 return taint; 943 944 /* 945 * If we don't have AArch32 at EL1, then relax the strictness of 946 * EL1-dependent register fields to avoid spurious sanity check fails. 947 */ 948 if (!id_aa64pfr0_32bit_el1(pfr0)) { 949 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 950 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 951 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 952 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 953 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 954 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 955 } 956 957 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 958 info->reg_id_dfr0, boot->reg_id_dfr0); 959 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 960 info->reg_id_dfr1, boot->reg_id_dfr1); 961 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 962 info->reg_id_isar0, boot->reg_id_isar0); 963 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 964 info->reg_id_isar1, boot->reg_id_isar1); 965 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 966 info->reg_id_isar2, boot->reg_id_isar2); 967 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 968 info->reg_id_isar3, boot->reg_id_isar3); 969 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 970 info->reg_id_isar4, boot->reg_id_isar4); 971 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 972 info->reg_id_isar5, boot->reg_id_isar5); 973 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 974 info->reg_id_isar6, boot->reg_id_isar6); 975 976 /* 977 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 978 * ACTLR formats could differ across CPUs and therefore would have to 979 * be trapped for virtualization anyway. 980 */ 981 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 982 info->reg_id_mmfr0, boot->reg_id_mmfr0); 983 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 984 info->reg_id_mmfr1, boot->reg_id_mmfr1); 985 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 986 info->reg_id_mmfr2, boot->reg_id_mmfr2); 987 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 988 info->reg_id_mmfr3, boot->reg_id_mmfr3); 989 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 990 info->reg_id_mmfr4, boot->reg_id_mmfr4); 991 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 992 info->reg_id_mmfr5, boot->reg_id_mmfr5); 993 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 994 info->reg_id_pfr0, boot->reg_id_pfr0); 995 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 996 info->reg_id_pfr1, boot->reg_id_pfr1); 997 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 998 info->reg_id_pfr2, boot->reg_id_pfr2); 999 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1000 info->reg_mvfr0, boot->reg_mvfr0); 1001 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1002 info->reg_mvfr1, boot->reg_mvfr1); 1003 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1004 info->reg_mvfr2, boot->reg_mvfr2); 1005 1006 return taint; 1007 } 1008 1009 /* 1010 * Update system wide CPU feature registers with the values from a 1011 * non-boot CPU. Also performs SANITY checks to make sure that there 1012 * aren't any insane variations from that of the boot CPU. 1013 */ 1014 void update_cpu_features(int cpu, 1015 struct cpuinfo_arm64 *info, 1016 struct cpuinfo_arm64 *boot) 1017 { 1018 int taint = 0; 1019 1020 /* 1021 * The kernel can handle differing I-cache policies, but otherwise 1022 * caches should look identical. Userspace JITs will make use of 1023 * *minLine. 1024 */ 1025 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1026 info->reg_ctr, boot->reg_ctr); 1027 1028 /* 1029 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1030 * could result in too much or too little memory being zeroed if a 1031 * process is preempted and migrated between CPUs. 1032 */ 1033 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1034 info->reg_dczid, boot->reg_dczid); 1035 1036 /* If different, timekeeping will be broken (especially with KVM) */ 1037 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1038 info->reg_cntfrq, boot->reg_cntfrq); 1039 1040 /* 1041 * The kernel uses self-hosted debug features and expects CPUs to 1042 * support identical debug features. We presently need CTX_CMPs, WRPs, 1043 * and BRPs to be identical. 1044 * ID_AA64DFR1 is currently RES0. 1045 */ 1046 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1047 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1048 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1049 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1050 /* 1051 * Even in big.LITTLE, processors should be identical instruction-set 1052 * wise. 1053 */ 1054 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1055 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1056 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1057 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1058 1059 /* 1060 * Differing PARange support is fine as long as all peripherals and 1061 * memory are mapped within the minimum PARange of all CPUs. 1062 * Linux should not care about secure memory. 1063 */ 1064 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1065 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1066 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1067 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1068 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1069 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1070 1071 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1072 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1073 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1074 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1075 1076 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1077 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1078 1079 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1080 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1081 info->reg_zcr, boot->reg_zcr); 1082 1083 /* Probe vector lengths, unless we already gave up on SVE */ 1084 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1085 !system_capabilities_finalized()) 1086 sve_update_vq_map(); 1087 } 1088 1089 /* 1090 * This relies on a sanitised view of the AArch64 ID registers 1091 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1092 */ 1093 taint |= update_32bit_cpu_features(cpu, info, boot); 1094 1095 /* 1096 * Mismatched CPU features are a recipe for disaster. Don't even 1097 * pretend to support them. 1098 */ 1099 if (taint) { 1100 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1101 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1102 } 1103 } 1104 1105 u64 read_sanitised_ftr_reg(u32 id) 1106 { 1107 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1108 1109 if (!regp) 1110 return 0; 1111 return regp->sys_val; 1112 } 1113 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1114 1115 #define read_sysreg_case(r) \ 1116 case r: return read_sysreg_s(r) 1117 1118 /* 1119 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1120 * Read the system register on the current CPU 1121 */ 1122 static u64 __read_sysreg_by_encoding(u32 sys_id) 1123 { 1124 switch (sys_id) { 1125 read_sysreg_case(SYS_ID_PFR0_EL1); 1126 read_sysreg_case(SYS_ID_PFR1_EL1); 1127 read_sysreg_case(SYS_ID_PFR2_EL1); 1128 read_sysreg_case(SYS_ID_DFR0_EL1); 1129 read_sysreg_case(SYS_ID_DFR1_EL1); 1130 read_sysreg_case(SYS_ID_MMFR0_EL1); 1131 read_sysreg_case(SYS_ID_MMFR1_EL1); 1132 read_sysreg_case(SYS_ID_MMFR2_EL1); 1133 read_sysreg_case(SYS_ID_MMFR3_EL1); 1134 read_sysreg_case(SYS_ID_MMFR4_EL1); 1135 read_sysreg_case(SYS_ID_MMFR5_EL1); 1136 read_sysreg_case(SYS_ID_ISAR0_EL1); 1137 read_sysreg_case(SYS_ID_ISAR1_EL1); 1138 read_sysreg_case(SYS_ID_ISAR2_EL1); 1139 read_sysreg_case(SYS_ID_ISAR3_EL1); 1140 read_sysreg_case(SYS_ID_ISAR4_EL1); 1141 read_sysreg_case(SYS_ID_ISAR5_EL1); 1142 read_sysreg_case(SYS_ID_ISAR6_EL1); 1143 read_sysreg_case(SYS_MVFR0_EL1); 1144 read_sysreg_case(SYS_MVFR1_EL1); 1145 read_sysreg_case(SYS_MVFR2_EL1); 1146 1147 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1148 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1149 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1150 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1151 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1152 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1153 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1154 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1155 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1156 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1157 1158 read_sysreg_case(SYS_CNTFRQ_EL0); 1159 read_sysreg_case(SYS_CTR_EL0); 1160 read_sysreg_case(SYS_DCZID_EL0); 1161 1162 default: 1163 BUG(); 1164 return 0; 1165 } 1166 } 1167 1168 #include <linux/irqchip/arm-gic-v3.h> 1169 1170 static bool 1171 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1172 { 1173 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1174 1175 return val >= entry->min_field_value; 1176 } 1177 1178 static bool 1179 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1180 { 1181 u64 val; 1182 1183 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1184 if (scope == SCOPE_SYSTEM) 1185 val = read_sanitised_ftr_reg(entry->sys_reg); 1186 else 1187 val = __read_sysreg_by_encoding(entry->sys_reg); 1188 1189 return feature_matches(val, entry); 1190 } 1191 1192 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1193 { 1194 bool has_sre; 1195 1196 if (!has_cpuid_feature(entry, scope)) 1197 return false; 1198 1199 has_sre = gic_enable_sre(); 1200 if (!has_sre) 1201 pr_warn_once("%s present but disabled by higher exception level\n", 1202 entry->desc); 1203 1204 return has_sre; 1205 } 1206 1207 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1208 { 1209 u32 midr = read_cpuid_id(); 1210 1211 /* Cavium ThunderX pass 1.x and 2.x */ 1212 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1213 MIDR_CPU_VAR_REV(0, 0), 1214 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1215 } 1216 1217 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1218 { 1219 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1220 1221 return cpuid_feature_extract_signed_field(pfr0, 1222 ID_AA64PFR0_FP_SHIFT) < 0; 1223 } 1224 1225 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1226 int scope) 1227 { 1228 u64 ctr; 1229 1230 if (scope == SCOPE_SYSTEM) 1231 ctr = arm64_ftr_reg_ctrel0.sys_val; 1232 else 1233 ctr = read_cpuid_effective_cachetype(); 1234 1235 return ctr & BIT(CTR_IDC_SHIFT); 1236 } 1237 1238 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1239 { 1240 /* 1241 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1242 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1243 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1244 * value. 1245 */ 1246 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1247 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1248 } 1249 1250 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1251 int scope) 1252 { 1253 u64 ctr; 1254 1255 if (scope == SCOPE_SYSTEM) 1256 ctr = arm64_ftr_reg_ctrel0.sys_val; 1257 else 1258 ctr = read_cpuid_cachetype(); 1259 1260 return ctr & BIT(CTR_DIC_SHIFT); 1261 } 1262 1263 static bool __maybe_unused 1264 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1265 { 1266 /* 1267 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1268 * may share TLB entries with a CPU stuck in the crashed 1269 * kernel. 1270 */ 1271 if (is_kdump_kernel()) 1272 return false; 1273 1274 return has_cpuid_feature(entry, scope); 1275 } 1276 1277 /* 1278 * This check is triggered during the early boot before the cpufeature 1279 * is initialised. Checking the status on the local CPU allows the boot 1280 * CPU to detect the need for non-global mappings and thus avoiding a 1281 * pagetable re-write after all the CPUs are booted. This check will be 1282 * anyway run on individual CPUs, allowing us to get the consistent 1283 * state once the SMP CPUs are up and thus make the switch to non-global 1284 * mappings if required. 1285 */ 1286 bool kaslr_requires_kpti(void) 1287 { 1288 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1289 return false; 1290 1291 /* 1292 * E0PD does a similar job to KPTI so can be used instead 1293 * where available. 1294 */ 1295 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1296 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1297 if (cpuid_feature_extract_unsigned_field(mmfr2, 1298 ID_AA64MMFR2_E0PD_SHIFT)) 1299 return false; 1300 } 1301 1302 /* 1303 * Systems affected by Cavium erratum 24756 are incompatible 1304 * with KPTI. 1305 */ 1306 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1307 extern const struct midr_range cavium_erratum_27456_cpus[]; 1308 1309 if (is_midr_in_range_list(read_cpuid_id(), 1310 cavium_erratum_27456_cpus)) 1311 return false; 1312 } 1313 1314 return kaslr_offset() > 0; 1315 } 1316 1317 static bool __meltdown_safe = true; 1318 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1319 1320 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1321 int scope) 1322 { 1323 /* List of CPUs that are not vulnerable and don't need KPTI */ 1324 static const struct midr_range kpti_safe_list[] = { 1325 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1326 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1327 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1328 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1329 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1330 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1331 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1332 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1333 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1334 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1335 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1336 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1337 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1338 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1339 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1340 { /* sentinel */ } 1341 }; 1342 char const *str = "kpti command line option"; 1343 bool meltdown_safe; 1344 1345 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1346 1347 /* Defer to CPU feature registers */ 1348 if (has_cpuid_feature(entry, scope)) 1349 meltdown_safe = true; 1350 1351 if (!meltdown_safe) 1352 __meltdown_safe = false; 1353 1354 /* 1355 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1356 * ThunderX leads to apparent I-cache corruption of kernel text, which 1357 * ends as well as you might imagine. Don't even try. 1358 */ 1359 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1360 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1361 __kpti_forced = -1; 1362 } 1363 1364 /* Useful for KASLR robustness */ 1365 if (kaslr_requires_kpti()) { 1366 if (!__kpti_forced) { 1367 str = "KASLR"; 1368 __kpti_forced = 1; 1369 } 1370 } 1371 1372 if (cpu_mitigations_off() && !__kpti_forced) { 1373 str = "mitigations=off"; 1374 __kpti_forced = -1; 1375 } 1376 1377 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1378 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1379 return false; 1380 } 1381 1382 /* Forced? */ 1383 if (__kpti_forced) { 1384 pr_info_once("kernel page table isolation forced %s by %s\n", 1385 __kpti_forced > 0 ? "ON" : "OFF", str); 1386 return __kpti_forced > 0; 1387 } 1388 1389 return !meltdown_safe; 1390 } 1391 1392 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1393 static void 1394 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1395 { 1396 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1397 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1398 kpti_remap_fn *remap_fn; 1399 1400 int cpu = smp_processor_id(); 1401 1402 /* 1403 * We don't need to rewrite the page-tables if either we've done 1404 * it already or we have KASLR enabled and therefore have not 1405 * created any global mappings at all. 1406 */ 1407 if (arm64_use_ng_mappings) 1408 return; 1409 1410 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1411 1412 cpu_install_idmap(); 1413 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1414 cpu_uninstall_idmap(); 1415 1416 if (!cpu) 1417 arm64_use_ng_mappings = true; 1418 1419 return; 1420 } 1421 #else 1422 static void 1423 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1424 { 1425 } 1426 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1427 1428 static int __init parse_kpti(char *str) 1429 { 1430 bool enabled; 1431 int ret = strtobool(str, &enabled); 1432 1433 if (ret) 1434 return ret; 1435 1436 __kpti_forced = enabled ? 1 : -1; 1437 return 0; 1438 } 1439 early_param("kpti", parse_kpti); 1440 1441 #ifdef CONFIG_ARM64_HW_AFDBM 1442 static inline void __cpu_enable_hw_dbm(void) 1443 { 1444 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1445 1446 write_sysreg(tcr, tcr_el1); 1447 isb(); 1448 local_flush_tlb_all(); 1449 } 1450 1451 static bool cpu_has_broken_dbm(void) 1452 { 1453 /* List of CPUs which have broken DBM support. */ 1454 static const struct midr_range cpus[] = { 1455 #ifdef CONFIG_ARM64_ERRATUM_1024718 1456 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1457 /* Kryo4xx Silver (rdpe => r1p0) */ 1458 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1459 #endif 1460 {}, 1461 }; 1462 1463 return is_midr_in_range_list(read_cpuid_id(), cpus); 1464 } 1465 1466 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1467 { 1468 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1469 !cpu_has_broken_dbm(); 1470 } 1471 1472 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1473 { 1474 if (cpu_can_use_dbm(cap)) 1475 __cpu_enable_hw_dbm(); 1476 } 1477 1478 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1479 int __unused) 1480 { 1481 static bool detected = false; 1482 /* 1483 * DBM is a non-conflicting feature. i.e, the kernel can safely 1484 * run a mix of CPUs with and without the feature. So, we 1485 * unconditionally enable the capability to allow any late CPU 1486 * to use the feature. We only enable the control bits on the 1487 * CPU, if it actually supports. 1488 * 1489 * We have to make sure we print the "feature" detection only 1490 * when at least one CPU actually uses it. So check if this CPU 1491 * can actually use it and print the message exactly once. 1492 * 1493 * This is safe as all CPUs (including secondary CPUs - due to the 1494 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1495 * goes through the "matches" check exactly once. Also if a CPU 1496 * matches the criteria, it is guaranteed that the CPU will turn 1497 * the DBM on, as the capability is unconditionally enabled. 1498 */ 1499 if (!detected && cpu_can_use_dbm(cap)) { 1500 detected = true; 1501 pr_info("detected: Hardware dirty bit management\n"); 1502 } 1503 1504 return true; 1505 } 1506 1507 #endif 1508 1509 #ifdef CONFIG_ARM64_AMU_EXTN 1510 1511 /* 1512 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1513 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1514 * information regarding all the events that it supports. When a CPU bit is 1515 * set in the cpumask, the user of this feature can only rely on the presence 1516 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1517 * counters are enabled or access to these counters is enabled by code 1518 * executed at higher exception levels (firmware). 1519 */ 1520 static struct cpumask amu_cpus __read_mostly; 1521 1522 bool cpu_has_amu_feat(int cpu) 1523 { 1524 return cpumask_test_cpu(cpu, &amu_cpus); 1525 } 1526 1527 int get_cpu_with_amu_feat(void) 1528 { 1529 return cpumask_any(&amu_cpus); 1530 } 1531 1532 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1533 { 1534 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1535 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1536 smp_processor_id()); 1537 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1538 update_freq_counters_refs(); 1539 } 1540 } 1541 1542 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1543 int __unused) 1544 { 1545 /* 1546 * The AMU extension is a non-conflicting feature: the kernel can 1547 * safely run a mix of CPUs with and without support for the 1548 * activity monitors extension. Therefore, unconditionally enable 1549 * the capability to allow any late CPU to use the feature. 1550 * 1551 * With this feature unconditionally enabled, the cpu_enable 1552 * function will be called for all CPUs that match the criteria, 1553 * including secondary and hotplugged, marking this feature as 1554 * present on that respective CPU. The enable function will also 1555 * print a detection message. 1556 */ 1557 1558 return true; 1559 } 1560 #else 1561 int get_cpu_with_amu_feat(void) 1562 { 1563 return nr_cpu_ids; 1564 } 1565 #endif 1566 1567 #ifdef CONFIG_ARM64_VHE 1568 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1569 { 1570 return is_kernel_in_hyp_mode(); 1571 } 1572 1573 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1574 { 1575 /* 1576 * Copy register values that aren't redirected by hardware. 1577 * 1578 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1579 * this value to tpidr_el2 before we patch the code. Once we've done 1580 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1581 * do anything here. 1582 */ 1583 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1584 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1585 } 1586 #endif 1587 1588 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1589 { 1590 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1591 1592 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1593 WARN_ON(val & (7 << 27 | 7 << 21)); 1594 } 1595 1596 #ifdef CONFIG_ARM64_PAN 1597 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1598 { 1599 /* 1600 * We modify PSTATE. This won't work from irq context as the PSTATE 1601 * is discarded once we return from the exception. 1602 */ 1603 WARN_ON_ONCE(in_interrupt()); 1604 1605 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1606 set_pstate_pan(1); 1607 } 1608 #endif /* CONFIG_ARM64_PAN */ 1609 1610 #ifdef CONFIG_ARM64_RAS_EXTN 1611 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1612 { 1613 /* Firmware may have left a deferred SError in this register. */ 1614 write_sysreg_s(0, SYS_DISR_EL1); 1615 } 1616 #endif /* CONFIG_ARM64_RAS_EXTN */ 1617 1618 #ifdef CONFIG_ARM64_PTR_AUTH 1619 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1620 { 1621 int boot_val, sec_val; 1622 1623 /* We don't expect to be called with SCOPE_SYSTEM */ 1624 WARN_ON(scope == SCOPE_SYSTEM); 1625 /* 1626 * The ptr-auth feature levels are not intercompatible with lower 1627 * levels. Hence we must match ptr-auth feature level of the secondary 1628 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1629 * from the sanitised register whereas direct register read is done for 1630 * the secondary CPUs. 1631 * The sanitised feature state is guaranteed to match that of the 1632 * boot CPU as a mismatched secondary CPU is parked before it gets 1633 * a chance to update the state, with the capability. 1634 */ 1635 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1636 entry->field_pos, entry->sign); 1637 if (scope & SCOPE_BOOT_CPU) 1638 return boot_val >= entry->min_field_value; 1639 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1640 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1641 entry->field_pos, entry->sign); 1642 return sec_val == boot_val; 1643 } 1644 1645 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1646 int scope) 1647 { 1648 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1649 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1650 } 1651 1652 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1653 int __unused) 1654 { 1655 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1656 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1657 } 1658 #endif /* CONFIG_ARM64_PTR_AUTH */ 1659 1660 #ifdef CONFIG_ARM64_E0PD 1661 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1662 { 1663 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1664 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1665 } 1666 #endif /* CONFIG_ARM64_E0PD */ 1667 1668 #ifdef CONFIG_ARM64_PSEUDO_NMI 1669 static bool enable_pseudo_nmi; 1670 1671 static int __init early_enable_pseudo_nmi(char *p) 1672 { 1673 return strtobool(p, &enable_pseudo_nmi); 1674 } 1675 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1676 1677 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1678 int scope) 1679 { 1680 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1681 } 1682 #endif 1683 1684 #ifdef CONFIG_ARM64_BTI 1685 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1686 { 1687 /* 1688 * Use of X16/X17 for tail-calls and trampolines that jump to 1689 * function entry points using BR is a requirement for 1690 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1691 * So, be strict and forbid other BRs using other registers to 1692 * jump onto a PACIxSP instruction: 1693 */ 1694 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1695 isb(); 1696 } 1697 #endif /* CONFIG_ARM64_BTI */ 1698 1699 #ifdef CONFIG_ARM64_MTE 1700 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1701 { 1702 static bool cleared_zero_page = false; 1703 1704 /* 1705 * Clear the tags in the zero page. This needs to be done via the 1706 * linear map which has the Tagged attribute. 1707 */ 1708 if (!cleared_zero_page) { 1709 cleared_zero_page = true; 1710 mte_clear_page_tags(lm_alias(empty_zero_page)); 1711 } 1712 } 1713 #endif /* CONFIG_ARM64_MTE */ 1714 1715 /* Internal helper functions to match cpu capability type */ 1716 static bool 1717 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1718 { 1719 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1720 } 1721 1722 static bool 1723 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1724 { 1725 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1726 } 1727 1728 static bool 1729 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1730 { 1731 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1732 } 1733 1734 static const struct arm64_cpu_capabilities arm64_features[] = { 1735 { 1736 .desc = "GIC system register CPU interface", 1737 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1738 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1739 .matches = has_useable_gicv3_cpuif, 1740 .sys_reg = SYS_ID_AA64PFR0_EL1, 1741 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1742 .sign = FTR_UNSIGNED, 1743 .min_field_value = 1, 1744 }, 1745 #ifdef CONFIG_ARM64_PAN 1746 { 1747 .desc = "Privileged Access Never", 1748 .capability = ARM64_HAS_PAN, 1749 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1750 .matches = has_cpuid_feature, 1751 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1752 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1753 .sign = FTR_UNSIGNED, 1754 .min_field_value = 1, 1755 .cpu_enable = cpu_enable_pan, 1756 }, 1757 #endif /* CONFIG_ARM64_PAN */ 1758 #ifdef CONFIG_ARM64_LSE_ATOMICS 1759 { 1760 .desc = "LSE atomic instructions", 1761 .capability = ARM64_HAS_LSE_ATOMICS, 1762 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1763 .matches = has_cpuid_feature, 1764 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1765 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1766 .sign = FTR_UNSIGNED, 1767 .min_field_value = 2, 1768 }, 1769 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1770 { 1771 .desc = "Software prefetching using PRFM", 1772 .capability = ARM64_HAS_NO_HW_PREFETCH, 1773 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1774 .matches = has_no_hw_prefetch, 1775 }, 1776 #ifdef CONFIG_ARM64_VHE 1777 { 1778 .desc = "Virtualization Host Extensions", 1779 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1780 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1781 .matches = runs_at_el2, 1782 .cpu_enable = cpu_copy_el2regs, 1783 }, 1784 #endif /* CONFIG_ARM64_VHE */ 1785 { 1786 .desc = "32-bit EL0 Support", 1787 .capability = ARM64_HAS_32BIT_EL0, 1788 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1789 .matches = has_cpuid_feature, 1790 .sys_reg = SYS_ID_AA64PFR0_EL1, 1791 .sign = FTR_UNSIGNED, 1792 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1793 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1794 }, 1795 #ifdef CONFIG_KVM 1796 { 1797 .desc = "32-bit EL1 Support", 1798 .capability = ARM64_HAS_32BIT_EL1, 1799 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1800 .matches = has_cpuid_feature, 1801 .sys_reg = SYS_ID_AA64PFR0_EL1, 1802 .sign = FTR_UNSIGNED, 1803 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1804 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1805 }, 1806 #endif 1807 { 1808 .desc = "Kernel page table isolation (KPTI)", 1809 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1810 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1811 /* 1812 * The ID feature fields below are used to indicate that 1813 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1814 * more details. 1815 */ 1816 .sys_reg = SYS_ID_AA64PFR0_EL1, 1817 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1818 .min_field_value = 1, 1819 .matches = unmap_kernel_at_el0, 1820 .cpu_enable = kpti_install_ng_mappings, 1821 }, 1822 { 1823 /* FP/SIMD is not implemented */ 1824 .capability = ARM64_HAS_NO_FPSIMD, 1825 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1826 .min_field_value = 0, 1827 .matches = has_no_fpsimd, 1828 }, 1829 #ifdef CONFIG_ARM64_PMEM 1830 { 1831 .desc = "Data cache clean to Point of Persistence", 1832 .capability = ARM64_HAS_DCPOP, 1833 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1834 .matches = has_cpuid_feature, 1835 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1836 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1837 .min_field_value = 1, 1838 }, 1839 { 1840 .desc = "Data cache clean to Point of Deep Persistence", 1841 .capability = ARM64_HAS_DCPODP, 1842 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1843 .matches = has_cpuid_feature, 1844 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1845 .sign = FTR_UNSIGNED, 1846 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1847 .min_field_value = 2, 1848 }, 1849 #endif 1850 #ifdef CONFIG_ARM64_SVE 1851 { 1852 .desc = "Scalable Vector Extension", 1853 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1854 .capability = ARM64_SVE, 1855 .sys_reg = SYS_ID_AA64PFR0_EL1, 1856 .sign = FTR_UNSIGNED, 1857 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1858 .min_field_value = ID_AA64PFR0_SVE, 1859 .matches = has_cpuid_feature, 1860 .cpu_enable = sve_kernel_enable, 1861 }, 1862 #endif /* CONFIG_ARM64_SVE */ 1863 #ifdef CONFIG_ARM64_RAS_EXTN 1864 { 1865 .desc = "RAS Extension Support", 1866 .capability = ARM64_HAS_RAS_EXTN, 1867 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1868 .matches = has_cpuid_feature, 1869 .sys_reg = SYS_ID_AA64PFR0_EL1, 1870 .sign = FTR_UNSIGNED, 1871 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1872 .min_field_value = ID_AA64PFR0_RAS_V1, 1873 .cpu_enable = cpu_clear_disr, 1874 }, 1875 #endif /* CONFIG_ARM64_RAS_EXTN */ 1876 #ifdef CONFIG_ARM64_AMU_EXTN 1877 { 1878 /* 1879 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1880 * Therefore, don't provide .desc as we don't want the detection 1881 * message to be shown until at least one CPU is detected to 1882 * support the feature. 1883 */ 1884 .capability = ARM64_HAS_AMU_EXTN, 1885 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1886 .matches = has_amu, 1887 .sys_reg = SYS_ID_AA64PFR0_EL1, 1888 .sign = FTR_UNSIGNED, 1889 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1890 .min_field_value = ID_AA64PFR0_AMU, 1891 .cpu_enable = cpu_amu_enable, 1892 }, 1893 #endif /* CONFIG_ARM64_AMU_EXTN */ 1894 { 1895 .desc = "Data cache clean to the PoU not required for I/D coherence", 1896 .capability = ARM64_HAS_CACHE_IDC, 1897 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1898 .matches = has_cache_idc, 1899 .cpu_enable = cpu_emulate_effective_ctr, 1900 }, 1901 { 1902 .desc = "Instruction cache invalidation not required for I/D coherence", 1903 .capability = ARM64_HAS_CACHE_DIC, 1904 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1905 .matches = has_cache_dic, 1906 }, 1907 { 1908 .desc = "Stage-2 Force Write-Back", 1909 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1910 .capability = ARM64_HAS_STAGE2_FWB, 1911 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1912 .sign = FTR_UNSIGNED, 1913 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1914 .min_field_value = 1, 1915 .matches = has_cpuid_feature, 1916 .cpu_enable = cpu_has_fwb, 1917 }, 1918 { 1919 .desc = "ARMv8.4 Translation Table Level", 1920 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1921 .capability = ARM64_HAS_ARMv8_4_TTL, 1922 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1923 .sign = FTR_UNSIGNED, 1924 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 1925 .min_field_value = 1, 1926 .matches = has_cpuid_feature, 1927 }, 1928 { 1929 .desc = "TLB range maintenance instructions", 1930 .capability = ARM64_HAS_TLB_RANGE, 1931 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1932 .matches = has_cpuid_feature, 1933 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1934 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 1935 .sign = FTR_UNSIGNED, 1936 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 1937 }, 1938 #ifdef CONFIG_ARM64_HW_AFDBM 1939 { 1940 /* 1941 * Since we turn this on always, we don't want the user to 1942 * think that the feature is available when it may not be. 1943 * So hide the description. 1944 * 1945 * .desc = "Hardware pagetable Dirty Bit Management", 1946 * 1947 */ 1948 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1949 .capability = ARM64_HW_DBM, 1950 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1951 .sign = FTR_UNSIGNED, 1952 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1953 .min_field_value = 2, 1954 .matches = has_hw_dbm, 1955 .cpu_enable = cpu_enable_hw_dbm, 1956 }, 1957 #endif 1958 { 1959 .desc = "CRC32 instructions", 1960 .capability = ARM64_HAS_CRC32, 1961 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1962 .matches = has_cpuid_feature, 1963 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1964 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1965 .min_field_value = 1, 1966 }, 1967 { 1968 .desc = "Speculative Store Bypassing Safe (SSBS)", 1969 .capability = ARM64_SSBS, 1970 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1971 .matches = has_cpuid_feature, 1972 .sys_reg = SYS_ID_AA64PFR1_EL1, 1973 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1974 .sign = FTR_UNSIGNED, 1975 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1976 }, 1977 #ifdef CONFIG_ARM64_CNP 1978 { 1979 .desc = "Common not Private translations", 1980 .capability = ARM64_HAS_CNP, 1981 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1982 .matches = has_useable_cnp, 1983 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1984 .sign = FTR_UNSIGNED, 1985 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 1986 .min_field_value = 1, 1987 .cpu_enable = cpu_enable_cnp, 1988 }, 1989 #endif 1990 { 1991 .desc = "Speculation barrier (SB)", 1992 .capability = ARM64_HAS_SB, 1993 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1994 .matches = has_cpuid_feature, 1995 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1996 .field_pos = ID_AA64ISAR1_SB_SHIFT, 1997 .sign = FTR_UNSIGNED, 1998 .min_field_value = 1, 1999 }, 2000 #ifdef CONFIG_ARM64_PTR_AUTH 2001 { 2002 .desc = "Address authentication (architected algorithm)", 2003 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2004 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2005 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2006 .sign = FTR_UNSIGNED, 2007 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2008 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2009 .matches = has_address_auth_cpucap, 2010 }, 2011 { 2012 .desc = "Address authentication (IMP DEF algorithm)", 2013 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2014 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2015 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2016 .sign = FTR_UNSIGNED, 2017 .field_pos = ID_AA64ISAR1_API_SHIFT, 2018 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2019 .matches = has_address_auth_cpucap, 2020 }, 2021 { 2022 .capability = ARM64_HAS_ADDRESS_AUTH, 2023 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2024 .matches = has_address_auth_metacap, 2025 }, 2026 { 2027 .desc = "Generic authentication (architected algorithm)", 2028 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2029 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2030 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2031 .sign = FTR_UNSIGNED, 2032 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2033 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2034 .matches = has_cpuid_feature, 2035 }, 2036 { 2037 .desc = "Generic authentication (IMP DEF algorithm)", 2038 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2039 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2040 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2041 .sign = FTR_UNSIGNED, 2042 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2043 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2044 .matches = has_cpuid_feature, 2045 }, 2046 { 2047 .capability = ARM64_HAS_GENERIC_AUTH, 2048 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2049 .matches = has_generic_auth, 2050 }, 2051 #endif /* CONFIG_ARM64_PTR_AUTH */ 2052 #ifdef CONFIG_ARM64_PSEUDO_NMI 2053 { 2054 /* 2055 * Depends on having GICv3 2056 */ 2057 .desc = "IRQ priority masking", 2058 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2059 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2060 .matches = can_use_gic_priorities, 2061 .sys_reg = SYS_ID_AA64PFR0_EL1, 2062 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2063 .sign = FTR_UNSIGNED, 2064 .min_field_value = 1, 2065 }, 2066 #endif 2067 #ifdef CONFIG_ARM64_E0PD 2068 { 2069 .desc = "E0PD", 2070 .capability = ARM64_HAS_E0PD, 2071 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2072 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2073 .sign = FTR_UNSIGNED, 2074 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2075 .matches = has_cpuid_feature, 2076 .min_field_value = 1, 2077 .cpu_enable = cpu_enable_e0pd, 2078 }, 2079 #endif 2080 #ifdef CONFIG_ARCH_RANDOM 2081 { 2082 .desc = "Random Number Generator", 2083 .capability = ARM64_HAS_RNG, 2084 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2085 .matches = has_cpuid_feature, 2086 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2087 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2088 .sign = FTR_UNSIGNED, 2089 .min_field_value = 1, 2090 }, 2091 #endif 2092 #ifdef CONFIG_ARM64_BTI 2093 { 2094 .desc = "Branch Target Identification", 2095 .capability = ARM64_BTI, 2096 #ifdef CONFIG_ARM64_BTI_KERNEL 2097 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2098 #else 2099 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2100 #endif 2101 .matches = has_cpuid_feature, 2102 .cpu_enable = bti_enable, 2103 .sys_reg = SYS_ID_AA64PFR1_EL1, 2104 .field_pos = ID_AA64PFR1_BT_SHIFT, 2105 .min_field_value = ID_AA64PFR1_BT_BTI, 2106 .sign = FTR_UNSIGNED, 2107 }, 2108 #endif 2109 #ifdef CONFIG_ARM64_MTE 2110 { 2111 .desc = "Memory Tagging Extension", 2112 .capability = ARM64_MTE, 2113 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2114 .matches = has_cpuid_feature, 2115 .sys_reg = SYS_ID_AA64PFR1_EL1, 2116 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2117 .min_field_value = ID_AA64PFR1_MTE, 2118 .sign = FTR_UNSIGNED, 2119 .cpu_enable = cpu_enable_mte, 2120 }, 2121 #endif /* CONFIG_ARM64_MTE */ 2122 { 2123 .desc = "RCpc load-acquire (LDAPR)", 2124 .capability = ARM64_HAS_LDAPR, 2125 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2126 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2127 .sign = FTR_UNSIGNED, 2128 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2129 .matches = has_cpuid_feature, 2130 .min_field_value = 1, 2131 }, 2132 {}, 2133 }; 2134 2135 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2136 .matches = has_cpuid_feature, \ 2137 .sys_reg = reg, \ 2138 .field_pos = field, \ 2139 .sign = s, \ 2140 .min_field_value = min_value, 2141 2142 #define __HWCAP_CAP(name, cap_type, cap) \ 2143 .desc = name, \ 2144 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2145 .hwcap_type = cap_type, \ 2146 .hwcap = cap, \ 2147 2148 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2149 { \ 2150 __HWCAP_CAP(#cap, cap_type, cap) \ 2151 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2152 } 2153 2154 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2155 { \ 2156 __HWCAP_CAP(#cap, cap_type, cap) \ 2157 .matches = cpucap_multi_entry_cap_matches, \ 2158 .match_list = list, \ 2159 } 2160 2161 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2162 { \ 2163 __HWCAP_CAP(#cap, cap_type, cap) \ 2164 .matches = match, \ 2165 } 2166 2167 #ifdef CONFIG_ARM64_PTR_AUTH 2168 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2169 { 2170 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2171 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2172 }, 2173 { 2174 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2175 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2176 }, 2177 {}, 2178 }; 2179 2180 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2181 { 2182 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2183 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2184 }, 2185 { 2186 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2187 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2188 }, 2189 {}, 2190 }; 2191 #endif 2192 2193 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2194 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2195 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2196 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2197 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2198 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2199 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2200 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2201 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2202 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2203 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2204 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2205 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2206 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2207 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2208 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2209 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2210 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2211 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2212 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2213 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2214 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2215 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2216 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2217 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2218 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2219 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2220 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2221 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2222 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2223 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2224 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2225 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2226 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2227 #ifdef CONFIG_ARM64_SVE 2228 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2229 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2230 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2231 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2232 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2233 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2234 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2235 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2236 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2237 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2238 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2239 #endif 2240 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2241 #ifdef CONFIG_ARM64_BTI 2242 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2243 #endif 2244 #ifdef CONFIG_ARM64_PTR_AUTH 2245 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2246 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2247 #endif 2248 #ifdef CONFIG_ARM64_MTE 2249 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2250 #endif /* CONFIG_ARM64_MTE */ 2251 {}, 2252 }; 2253 2254 #ifdef CONFIG_COMPAT 2255 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2256 { 2257 /* 2258 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2259 * in line with that of arm32 as in vfp_init(). We make sure that the 2260 * check is future proof, by making sure value is non-zero. 2261 */ 2262 u32 mvfr1; 2263 2264 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2265 if (scope == SCOPE_SYSTEM) 2266 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2267 else 2268 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2269 2270 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2271 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2272 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2273 } 2274 #endif 2275 2276 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2277 #ifdef CONFIG_COMPAT 2278 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2279 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2280 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2281 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2282 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2283 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2284 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2285 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2286 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2287 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2288 #endif 2289 {}, 2290 }; 2291 2292 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2293 { 2294 switch (cap->hwcap_type) { 2295 case CAP_HWCAP: 2296 cpu_set_feature(cap->hwcap); 2297 break; 2298 #ifdef CONFIG_COMPAT 2299 case CAP_COMPAT_HWCAP: 2300 compat_elf_hwcap |= (u32)cap->hwcap; 2301 break; 2302 case CAP_COMPAT_HWCAP2: 2303 compat_elf_hwcap2 |= (u32)cap->hwcap; 2304 break; 2305 #endif 2306 default: 2307 WARN_ON(1); 2308 break; 2309 } 2310 } 2311 2312 /* Check if we have a particular HWCAP enabled */ 2313 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2314 { 2315 bool rc; 2316 2317 switch (cap->hwcap_type) { 2318 case CAP_HWCAP: 2319 rc = cpu_have_feature(cap->hwcap); 2320 break; 2321 #ifdef CONFIG_COMPAT 2322 case CAP_COMPAT_HWCAP: 2323 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2324 break; 2325 case CAP_COMPAT_HWCAP2: 2326 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2327 break; 2328 #endif 2329 default: 2330 WARN_ON(1); 2331 rc = false; 2332 } 2333 2334 return rc; 2335 } 2336 2337 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2338 { 2339 /* We support emulation of accesses to CPU ID feature registers */ 2340 cpu_set_named_feature(CPUID); 2341 for (; hwcaps->matches; hwcaps++) 2342 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2343 cap_set_elf_hwcap(hwcaps); 2344 } 2345 2346 static void update_cpu_capabilities(u16 scope_mask) 2347 { 2348 int i; 2349 const struct arm64_cpu_capabilities *caps; 2350 2351 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2352 for (i = 0; i < ARM64_NCAPS; i++) { 2353 caps = cpu_hwcaps_ptrs[i]; 2354 if (!caps || !(caps->type & scope_mask) || 2355 cpus_have_cap(caps->capability) || 2356 !caps->matches(caps, cpucap_default_scope(caps))) 2357 continue; 2358 2359 if (caps->desc) 2360 pr_info("detected: %s\n", caps->desc); 2361 cpus_set_cap(caps->capability); 2362 2363 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2364 set_bit(caps->capability, boot_capabilities); 2365 } 2366 } 2367 2368 /* 2369 * Enable all the available capabilities on this CPU. The capabilities 2370 * with BOOT_CPU scope are handled separately and hence skipped here. 2371 */ 2372 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2373 { 2374 int i; 2375 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2376 2377 for_each_available_cap(i) { 2378 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2379 2380 if (WARN_ON(!cap)) 2381 continue; 2382 2383 if (!(cap->type & non_boot_scope)) 2384 continue; 2385 2386 if (cap->cpu_enable) 2387 cap->cpu_enable(cap); 2388 } 2389 return 0; 2390 } 2391 2392 /* 2393 * Run through the enabled capabilities and enable() it on all active 2394 * CPUs 2395 */ 2396 static void __init enable_cpu_capabilities(u16 scope_mask) 2397 { 2398 int i; 2399 const struct arm64_cpu_capabilities *caps; 2400 bool boot_scope; 2401 2402 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2403 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2404 2405 for (i = 0; i < ARM64_NCAPS; i++) { 2406 unsigned int num; 2407 2408 caps = cpu_hwcaps_ptrs[i]; 2409 if (!caps || !(caps->type & scope_mask)) 2410 continue; 2411 num = caps->capability; 2412 if (!cpus_have_cap(num)) 2413 continue; 2414 2415 /* Ensure cpus_have_const_cap(num) works */ 2416 static_branch_enable(&cpu_hwcap_keys[num]); 2417 2418 if (boot_scope && caps->cpu_enable) 2419 /* 2420 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2421 * before any secondary CPU boots. Thus, each secondary 2422 * will enable the capability as appropriate via 2423 * check_local_cpu_capabilities(). The only exception is 2424 * the boot CPU, for which the capability must be 2425 * enabled here. This approach avoids costly 2426 * stop_machine() calls for this case. 2427 */ 2428 caps->cpu_enable(caps); 2429 } 2430 2431 /* 2432 * For all non-boot scope capabilities, use stop_machine() 2433 * as it schedules the work allowing us to modify PSTATE, 2434 * instead of on_each_cpu() which uses an IPI, giving us a 2435 * PSTATE that disappears when we return. 2436 */ 2437 if (!boot_scope) 2438 stop_machine(cpu_enable_non_boot_scope_capabilities, 2439 NULL, cpu_online_mask); 2440 } 2441 2442 /* 2443 * Run through the list of capabilities to check for conflicts. 2444 * If the system has already detected a capability, take necessary 2445 * action on this CPU. 2446 */ 2447 static void verify_local_cpu_caps(u16 scope_mask) 2448 { 2449 int i; 2450 bool cpu_has_cap, system_has_cap; 2451 const struct arm64_cpu_capabilities *caps; 2452 2453 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2454 2455 for (i = 0; i < ARM64_NCAPS; i++) { 2456 caps = cpu_hwcaps_ptrs[i]; 2457 if (!caps || !(caps->type & scope_mask)) 2458 continue; 2459 2460 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2461 system_has_cap = cpus_have_cap(caps->capability); 2462 2463 if (system_has_cap) { 2464 /* 2465 * Check if the new CPU misses an advertised feature, 2466 * which is not safe to miss. 2467 */ 2468 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2469 break; 2470 /* 2471 * We have to issue cpu_enable() irrespective of 2472 * whether the CPU has it or not, as it is enabeld 2473 * system wide. It is upto the call back to take 2474 * appropriate action on this CPU. 2475 */ 2476 if (caps->cpu_enable) 2477 caps->cpu_enable(caps); 2478 } else { 2479 /* 2480 * Check if the CPU has this capability if it isn't 2481 * safe to have when the system doesn't. 2482 */ 2483 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2484 break; 2485 } 2486 } 2487 2488 if (i < ARM64_NCAPS) { 2489 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2490 smp_processor_id(), caps->capability, 2491 caps->desc, system_has_cap, cpu_has_cap); 2492 2493 if (cpucap_panic_on_conflict(caps)) 2494 cpu_panic_kernel(); 2495 else 2496 cpu_die_early(); 2497 } 2498 } 2499 2500 /* 2501 * Check for CPU features that are used in early boot 2502 * based on the Boot CPU value. 2503 */ 2504 static void check_early_cpu_features(void) 2505 { 2506 verify_cpu_asid_bits(); 2507 2508 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2509 } 2510 2511 static void 2512 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2513 { 2514 2515 for (; caps->matches; caps++) 2516 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2517 pr_crit("CPU%d: missing HWCAP: %s\n", 2518 smp_processor_id(), caps->desc); 2519 cpu_die_early(); 2520 } 2521 } 2522 2523 static void verify_sve_features(void) 2524 { 2525 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2526 u64 zcr = read_zcr_features(); 2527 2528 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2529 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2530 2531 if (len < safe_len || sve_verify_vq_map()) { 2532 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2533 smp_processor_id()); 2534 cpu_die_early(); 2535 } 2536 2537 /* Add checks on other ZCR bits here if necessary */ 2538 } 2539 2540 static void verify_hyp_capabilities(void) 2541 { 2542 u64 safe_mmfr1, mmfr0, mmfr1; 2543 int parange, ipa_max; 2544 unsigned int safe_vmid_bits, vmid_bits; 2545 2546 if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST)) 2547 return; 2548 2549 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2550 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2551 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2552 2553 /* Verify VMID bits */ 2554 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2555 vmid_bits = get_vmid_bits(mmfr1); 2556 if (vmid_bits < safe_vmid_bits) { 2557 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2558 cpu_die_early(); 2559 } 2560 2561 /* Verify IPA range */ 2562 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2563 ID_AA64MMFR0_PARANGE_SHIFT); 2564 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2565 if (ipa_max < get_kvm_ipa_limit()) { 2566 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2567 cpu_die_early(); 2568 } 2569 } 2570 2571 /* 2572 * Run through the enabled system capabilities and enable() it on this CPU. 2573 * The capabilities were decided based on the available CPUs at the boot time. 2574 * Any new CPU should match the system wide status of the capability. If the 2575 * new CPU doesn't have a capability which the system now has enabled, we 2576 * cannot do anything to fix it up and could cause unexpected failures. So 2577 * we park the CPU. 2578 */ 2579 static void verify_local_cpu_capabilities(void) 2580 { 2581 /* 2582 * The capabilities with SCOPE_BOOT_CPU are checked from 2583 * check_early_cpu_features(), as they need to be verified 2584 * on all secondary CPUs. 2585 */ 2586 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2587 2588 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2589 2590 if (system_supports_32bit_el0()) 2591 verify_local_elf_hwcaps(compat_elf_hwcaps); 2592 2593 if (system_supports_sve()) 2594 verify_sve_features(); 2595 2596 if (is_hyp_mode_available()) 2597 verify_hyp_capabilities(); 2598 } 2599 2600 void check_local_cpu_capabilities(void) 2601 { 2602 /* 2603 * All secondary CPUs should conform to the early CPU features 2604 * in use by the kernel based on boot CPU. 2605 */ 2606 check_early_cpu_features(); 2607 2608 /* 2609 * If we haven't finalised the system capabilities, this CPU gets 2610 * a chance to update the errata work arounds and local features. 2611 * Otherwise, this CPU should verify that it has all the system 2612 * advertised capabilities. 2613 */ 2614 if (!system_capabilities_finalized()) 2615 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2616 else 2617 verify_local_cpu_capabilities(); 2618 } 2619 2620 static void __init setup_boot_cpu_capabilities(void) 2621 { 2622 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2623 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2624 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2625 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2626 } 2627 2628 bool this_cpu_has_cap(unsigned int n) 2629 { 2630 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2631 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2632 2633 if (cap) 2634 return cap->matches(cap, SCOPE_LOCAL_CPU); 2635 } 2636 2637 return false; 2638 } 2639 2640 /* 2641 * This helper function is used in a narrow window when, 2642 * - The system wide safe registers are set with all the SMP CPUs and, 2643 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2644 * In all other cases cpus_have_{const_}cap() should be used. 2645 */ 2646 static bool __maybe_unused __system_matches_cap(unsigned int n) 2647 { 2648 if (n < ARM64_NCAPS) { 2649 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2650 2651 if (cap) 2652 return cap->matches(cap, SCOPE_SYSTEM); 2653 } 2654 return false; 2655 } 2656 2657 void cpu_set_feature(unsigned int num) 2658 { 2659 WARN_ON(num >= MAX_CPU_FEATURES); 2660 elf_hwcap |= BIT(num); 2661 } 2662 EXPORT_SYMBOL_GPL(cpu_set_feature); 2663 2664 bool cpu_have_feature(unsigned int num) 2665 { 2666 WARN_ON(num >= MAX_CPU_FEATURES); 2667 return elf_hwcap & BIT(num); 2668 } 2669 EXPORT_SYMBOL_GPL(cpu_have_feature); 2670 2671 unsigned long cpu_get_elf_hwcap(void) 2672 { 2673 /* 2674 * We currently only populate the first 32 bits of AT_HWCAP. Please 2675 * note that for userspace compatibility we guarantee that bits 62 2676 * and 63 will always be returned as 0. 2677 */ 2678 return lower_32_bits(elf_hwcap); 2679 } 2680 2681 unsigned long cpu_get_elf_hwcap2(void) 2682 { 2683 return upper_32_bits(elf_hwcap); 2684 } 2685 2686 static void __init setup_system_capabilities(void) 2687 { 2688 /* 2689 * We have finalised the system-wide safe feature 2690 * registers, finalise the capabilities that depend 2691 * on it. Also enable all the available capabilities, 2692 * that are not enabled already. 2693 */ 2694 update_cpu_capabilities(SCOPE_SYSTEM); 2695 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2696 } 2697 2698 void __init setup_cpu_features(void) 2699 { 2700 u32 cwg; 2701 2702 setup_system_capabilities(); 2703 setup_elf_hwcaps(arm64_elf_hwcaps); 2704 2705 if (system_supports_32bit_el0()) 2706 setup_elf_hwcaps(compat_elf_hwcaps); 2707 2708 if (system_uses_ttbr0_pan()) 2709 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2710 2711 sve_setup(); 2712 minsigstksz_setup(); 2713 2714 /* Advertise that we have computed the system capabilities */ 2715 finalize_system_capabilities(); 2716 2717 /* 2718 * Check for sane CTR_EL0.CWG value. 2719 */ 2720 cwg = cache_type_cwg(); 2721 if (!cwg) 2722 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2723 ARCH_DMA_MINALIGN); 2724 } 2725 2726 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2727 { 2728 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2729 } 2730 2731 /* 2732 * We emulate only the following system register space. 2733 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2734 * See Table C5-6 System instruction encodings for System register accesses, 2735 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2736 */ 2737 static inline bool __attribute_const__ is_emulated(u32 id) 2738 { 2739 return (sys_reg_Op0(id) == 0x3 && 2740 sys_reg_CRn(id) == 0x0 && 2741 sys_reg_Op1(id) == 0x0 && 2742 (sys_reg_CRm(id) == 0 || 2743 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2744 } 2745 2746 /* 2747 * With CRm == 0, reg should be one of : 2748 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2749 */ 2750 static inline int emulate_id_reg(u32 id, u64 *valp) 2751 { 2752 switch (id) { 2753 case SYS_MIDR_EL1: 2754 *valp = read_cpuid_id(); 2755 break; 2756 case SYS_MPIDR_EL1: 2757 *valp = SYS_MPIDR_SAFE_VAL; 2758 break; 2759 case SYS_REVIDR_EL1: 2760 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2761 *valp = 0; 2762 break; 2763 default: 2764 return -EINVAL; 2765 } 2766 2767 return 0; 2768 } 2769 2770 static int emulate_sys_reg(u32 id, u64 *valp) 2771 { 2772 struct arm64_ftr_reg *regp; 2773 2774 if (!is_emulated(id)) 2775 return -EINVAL; 2776 2777 if (sys_reg_CRm(id) == 0) 2778 return emulate_id_reg(id, valp); 2779 2780 regp = get_arm64_ftr_reg_nowarn(id); 2781 if (regp) 2782 *valp = arm64_ftr_reg_user_value(regp); 2783 else 2784 /* 2785 * The untracked registers are either IMPLEMENTATION DEFINED 2786 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2787 */ 2788 *valp = 0; 2789 return 0; 2790 } 2791 2792 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2793 { 2794 int rc; 2795 u64 val; 2796 2797 rc = emulate_sys_reg(sys_reg, &val); 2798 if (!rc) { 2799 pt_regs_write_reg(regs, rt, val); 2800 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2801 } 2802 return rc; 2803 } 2804 2805 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2806 { 2807 u32 sys_reg, rt; 2808 2809 /* 2810 * sys_reg values are defined as used in mrs/msr instruction. 2811 * shift the imm value to get the encoding. 2812 */ 2813 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2814 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2815 return do_emulate_mrs(regs, sys_reg, rt); 2816 } 2817 2818 static struct undef_hook mrs_hook = { 2819 .instr_mask = 0xfff00000, 2820 .instr_val = 0xd5300000, 2821 .pstate_mask = PSR_AA32_MODE_MASK, 2822 .pstate_val = PSR_MODE_EL0t, 2823 .fn = emulate_mrs, 2824 }; 2825 2826 static int __init enable_mrs_emulation(void) 2827 { 2828 register_undef_hook(&mrs_hook); 2829 return 0; 2830 } 2831 2832 core_initcall(enable_mrs_emulation); 2833 2834 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2835 char *buf) 2836 { 2837 if (__meltdown_safe) 2838 return sprintf(buf, "Not affected\n"); 2839 2840 if (arm64_kernel_unmapped_at_el0()) 2841 return sprintf(buf, "Mitigation: PTI\n"); 2842 2843 return sprintf(buf, "Vulnerable\n"); 2844 } 2845