1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 #endif 107 108 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 109 EXPORT_SYMBOL(cpu_hwcaps); 110 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 111 112 DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 void dump_cpu_features(void) 138 { 139 /* file-wide pr_fmt adds "CPU features: " prefix */ 140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 141 } 142 143 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 144 .sys_reg = SYS_##reg, \ 145 .field_pos = reg##_##field##_SHIFT, \ 146 .field_width = reg##_##field##_WIDTH, \ 147 .sign = reg##_##field##_SIGNED, \ 148 .min_field_value = reg##_##field##_##min_value, 149 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 { \ 152 .sign = SIGNED, \ 153 .visible = VISIBLE, \ 154 .strict = STRICT, \ 155 .type = TYPE, \ 156 .shift = SHIFT, \ 157 .width = WIDTH, \ 158 .safe_val = SAFE_VAL, \ 159 } 160 161 /* Define a feature with unsigned values */ 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 163 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 164 165 /* Define a feature with a signed value */ 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 167 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 168 169 #define ARM64_FTR_END \ 170 { \ 171 .width = 0, \ 172 } 173 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 175 176 static bool __system_matches_cap(unsigned int n); 177 178 /* 179 * NOTE: Any changes to the visibility of features should be kept in 180 * sync with the documentation of the CPU feature register ABI. 181 */ 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 197 ARM64_FTR_END, 198 }; 199 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 210 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 215 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 217 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 227 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 229 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 232 ARM64_FTR_END, 233 }; 234 235 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 246 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 247 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 252 ARM64_FTR_END, 253 }; 254 255 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 269 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 270 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 287 ARM64_FTR_END, 288 }; 289 290 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 292 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 293 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 294 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 296 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 298 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 300 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 314 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 315 ARM64_FTR_END, 316 }; 317 318 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 319 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 322 /* 323 * Page size not being supported at Stage-2 is not fatal. You 324 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 325 * your favourite nesting hypervisor. 326 * 327 * There is a small corner case where the hypervisor explicitly 328 * advertises a given granule size at Stage-2 (value 2) on some 329 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 330 * vCPUs. Although this is not forbidden by the architecture, it 331 * indicates that the hypervisor is being silly (or buggy). 332 * 333 * We make no effort to cope with this and pretend that if these 334 * fields are inconsistent across vCPUs, then it isn't worth 335 * trying to bring KVM up. 336 */ 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 340 /* 341 * We already refuse to boot CPUs that don't support our configured 342 * page size, so we can only detect mismatches for a page size other 343 * than the one we're currently using. Unfortunately, SoCs like this 344 * exist in the wild so, even though we don't like it, we'll have to go 345 * along with it and treat them as non-strict. 346 */ 347 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 348 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 350 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 352 /* Linux shouldn't care about secure memory */ 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 356 /* 357 * Differing PARange is fine as long as all peripherals and memory are mapped 358 * within the minimum PARange of all CPUs 359 */ 360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 361 ARM64_FTR_END, 362 }; 363 364 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 377 ARM64_FTR_END, 378 }; 379 380 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 396 ARM64_FTR_END, 397 }; 398 399 static const struct arm64_ftr_bits ftr_ctr[] = { 400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 406 /* 407 * Linux can handle differing I-cache policies. Userspace JITs will 408 * make use of *minLine. 409 * If we have differing I-cache policies, report it as the weakest - VIPT. 410 */ 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 413 ARM64_FTR_END, 414 }; 415 416 static struct arm64_ftr_override __ro_after_init no_override = { }; 417 418 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 419 .name = "SYS_CTR_EL0", 420 .ftr_bits = ftr_ctr, 421 .override = &no_override, 422 }; 423 424 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 425 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 430 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 433 ARM64_FTR_END, 434 }; 435 436 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 437 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 442 /* 443 * We can instantiate multiple PMU instances with different levels 444 * of support. 445 */ 446 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 448 ARM64_FTR_END, 449 }; 450 451 static const struct arm64_ftr_bits ftr_mvfr0[] = { 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 460 ARM64_FTR_END, 461 }; 462 463 static const struct arm64_ftr_bits ftr_mvfr1[] = { 464 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 472 ARM64_FTR_END, 473 }; 474 475 static const struct arm64_ftr_bits ftr_mvfr2[] = { 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_dczid[] = { 482 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 483 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 484 ARM64_FTR_END, 485 }; 486 487 static const struct arm64_ftr_bits ftr_gmid[] = { 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 489 ARM64_FTR_END, 490 }; 491 492 static const struct arm64_ftr_bits ftr_id_isar0[] = { 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 500 ARM64_FTR_END, 501 }; 502 503 static const struct arm64_ftr_bits ftr_id_isar5[] = { 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 521 522 /* 523 * SpecSEI = 1 indicates that the PE might generate an SError on an 524 * external abort on speculative read. It is safe to assume that an 525 * SError might be generated than it will not be. Hence it has been 526 * classified as FTR_HIGHER_SAFE. 527 */ 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 529 ARM64_FTR_END, 530 }; 531 532 static const struct arm64_ftr_bits ftr_id_isar4[] = { 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 541 ARM64_FTR_END, 542 }; 543 544 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 546 ARM64_FTR_END, 547 }; 548 549 static const struct arm64_ftr_bits ftr_id_isar6[] = { 550 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 557 ARM64_FTR_END, 558 }; 559 560 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 567 ARM64_FTR_END, 568 }; 569 570 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 579 ARM64_FTR_END, 580 }; 581 582 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 583 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 585 ARM64_FTR_END, 586 }; 587 588 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 589 /* [31:28] TraceFilt */ 590 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 593 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 594 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 596 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 597 ARM64_FTR_END, 598 }; 599 600 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 601 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 602 ARM64_FTR_END, 603 }; 604 605 static const struct arm64_ftr_bits ftr_zcr[] = { 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 607 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */ 608 ARM64_FTR_END, 609 }; 610 611 static const struct arm64_ftr_bits ftr_smcr[] = { 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 613 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */ 614 ARM64_FTR_END, 615 }; 616 617 /* 618 * Common ftr bits for a 32bit register with all hidden, strict 619 * attributes, with 4bit feature fields and a default safe value of 620 * 0. Covers the following 32bit registers: 621 * id_isar[1-3], id_mmfr[1-3] 622 */ 623 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 632 ARM64_FTR_END, 633 }; 634 635 /* Table for a single 32bit feature value */ 636 static const struct arm64_ftr_bits ftr_single32[] = { 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 638 ARM64_FTR_END, 639 }; 640 641 static const struct arm64_ftr_bits ftr_raz[] = { 642 ARM64_FTR_END, 643 }; 644 645 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 646 .sys_id = id, \ 647 .reg = &(struct arm64_ftr_reg){ \ 648 .name = id_str, \ 649 .override = (ovr), \ 650 .ftr_bits = &((table)[0]), \ 651 }} 652 653 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 654 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 655 656 #define ARM64_FTR_REG(id, table) \ 657 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 658 659 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 660 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 661 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 662 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 663 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 664 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 665 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 666 667 static const struct __ftr_reg_entry { 668 u32 sys_id; 669 struct arm64_ftr_reg *reg; 670 } arm64_ftr_regs[] = { 671 672 /* Op1 = 0, CRn = 0, CRm = 1 */ 673 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 674 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 675 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 676 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 677 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 678 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 679 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 680 681 /* Op1 = 0, CRn = 0, CRm = 2 */ 682 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 683 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 684 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 685 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 686 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 687 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 688 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 689 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 690 691 /* Op1 = 0, CRn = 0, CRm = 3 */ 692 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 693 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 694 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 695 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 696 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 697 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 698 699 /* Op1 = 0, CRn = 0, CRm = 4 */ 700 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 701 &id_aa64pfr0_override), 702 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 703 &id_aa64pfr1_override), 704 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 705 &id_aa64zfr0_override), 706 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 707 &id_aa64smfr0_override), 708 709 /* Op1 = 0, CRn = 0, CRm = 5 */ 710 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 711 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 712 713 /* Op1 = 0, CRn = 0, CRm = 6 */ 714 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 715 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 716 &id_aa64isar1_override), 717 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 718 &id_aa64isar2_override), 719 720 /* Op1 = 0, CRn = 0, CRm = 7 */ 721 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 722 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 723 &id_aa64mmfr1_override), 724 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 725 726 /* Op1 = 0, CRn = 1, CRm = 2 */ 727 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 728 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr), 729 730 /* Op1 = 1, CRn = 0, CRm = 0 */ 731 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 732 733 /* Op1 = 3, CRn = 0, CRm = 0 */ 734 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 735 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 736 737 /* Op1 = 3, CRn = 14, CRm = 0 */ 738 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 739 }; 740 741 static int search_cmp_ftr_reg(const void *id, const void *regp) 742 { 743 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 744 } 745 746 /* 747 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 748 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 749 * ascending order of sys_id, we use binary search to find a matching 750 * entry. 751 * 752 * returns - Upon success, matching ftr_reg entry for id. 753 * - NULL on failure. It is upto the caller to decide 754 * the impact of a failure. 755 */ 756 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 757 { 758 const struct __ftr_reg_entry *ret; 759 760 ret = bsearch((const void *)(unsigned long)sys_id, 761 arm64_ftr_regs, 762 ARRAY_SIZE(arm64_ftr_regs), 763 sizeof(arm64_ftr_regs[0]), 764 search_cmp_ftr_reg); 765 if (ret) 766 return ret->reg; 767 return NULL; 768 } 769 770 /* 771 * get_arm64_ftr_reg - Looks up a feature register entry using 772 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 773 * 774 * returns - Upon success, matching ftr_reg entry for id. 775 * - NULL on failure but with an WARN_ON(). 776 */ 777 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 778 { 779 struct arm64_ftr_reg *reg; 780 781 reg = get_arm64_ftr_reg_nowarn(sys_id); 782 783 /* 784 * Requesting a non-existent register search is an error. Warn 785 * and let the caller handle it. 786 */ 787 WARN_ON(!reg); 788 return reg; 789 } 790 791 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 792 s64 ftr_val) 793 { 794 u64 mask = arm64_ftr_mask(ftrp); 795 796 reg &= ~mask; 797 reg |= (ftr_val << ftrp->shift) & mask; 798 return reg; 799 } 800 801 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 802 s64 cur) 803 { 804 s64 ret = 0; 805 806 switch (ftrp->type) { 807 case FTR_EXACT: 808 ret = ftrp->safe_val; 809 break; 810 case FTR_LOWER_SAFE: 811 ret = min(new, cur); 812 break; 813 case FTR_HIGHER_OR_ZERO_SAFE: 814 if (!cur || !new) 815 break; 816 fallthrough; 817 case FTR_HIGHER_SAFE: 818 ret = max(new, cur); 819 break; 820 default: 821 BUG(); 822 } 823 824 return ret; 825 } 826 827 static void __init sort_ftr_regs(void) 828 { 829 unsigned int i; 830 831 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 832 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 833 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 834 unsigned int j = 0; 835 836 /* 837 * Features here must be sorted in descending order with respect 838 * to their shift values and should not overlap with each other. 839 */ 840 for (; ftr_bits->width != 0; ftr_bits++, j++) { 841 unsigned int width = ftr_reg->ftr_bits[j].width; 842 unsigned int shift = ftr_reg->ftr_bits[j].shift; 843 unsigned int prev_shift; 844 845 WARN((shift + width) > 64, 846 "%s has invalid feature at shift %d\n", 847 ftr_reg->name, shift); 848 849 /* 850 * Skip the first feature. There is nothing to 851 * compare against for now. 852 */ 853 if (j == 0) 854 continue; 855 856 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 857 WARN((shift + width) > prev_shift, 858 "%s has feature overlap at shift %d\n", 859 ftr_reg->name, shift); 860 } 861 862 /* 863 * Skip the first register. There is nothing to 864 * compare against for now. 865 */ 866 if (i == 0) 867 continue; 868 /* 869 * Registers here must be sorted in ascending order with respect 870 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 871 * to work correctly. 872 */ 873 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 874 } 875 } 876 877 /* 878 * Initialise the CPU feature register from Boot CPU values. 879 * Also initiliases the strict_mask for the register. 880 * Any bits that are not covered by an arm64_ftr_bits entry are considered 881 * RES0 for the system-wide value, and must strictly match. 882 */ 883 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 884 { 885 u64 val = 0; 886 u64 strict_mask = ~0x0ULL; 887 u64 user_mask = 0; 888 u64 valid_mask = 0; 889 890 const struct arm64_ftr_bits *ftrp; 891 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 892 893 if (!reg) 894 return; 895 896 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 897 u64 ftr_mask = arm64_ftr_mask(ftrp); 898 s64 ftr_new = arm64_ftr_value(ftrp, new); 899 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 900 901 if ((ftr_mask & reg->override->mask) == ftr_mask) { 902 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 903 char *str = NULL; 904 905 if (ftr_ovr != tmp) { 906 /* Unsafe, remove the override */ 907 reg->override->mask &= ~ftr_mask; 908 reg->override->val &= ~ftr_mask; 909 tmp = ftr_ovr; 910 str = "ignoring override"; 911 } else if (ftr_new != tmp) { 912 /* Override was valid */ 913 ftr_new = tmp; 914 str = "forced"; 915 } else if (ftr_ovr == tmp) { 916 /* Override was the safe value */ 917 str = "already set"; 918 } 919 920 if (str) 921 pr_warn("%s[%d:%d]: %s to %llx\n", 922 reg->name, 923 ftrp->shift + ftrp->width - 1, 924 ftrp->shift, str, tmp); 925 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 926 reg->override->val &= ~ftr_mask; 927 pr_warn("%s[%d:%d]: impossible override, ignored\n", 928 reg->name, 929 ftrp->shift + ftrp->width - 1, 930 ftrp->shift); 931 } 932 933 val = arm64_ftr_set_value(ftrp, val, ftr_new); 934 935 valid_mask |= ftr_mask; 936 if (!ftrp->strict) 937 strict_mask &= ~ftr_mask; 938 if (ftrp->visible) 939 user_mask |= ftr_mask; 940 else 941 reg->user_val = arm64_ftr_set_value(ftrp, 942 reg->user_val, 943 ftrp->safe_val); 944 } 945 946 val &= valid_mask; 947 948 reg->sys_val = val; 949 reg->strict_mask = strict_mask; 950 reg->user_mask = user_mask; 951 } 952 953 extern const struct arm64_cpu_capabilities arm64_errata[]; 954 static const struct arm64_cpu_capabilities arm64_features[]; 955 956 static void __init 957 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 958 { 959 for (; caps->matches; caps++) { 960 if (WARN(caps->capability >= ARM64_NCAPS, 961 "Invalid capability %d\n", caps->capability)) 962 continue; 963 if (WARN(cpu_hwcaps_ptrs[caps->capability], 964 "Duplicate entry for capability %d\n", 965 caps->capability)) 966 continue; 967 cpu_hwcaps_ptrs[caps->capability] = caps; 968 } 969 } 970 971 static void __init init_cpu_hwcaps_indirect_list(void) 972 { 973 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 974 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 975 } 976 977 static void __init setup_boot_cpu_capabilities(void); 978 979 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 980 { 981 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 982 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 983 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 984 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 985 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 986 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 987 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 988 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 989 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 990 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 991 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 992 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 993 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 994 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 995 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 996 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 997 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 998 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 999 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1000 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1001 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1002 } 1003 1004 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1005 { 1006 /* Before we start using the tables, make sure it is sorted */ 1007 sort_ftr_regs(); 1008 1009 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1010 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1011 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1012 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1013 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1014 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1015 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1016 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1017 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1018 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1019 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1020 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1021 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1022 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1023 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1024 1025 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1026 init_32bit_cpu_features(&info->aarch32); 1027 1028 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1029 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1030 info->reg_zcr = read_zcr_features(); 1031 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 1032 vec_init_vq_map(ARM64_VEC_SVE); 1033 } 1034 1035 if (IS_ENABLED(CONFIG_ARM64_SME) && 1036 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1037 info->reg_smcr = read_smcr_features(); 1038 /* 1039 * We mask out SMPS since even if the hardware 1040 * supports priorities the kernel does not at present 1041 * and we block access to them. 1042 */ 1043 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1044 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr); 1045 vec_init_vq_map(ARM64_VEC_SME); 1046 } 1047 1048 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1049 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1050 1051 /* 1052 * Initialize the indirect array of CPU hwcaps capabilities pointers 1053 * before we handle the boot CPU below. 1054 */ 1055 init_cpu_hwcaps_indirect_list(); 1056 1057 /* 1058 * Detect and enable early CPU capabilities based on the boot CPU, 1059 * after we have initialised the CPU feature infrastructure. 1060 */ 1061 setup_boot_cpu_capabilities(); 1062 } 1063 1064 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1065 { 1066 const struct arm64_ftr_bits *ftrp; 1067 1068 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1069 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1070 s64 ftr_new = arm64_ftr_value(ftrp, new); 1071 1072 if (ftr_cur == ftr_new) 1073 continue; 1074 /* Find a safe value */ 1075 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1076 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1077 } 1078 1079 } 1080 1081 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1082 { 1083 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1084 1085 if (!regp) 1086 return 0; 1087 1088 update_cpu_ftr_reg(regp, val); 1089 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1090 return 0; 1091 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1092 regp->name, boot, cpu, val); 1093 return 1; 1094 } 1095 1096 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1097 { 1098 const struct arm64_ftr_bits *ftrp; 1099 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1100 1101 if (!regp) 1102 return; 1103 1104 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1105 if (ftrp->shift == field) { 1106 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1107 break; 1108 } 1109 } 1110 1111 /* Bogus field? */ 1112 WARN_ON(!ftrp->width); 1113 } 1114 1115 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1116 struct cpuinfo_arm64 *boot) 1117 { 1118 static bool boot_cpu_32bit_regs_overridden = false; 1119 1120 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1121 return; 1122 1123 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1124 return; 1125 1126 boot->aarch32 = info->aarch32; 1127 init_32bit_cpu_features(&boot->aarch32); 1128 boot_cpu_32bit_regs_overridden = true; 1129 } 1130 1131 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1132 struct cpuinfo_32bit *boot) 1133 { 1134 int taint = 0; 1135 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1136 1137 /* 1138 * If we don't have AArch32 at EL1, then relax the strictness of 1139 * EL1-dependent register fields to avoid spurious sanity check fails. 1140 */ 1141 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1142 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1143 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1144 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1145 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1146 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1147 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1148 } 1149 1150 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1151 info->reg_id_dfr0, boot->reg_id_dfr0); 1152 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1153 info->reg_id_dfr1, boot->reg_id_dfr1); 1154 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1155 info->reg_id_isar0, boot->reg_id_isar0); 1156 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1157 info->reg_id_isar1, boot->reg_id_isar1); 1158 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1159 info->reg_id_isar2, boot->reg_id_isar2); 1160 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1161 info->reg_id_isar3, boot->reg_id_isar3); 1162 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1163 info->reg_id_isar4, boot->reg_id_isar4); 1164 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1165 info->reg_id_isar5, boot->reg_id_isar5); 1166 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1167 info->reg_id_isar6, boot->reg_id_isar6); 1168 1169 /* 1170 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1171 * ACTLR formats could differ across CPUs and therefore would have to 1172 * be trapped for virtualization anyway. 1173 */ 1174 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1175 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1176 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1177 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1178 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1179 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1180 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1181 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1182 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1183 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1184 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1185 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1186 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1187 info->reg_id_pfr0, boot->reg_id_pfr0); 1188 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1189 info->reg_id_pfr1, boot->reg_id_pfr1); 1190 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1191 info->reg_id_pfr2, boot->reg_id_pfr2); 1192 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1193 info->reg_mvfr0, boot->reg_mvfr0); 1194 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1195 info->reg_mvfr1, boot->reg_mvfr1); 1196 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1197 info->reg_mvfr2, boot->reg_mvfr2); 1198 1199 return taint; 1200 } 1201 1202 /* 1203 * Update system wide CPU feature registers with the values from a 1204 * non-boot CPU. Also performs SANITY checks to make sure that there 1205 * aren't any insane variations from that of the boot CPU. 1206 */ 1207 void update_cpu_features(int cpu, 1208 struct cpuinfo_arm64 *info, 1209 struct cpuinfo_arm64 *boot) 1210 { 1211 int taint = 0; 1212 1213 /* 1214 * The kernel can handle differing I-cache policies, but otherwise 1215 * caches should look identical. Userspace JITs will make use of 1216 * *minLine. 1217 */ 1218 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1219 info->reg_ctr, boot->reg_ctr); 1220 1221 /* 1222 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1223 * could result in too much or too little memory being zeroed if a 1224 * process is preempted and migrated between CPUs. 1225 */ 1226 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1227 info->reg_dczid, boot->reg_dczid); 1228 1229 /* If different, timekeeping will be broken (especially with KVM) */ 1230 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1231 info->reg_cntfrq, boot->reg_cntfrq); 1232 1233 /* 1234 * The kernel uses self-hosted debug features and expects CPUs to 1235 * support identical debug features. We presently need CTX_CMPs, WRPs, 1236 * and BRPs to be identical. 1237 * ID_AA64DFR1 is currently RES0. 1238 */ 1239 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1240 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1241 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1242 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1243 /* 1244 * Even in big.LITTLE, processors should be identical instruction-set 1245 * wise. 1246 */ 1247 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1248 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1249 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1250 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1251 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1252 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1253 1254 /* 1255 * Differing PARange support is fine as long as all peripherals and 1256 * memory are mapped within the minimum PARange of all CPUs. 1257 * Linux should not care about secure memory. 1258 */ 1259 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1260 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1261 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1262 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1263 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1264 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1265 1266 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1267 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1268 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1269 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1270 1271 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1272 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1273 1274 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1275 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1276 1277 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1278 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1279 info->reg_zcr = read_zcr_features(); 1280 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1281 info->reg_zcr, boot->reg_zcr); 1282 1283 /* Probe vector lengths */ 1284 if (!system_capabilities_finalized()) 1285 vec_update_vq_map(ARM64_VEC_SVE); 1286 } 1287 1288 if (IS_ENABLED(CONFIG_ARM64_SME) && 1289 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1290 info->reg_smcr = read_smcr_features(); 1291 /* 1292 * We mask out SMPS since even if the hardware 1293 * supports priorities the kernel does not at present 1294 * and we block access to them. 1295 */ 1296 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1297 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu, 1298 info->reg_smcr, boot->reg_smcr); 1299 1300 /* Probe vector lengths */ 1301 if (!system_capabilities_finalized()) 1302 vec_update_vq_map(ARM64_VEC_SME); 1303 } 1304 1305 /* 1306 * The kernel uses the LDGM/STGM instructions and the number of tags 1307 * they read/write depends on the GMID_EL1.BS field. Check that the 1308 * value is the same on all CPUs. 1309 */ 1310 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1311 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1312 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1313 info->reg_gmid, boot->reg_gmid); 1314 } 1315 1316 /* 1317 * If we don't have AArch32 at all then skip the checks entirely 1318 * as the register values may be UNKNOWN and we're not going to be 1319 * using them for anything. 1320 * 1321 * This relies on a sanitised view of the AArch64 ID registers 1322 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1323 */ 1324 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1325 lazy_init_32bit_cpu_features(info, boot); 1326 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1327 &boot->aarch32); 1328 } 1329 1330 /* 1331 * Mismatched CPU features are a recipe for disaster. Don't even 1332 * pretend to support them. 1333 */ 1334 if (taint) { 1335 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1336 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1337 } 1338 } 1339 1340 u64 read_sanitised_ftr_reg(u32 id) 1341 { 1342 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1343 1344 if (!regp) 1345 return 0; 1346 return regp->sys_val; 1347 } 1348 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1349 1350 #define read_sysreg_case(r) \ 1351 case r: val = read_sysreg_s(r); break; 1352 1353 /* 1354 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1355 * Read the system register on the current CPU 1356 */ 1357 u64 __read_sysreg_by_encoding(u32 sys_id) 1358 { 1359 struct arm64_ftr_reg *regp; 1360 u64 val; 1361 1362 switch (sys_id) { 1363 read_sysreg_case(SYS_ID_PFR0_EL1); 1364 read_sysreg_case(SYS_ID_PFR1_EL1); 1365 read_sysreg_case(SYS_ID_PFR2_EL1); 1366 read_sysreg_case(SYS_ID_DFR0_EL1); 1367 read_sysreg_case(SYS_ID_DFR1_EL1); 1368 read_sysreg_case(SYS_ID_MMFR0_EL1); 1369 read_sysreg_case(SYS_ID_MMFR1_EL1); 1370 read_sysreg_case(SYS_ID_MMFR2_EL1); 1371 read_sysreg_case(SYS_ID_MMFR3_EL1); 1372 read_sysreg_case(SYS_ID_MMFR4_EL1); 1373 read_sysreg_case(SYS_ID_MMFR5_EL1); 1374 read_sysreg_case(SYS_ID_ISAR0_EL1); 1375 read_sysreg_case(SYS_ID_ISAR1_EL1); 1376 read_sysreg_case(SYS_ID_ISAR2_EL1); 1377 read_sysreg_case(SYS_ID_ISAR3_EL1); 1378 read_sysreg_case(SYS_ID_ISAR4_EL1); 1379 read_sysreg_case(SYS_ID_ISAR5_EL1); 1380 read_sysreg_case(SYS_ID_ISAR6_EL1); 1381 read_sysreg_case(SYS_MVFR0_EL1); 1382 read_sysreg_case(SYS_MVFR1_EL1); 1383 read_sysreg_case(SYS_MVFR2_EL1); 1384 1385 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1386 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1387 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1388 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1389 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1390 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1391 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1392 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1393 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1394 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1395 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1396 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1397 1398 read_sysreg_case(SYS_CNTFRQ_EL0); 1399 read_sysreg_case(SYS_CTR_EL0); 1400 read_sysreg_case(SYS_DCZID_EL0); 1401 1402 default: 1403 BUG(); 1404 return 0; 1405 } 1406 1407 regp = get_arm64_ftr_reg(sys_id); 1408 if (regp) { 1409 val &= ~regp->override->mask; 1410 val |= (regp->override->val & regp->override->mask); 1411 } 1412 1413 return val; 1414 } 1415 1416 #include <linux/irqchip/arm-gic-v3.h> 1417 1418 static bool 1419 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1420 { 1421 return true; 1422 } 1423 1424 static bool 1425 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1426 { 1427 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1428 entry->field_width, 1429 entry->sign); 1430 1431 return val >= entry->min_field_value; 1432 } 1433 1434 static u64 1435 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1436 { 1437 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1438 if (scope == SCOPE_SYSTEM) 1439 return read_sanitised_ftr_reg(entry->sys_reg); 1440 else 1441 return __read_sysreg_by_encoding(entry->sys_reg); 1442 } 1443 1444 static bool 1445 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1446 { 1447 int mask; 1448 struct arm64_ftr_reg *regp; 1449 u64 val = read_scoped_sysreg(entry, scope); 1450 1451 regp = get_arm64_ftr_reg(entry->sys_reg); 1452 if (!regp) 1453 return false; 1454 1455 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1456 entry->field_pos, 1457 entry->field_width); 1458 if (!mask) 1459 return false; 1460 1461 return feature_matches(val, entry); 1462 } 1463 1464 static bool 1465 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1466 { 1467 u64 val = read_scoped_sysreg(entry, scope); 1468 return feature_matches(val, entry); 1469 } 1470 1471 const struct cpumask *system_32bit_el0_cpumask(void) 1472 { 1473 if (!system_supports_32bit_el0()) 1474 return cpu_none_mask; 1475 1476 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1477 return cpu_32bit_el0_mask; 1478 1479 return cpu_possible_mask; 1480 } 1481 1482 static int __init parse_32bit_el0_param(char *str) 1483 { 1484 allow_mismatched_32bit_el0 = true; 1485 return 0; 1486 } 1487 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1488 1489 static ssize_t aarch32_el0_show(struct device *dev, 1490 struct device_attribute *attr, char *buf) 1491 { 1492 const struct cpumask *mask = system_32bit_el0_cpumask(); 1493 1494 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1495 } 1496 static const DEVICE_ATTR_RO(aarch32_el0); 1497 1498 static int __init aarch32_el0_sysfs_init(void) 1499 { 1500 struct device *dev_root; 1501 int ret = 0; 1502 1503 if (!allow_mismatched_32bit_el0) 1504 return 0; 1505 1506 dev_root = bus_get_dev_root(&cpu_subsys); 1507 if (dev_root) { 1508 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1509 put_device(dev_root); 1510 } 1511 return ret; 1512 } 1513 device_initcall(aarch32_el0_sysfs_init); 1514 1515 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1516 { 1517 if (!has_cpuid_feature(entry, scope)) 1518 return allow_mismatched_32bit_el0; 1519 1520 if (scope == SCOPE_SYSTEM) 1521 pr_info("detected: 32-bit EL0 Support\n"); 1522 1523 return true; 1524 } 1525 1526 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1527 { 1528 bool has_sre; 1529 1530 if (!has_cpuid_feature(entry, scope)) 1531 return false; 1532 1533 has_sre = gic_enable_sre(); 1534 if (!has_sre) 1535 pr_warn_once("%s present but disabled by higher exception level\n", 1536 entry->desc); 1537 1538 return has_sre; 1539 } 1540 1541 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1542 { 1543 u32 midr = read_cpuid_id(); 1544 1545 /* Cavium ThunderX pass 1.x and 2.x */ 1546 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1547 MIDR_CPU_VAR_REV(0, 0), 1548 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1549 } 1550 1551 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1552 { 1553 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1554 1555 return cpuid_feature_extract_signed_field(pfr0, 1556 ID_AA64PFR0_EL1_FP_SHIFT) < 0; 1557 } 1558 1559 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1560 int scope) 1561 { 1562 u64 ctr; 1563 1564 if (scope == SCOPE_SYSTEM) 1565 ctr = arm64_ftr_reg_ctrel0.sys_val; 1566 else 1567 ctr = read_cpuid_effective_cachetype(); 1568 1569 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1570 } 1571 1572 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1573 { 1574 /* 1575 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1576 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1577 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1578 * value. 1579 */ 1580 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1581 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1582 } 1583 1584 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1585 int scope) 1586 { 1587 u64 ctr; 1588 1589 if (scope == SCOPE_SYSTEM) 1590 ctr = arm64_ftr_reg_ctrel0.sys_val; 1591 else 1592 ctr = read_cpuid_cachetype(); 1593 1594 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1595 } 1596 1597 static bool __maybe_unused 1598 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1599 { 1600 /* 1601 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1602 * may share TLB entries with a CPU stuck in the crashed 1603 * kernel. 1604 */ 1605 if (is_kdump_kernel()) 1606 return false; 1607 1608 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1609 return false; 1610 1611 return has_cpuid_feature(entry, scope); 1612 } 1613 1614 /* 1615 * This check is triggered during the early boot before the cpufeature 1616 * is initialised. Checking the status on the local CPU allows the boot 1617 * CPU to detect the need for non-global mappings and thus avoiding a 1618 * pagetable re-write after all the CPUs are booted. This check will be 1619 * anyway run on individual CPUs, allowing us to get the consistent 1620 * state once the SMP CPUs are up and thus make the switch to non-global 1621 * mappings if required. 1622 */ 1623 bool kaslr_requires_kpti(void) 1624 { 1625 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1626 return false; 1627 1628 /* 1629 * E0PD does a similar job to KPTI so can be used instead 1630 * where available. 1631 */ 1632 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1633 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1634 if (cpuid_feature_extract_unsigned_field(mmfr2, 1635 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1636 return false; 1637 } 1638 1639 /* 1640 * Systems affected by Cavium erratum 24756 are incompatible 1641 * with KPTI. 1642 */ 1643 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1644 extern const struct midr_range cavium_erratum_27456_cpus[]; 1645 1646 if (is_midr_in_range_list(read_cpuid_id(), 1647 cavium_erratum_27456_cpus)) 1648 return false; 1649 } 1650 1651 return kaslr_enabled(); 1652 } 1653 1654 static bool __meltdown_safe = true; 1655 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1656 1657 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1658 int scope) 1659 { 1660 /* List of CPUs that are not vulnerable and don't need KPTI */ 1661 static const struct midr_range kpti_safe_list[] = { 1662 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1663 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1664 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1665 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1666 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1667 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1668 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1669 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1670 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1671 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1672 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1673 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1674 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1675 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1676 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1677 { /* sentinel */ } 1678 }; 1679 char const *str = "kpti command line option"; 1680 bool meltdown_safe; 1681 1682 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1683 1684 /* Defer to CPU feature registers */ 1685 if (has_cpuid_feature(entry, scope)) 1686 meltdown_safe = true; 1687 1688 if (!meltdown_safe) 1689 __meltdown_safe = false; 1690 1691 /* 1692 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1693 * ThunderX leads to apparent I-cache corruption of kernel text, which 1694 * ends as well as you might imagine. Don't even try. We cannot rely 1695 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1696 * because cpucap detection order may change. However, since we know 1697 * affected CPUs are always in a homogeneous configuration, it is 1698 * safe to rely on this_cpu_has_cap() here. 1699 */ 1700 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1701 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1702 __kpti_forced = -1; 1703 } 1704 1705 /* Useful for KASLR robustness */ 1706 if (kaslr_requires_kpti()) { 1707 if (!__kpti_forced) { 1708 str = "KASLR"; 1709 __kpti_forced = 1; 1710 } 1711 } 1712 1713 if (cpu_mitigations_off() && !__kpti_forced) { 1714 str = "mitigations=off"; 1715 __kpti_forced = -1; 1716 } 1717 1718 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1719 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1720 return false; 1721 } 1722 1723 /* Forced? */ 1724 if (__kpti_forced) { 1725 pr_info_once("kernel page table isolation forced %s by %s\n", 1726 __kpti_forced > 0 ? "ON" : "OFF", str); 1727 return __kpti_forced > 0; 1728 } 1729 1730 return !meltdown_safe; 1731 } 1732 1733 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1734 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1735 1736 extern 1737 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1738 phys_addr_t size, pgprot_t prot, 1739 phys_addr_t (*pgtable_alloc)(int), int flags); 1740 1741 static phys_addr_t kpti_ng_temp_alloc; 1742 1743 static phys_addr_t kpti_ng_pgd_alloc(int shift) 1744 { 1745 kpti_ng_temp_alloc -= PAGE_SIZE; 1746 return kpti_ng_temp_alloc; 1747 } 1748 1749 static void 1750 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1751 { 1752 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1753 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1754 kpti_remap_fn *remap_fn; 1755 1756 int cpu = smp_processor_id(); 1757 int levels = CONFIG_PGTABLE_LEVELS; 1758 int order = order_base_2(levels); 1759 u64 kpti_ng_temp_pgd_pa = 0; 1760 pgd_t *kpti_ng_temp_pgd; 1761 u64 alloc = 0; 1762 1763 if (__this_cpu_read(this_cpu_vector) == vectors) { 1764 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1765 1766 __this_cpu_write(this_cpu_vector, v); 1767 } 1768 1769 /* 1770 * We don't need to rewrite the page-tables if either we've done 1771 * it already or we have KASLR enabled and therefore have not 1772 * created any global mappings at all. 1773 */ 1774 if (arm64_use_ng_mappings) 1775 return; 1776 1777 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1778 1779 if (!cpu) { 1780 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1781 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1782 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1783 1784 // 1785 // Create a minimal page table hierarchy that permits us to map 1786 // the swapper page tables temporarily as we traverse them. 1787 // 1788 // The physical pages are laid out as follows: 1789 // 1790 // +--------+-/-------+-/------ +-\\--------+ 1791 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1792 // +--------+-\-------+-\------ +-//--------+ 1793 // ^ 1794 // The first page is mapped into this hierarchy at a PMD_SHIFT 1795 // aligned virtual address, so that we can manipulate the PTE 1796 // level entries while the mapping is active. The first entry 1797 // covers the PTE[] page itself, the remaining entries are free 1798 // to be used as a ad-hoc fixmap. 1799 // 1800 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1801 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1802 kpti_ng_pgd_alloc, 0); 1803 } 1804 1805 cpu_install_idmap(); 1806 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1807 cpu_uninstall_idmap(); 1808 1809 if (!cpu) { 1810 free_pages(alloc, order); 1811 arm64_use_ng_mappings = true; 1812 } 1813 } 1814 #else 1815 static void 1816 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1817 { 1818 } 1819 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1820 1821 static int __init parse_kpti(char *str) 1822 { 1823 bool enabled; 1824 int ret = kstrtobool(str, &enabled); 1825 1826 if (ret) 1827 return ret; 1828 1829 __kpti_forced = enabled ? 1 : -1; 1830 return 0; 1831 } 1832 early_param("kpti", parse_kpti); 1833 1834 #ifdef CONFIG_ARM64_HW_AFDBM 1835 static inline void __cpu_enable_hw_dbm(void) 1836 { 1837 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1838 1839 write_sysreg(tcr, tcr_el1); 1840 isb(); 1841 local_flush_tlb_all(); 1842 } 1843 1844 static bool cpu_has_broken_dbm(void) 1845 { 1846 /* List of CPUs which have broken DBM support. */ 1847 static const struct midr_range cpus[] = { 1848 #ifdef CONFIG_ARM64_ERRATUM_1024718 1849 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1850 /* Kryo4xx Silver (rdpe => r1p0) */ 1851 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1852 #endif 1853 #ifdef CONFIG_ARM64_ERRATUM_2051678 1854 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1855 #endif 1856 {}, 1857 }; 1858 1859 return is_midr_in_range_list(read_cpuid_id(), cpus); 1860 } 1861 1862 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1863 { 1864 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1865 !cpu_has_broken_dbm(); 1866 } 1867 1868 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1869 { 1870 if (cpu_can_use_dbm(cap)) 1871 __cpu_enable_hw_dbm(); 1872 } 1873 1874 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1875 int __unused) 1876 { 1877 static bool detected = false; 1878 /* 1879 * DBM is a non-conflicting feature. i.e, the kernel can safely 1880 * run a mix of CPUs with and without the feature. So, we 1881 * unconditionally enable the capability to allow any late CPU 1882 * to use the feature. We only enable the control bits on the 1883 * CPU, if it actually supports. 1884 * 1885 * We have to make sure we print the "feature" detection only 1886 * when at least one CPU actually uses it. So check if this CPU 1887 * can actually use it and print the message exactly once. 1888 * 1889 * This is safe as all CPUs (including secondary CPUs - due to the 1890 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1891 * goes through the "matches" check exactly once. Also if a CPU 1892 * matches the criteria, it is guaranteed that the CPU will turn 1893 * the DBM on, as the capability is unconditionally enabled. 1894 */ 1895 if (!detected && cpu_can_use_dbm(cap)) { 1896 detected = true; 1897 pr_info("detected: Hardware dirty bit management\n"); 1898 } 1899 1900 return true; 1901 } 1902 1903 #endif 1904 1905 #ifdef CONFIG_ARM64_AMU_EXTN 1906 1907 /* 1908 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1909 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1910 * information regarding all the events that it supports. When a CPU bit is 1911 * set in the cpumask, the user of this feature can only rely on the presence 1912 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1913 * counters are enabled or access to these counters is enabled by code 1914 * executed at higher exception levels (firmware). 1915 */ 1916 static struct cpumask amu_cpus __read_mostly; 1917 1918 bool cpu_has_amu_feat(int cpu) 1919 { 1920 return cpumask_test_cpu(cpu, &amu_cpus); 1921 } 1922 1923 int get_cpu_with_amu_feat(void) 1924 { 1925 return cpumask_any(&amu_cpus); 1926 } 1927 1928 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1929 { 1930 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1931 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1932 smp_processor_id()); 1933 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1934 1935 /* 0 reference values signal broken/disabled counters */ 1936 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1937 update_freq_counters_refs(); 1938 } 1939 } 1940 1941 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1942 int __unused) 1943 { 1944 /* 1945 * The AMU extension is a non-conflicting feature: the kernel can 1946 * safely run a mix of CPUs with and without support for the 1947 * activity monitors extension. Therefore, unconditionally enable 1948 * the capability to allow any late CPU to use the feature. 1949 * 1950 * With this feature unconditionally enabled, the cpu_enable 1951 * function will be called for all CPUs that match the criteria, 1952 * including secondary and hotplugged, marking this feature as 1953 * present on that respective CPU. The enable function will also 1954 * print a detection message. 1955 */ 1956 1957 return true; 1958 } 1959 #else 1960 int get_cpu_with_amu_feat(void) 1961 { 1962 return nr_cpu_ids; 1963 } 1964 #endif 1965 1966 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1967 { 1968 return is_kernel_in_hyp_mode(); 1969 } 1970 1971 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1972 { 1973 /* 1974 * Copy register values that aren't redirected by hardware. 1975 * 1976 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1977 * this value to tpidr_el2 before we patch the code. Once we've done 1978 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1979 * do anything here. 1980 */ 1981 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1982 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1983 } 1984 1985 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 1986 int scope) 1987 { 1988 if (kvm_get_mode() != KVM_MODE_NV) 1989 return false; 1990 1991 if (!has_cpuid_feature(cap, scope)) { 1992 pr_warn("unavailable: %s\n", cap->desc); 1993 return false; 1994 } 1995 1996 return true; 1997 } 1998 1999 #ifdef CONFIG_ARM64_PAN 2000 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2001 { 2002 /* 2003 * We modify PSTATE. This won't work from irq context as the PSTATE 2004 * is discarded once we return from the exception. 2005 */ 2006 WARN_ON_ONCE(in_interrupt()); 2007 2008 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2009 set_pstate_pan(1); 2010 } 2011 #endif /* CONFIG_ARM64_PAN */ 2012 2013 #ifdef CONFIG_ARM64_RAS_EXTN 2014 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2015 { 2016 /* Firmware may have left a deferred SError in this register. */ 2017 write_sysreg_s(0, SYS_DISR_EL1); 2018 } 2019 #endif /* CONFIG_ARM64_RAS_EXTN */ 2020 2021 #ifdef CONFIG_ARM64_PTR_AUTH 2022 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2023 { 2024 int boot_val, sec_val; 2025 2026 /* We don't expect to be called with SCOPE_SYSTEM */ 2027 WARN_ON(scope == SCOPE_SYSTEM); 2028 /* 2029 * The ptr-auth feature levels are not intercompatible with lower 2030 * levels. Hence we must match ptr-auth feature level of the secondary 2031 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2032 * from the sanitised register whereas direct register read is done for 2033 * the secondary CPUs. 2034 * The sanitised feature state is guaranteed to match that of the 2035 * boot CPU as a mismatched secondary CPU is parked before it gets 2036 * a chance to update the state, with the capability. 2037 */ 2038 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2039 entry->field_pos, entry->sign); 2040 if (scope & SCOPE_BOOT_CPU) 2041 return boot_val >= entry->min_field_value; 2042 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2043 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2044 entry->field_pos, entry->sign); 2045 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2046 } 2047 2048 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2049 int scope) 2050 { 2051 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2052 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2053 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2054 2055 return apa || apa3 || api; 2056 } 2057 2058 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2059 int __unused) 2060 { 2061 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2062 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2063 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2064 2065 return gpa || gpa3 || gpi; 2066 } 2067 #endif /* CONFIG_ARM64_PTR_AUTH */ 2068 2069 #ifdef CONFIG_ARM64_E0PD 2070 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2071 { 2072 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2073 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2074 } 2075 #endif /* CONFIG_ARM64_E0PD */ 2076 2077 #ifdef CONFIG_ARM64_PSEUDO_NMI 2078 static bool enable_pseudo_nmi; 2079 2080 static int __init early_enable_pseudo_nmi(char *p) 2081 { 2082 return kstrtobool(p, &enable_pseudo_nmi); 2083 } 2084 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2085 2086 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2087 int scope) 2088 { 2089 /* 2090 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2091 * feature, so will be detected earlier. 2092 */ 2093 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2094 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2095 return false; 2096 2097 return enable_pseudo_nmi; 2098 } 2099 2100 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2101 int scope) 2102 { 2103 /* 2104 * If we're not using priority masking then we won't be poking PMR_EL1, 2105 * and there's no need to relax synchronization of writes to it, and 2106 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2107 * that. 2108 * 2109 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2110 * feature, so will be detected earlier. 2111 */ 2112 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2113 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2114 return false; 2115 2116 /* 2117 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2118 * hint for interrupt distribution, a DSB is not necessary when 2119 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2120 * 2121 * Linux itself doesn't use 1:N distribution, so has no need to 2122 * set PMHE. The only reason to have it set is if EL3 requires it 2123 * (and we can't change it). 2124 */ 2125 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2126 } 2127 #endif 2128 2129 #ifdef CONFIG_ARM64_BTI 2130 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2131 { 2132 /* 2133 * Use of X16/X17 for tail-calls and trampolines that jump to 2134 * function entry points using BR is a requirement for 2135 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2136 * So, be strict and forbid other BRs using other registers to 2137 * jump onto a PACIxSP instruction: 2138 */ 2139 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2140 isb(); 2141 } 2142 #endif /* CONFIG_ARM64_BTI */ 2143 2144 #ifdef CONFIG_ARM64_MTE 2145 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2146 { 2147 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2148 2149 mte_cpu_setup(); 2150 2151 /* 2152 * Clear the tags in the zero page. This needs to be done via the 2153 * linear map which has the Tagged attribute. 2154 */ 2155 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2156 mte_clear_page_tags(lm_alias(empty_zero_page)); 2157 set_page_mte_tagged(ZERO_PAGE(0)); 2158 } 2159 2160 kasan_init_hw_tags_cpu(); 2161 } 2162 #endif /* CONFIG_ARM64_MTE */ 2163 2164 static void elf_hwcap_fixup(void) 2165 { 2166 #ifdef CONFIG_ARM64_ERRATUM_1742098 2167 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) 2168 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2169 #endif /* ARM64_ERRATUM_1742098 */ 2170 } 2171 2172 #ifdef CONFIG_KVM 2173 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2174 { 2175 return kvm_get_mode() == KVM_MODE_PROTECTED; 2176 } 2177 #endif /* CONFIG_KVM */ 2178 2179 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2180 { 2181 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2182 } 2183 2184 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2185 { 2186 set_pstate_dit(1); 2187 } 2188 2189 /* Internal helper functions to match cpu capability type */ 2190 static bool 2191 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2192 { 2193 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2194 } 2195 2196 static bool 2197 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2198 { 2199 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2200 } 2201 2202 static bool 2203 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2204 { 2205 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2206 } 2207 2208 static const struct arm64_cpu_capabilities arm64_features[] = { 2209 { 2210 .capability = ARM64_ALWAYS_BOOT, 2211 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2212 .matches = has_always, 2213 }, 2214 { 2215 .capability = ARM64_ALWAYS_SYSTEM, 2216 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2217 .matches = has_always, 2218 }, 2219 { 2220 .desc = "GIC system register CPU interface", 2221 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2222 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2223 .matches = has_useable_gicv3_cpuif, 2224 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2225 }, 2226 { 2227 .desc = "Enhanced Counter Virtualization", 2228 .capability = ARM64_HAS_ECV, 2229 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2230 .matches = has_cpuid_feature, 2231 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2232 }, 2233 { 2234 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2235 .capability = ARM64_HAS_ECV_CNTPOFF, 2236 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2237 .matches = has_cpuid_feature, 2238 .sys_reg = SYS_ID_AA64MMFR0_EL1, 2239 .field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT, 2240 .field_width = 4, 2241 .sign = FTR_UNSIGNED, 2242 .min_field_value = ID_AA64MMFR0_EL1_ECV_CNTPOFF, 2243 }, 2244 #ifdef CONFIG_ARM64_PAN 2245 { 2246 .desc = "Privileged Access Never", 2247 .capability = ARM64_HAS_PAN, 2248 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2249 .matches = has_cpuid_feature, 2250 .cpu_enable = cpu_enable_pan, 2251 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2252 }, 2253 #endif /* CONFIG_ARM64_PAN */ 2254 #ifdef CONFIG_ARM64_EPAN 2255 { 2256 .desc = "Enhanced Privileged Access Never", 2257 .capability = ARM64_HAS_EPAN, 2258 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2259 .matches = has_cpuid_feature, 2260 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2261 }, 2262 #endif /* CONFIG_ARM64_EPAN */ 2263 #ifdef CONFIG_ARM64_LSE_ATOMICS 2264 { 2265 .desc = "LSE atomic instructions", 2266 .capability = ARM64_HAS_LSE_ATOMICS, 2267 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2268 .matches = has_cpuid_feature, 2269 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2270 }, 2271 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2272 { 2273 .desc = "Software prefetching using PRFM", 2274 .capability = ARM64_HAS_NO_HW_PREFETCH, 2275 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2276 .matches = has_no_hw_prefetch, 2277 }, 2278 { 2279 .desc = "Virtualization Host Extensions", 2280 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2281 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2282 .matches = runs_at_el2, 2283 .cpu_enable = cpu_copy_el2regs, 2284 }, 2285 { 2286 .desc = "Nested Virtualization Support", 2287 .capability = ARM64_HAS_NESTED_VIRT, 2288 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2289 .matches = has_nested_virt_support, 2290 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) 2291 }, 2292 { 2293 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2294 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2295 .matches = has_32bit_el0, 2296 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2297 }, 2298 #ifdef CONFIG_KVM 2299 { 2300 .desc = "32-bit EL1 Support", 2301 .capability = ARM64_HAS_32BIT_EL1, 2302 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2303 .matches = has_cpuid_feature, 2304 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2305 }, 2306 { 2307 .desc = "Protected KVM", 2308 .capability = ARM64_KVM_PROTECTED_MODE, 2309 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2310 .matches = is_kvm_protected_mode, 2311 }, 2312 #endif 2313 { 2314 .desc = "Kernel page table isolation (KPTI)", 2315 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2316 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2317 .cpu_enable = kpti_install_ng_mappings, 2318 .matches = unmap_kernel_at_el0, 2319 /* 2320 * The ID feature fields below are used to indicate that 2321 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2322 * more details. 2323 */ 2324 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2325 }, 2326 { 2327 /* FP/SIMD is not implemented */ 2328 .capability = ARM64_HAS_NO_FPSIMD, 2329 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2330 .min_field_value = 0, 2331 .matches = has_no_fpsimd, 2332 }, 2333 #ifdef CONFIG_ARM64_PMEM 2334 { 2335 .desc = "Data cache clean to Point of Persistence", 2336 .capability = ARM64_HAS_DCPOP, 2337 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2338 .matches = has_cpuid_feature, 2339 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2340 }, 2341 { 2342 .desc = "Data cache clean to Point of Deep Persistence", 2343 .capability = ARM64_HAS_DCPODP, 2344 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2345 .matches = has_cpuid_feature, 2346 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2347 }, 2348 #endif 2349 #ifdef CONFIG_ARM64_SVE 2350 { 2351 .desc = "Scalable Vector Extension", 2352 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2353 .capability = ARM64_SVE, 2354 .cpu_enable = sve_kernel_enable, 2355 .matches = has_cpuid_feature, 2356 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2357 }, 2358 #endif /* CONFIG_ARM64_SVE */ 2359 #ifdef CONFIG_ARM64_RAS_EXTN 2360 { 2361 .desc = "RAS Extension Support", 2362 .capability = ARM64_HAS_RAS_EXTN, 2363 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2364 .matches = has_cpuid_feature, 2365 .cpu_enable = cpu_clear_disr, 2366 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2367 }, 2368 #endif /* CONFIG_ARM64_RAS_EXTN */ 2369 #ifdef CONFIG_ARM64_AMU_EXTN 2370 { 2371 /* 2372 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2373 * Therefore, don't provide .desc as we don't want the detection 2374 * message to be shown until at least one CPU is detected to 2375 * support the feature. 2376 */ 2377 .capability = ARM64_HAS_AMU_EXTN, 2378 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2379 .matches = has_amu, 2380 .cpu_enable = cpu_amu_enable, 2381 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2382 }, 2383 #endif /* CONFIG_ARM64_AMU_EXTN */ 2384 { 2385 .desc = "Data cache clean to the PoU not required for I/D coherence", 2386 .capability = ARM64_HAS_CACHE_IDC, 2387 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2388 .matches = has_cache_idc, 2389 .cpu_enable = cpu_emulate_effective_ctr, 2390 }, 2391 { 2392 .desc = "Instruction cache invalidation not required for I/D coherence", 2393 .capability = ARM64_HAS_CACHE_DIC, 2394 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2395 .matches = has_cache_dic, 2396 }, 2397 { 2398 .desc = "Stage-2 Force Write-Back", 2399 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2400 .capability = ARM64_HAS_STAGE2_FWB, 2401 .matches = has_cpuid_feature, 2402 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2403 }, 2404 { 2405 .desc = "ARMv8.4 Translation Table Level", 2406 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2407 .capability = ARM64_HAS_ARMv8_4_TTL, 2408 .matches = has_cpuid_feature, 2409 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2410 }, 2411 { 2412 .desc = "TLB range maintenance instructions", 2413 .capability = ARM64_HAS_TLB_RANGE, 2414 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2415 .matches = has_cpuid_feature, 2416 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2417 }, 2418 #ifdef CONFIG_ARM64_HW_AFDBM 2419 { 2420 /* 2421 * Since we turn this on always, we don't want the user to 2422 * think that the feature is available when it may not be. 2423 * So hide the description. 2424 * 2425 * .desc = "Hardware pagetable Dirty Bit Management", 2426 * 2427 */ 2428 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2429 .capability = ARM64_HW_DBM, 2430 .matches = has_hw_dbm, 2431 .cpu_enable = cpu_enable_hw_dbm, 2432 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2433 }, 2434 #endif 2435 { 2436 .desc = "CRC32 instructions", 2437 .capability = ARM64_HAS_CRC32, 2438 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2439 .matches = has_cpuid_feature, 2440 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2441 }, 2442 { 2443 .desc = "Speculative Store Bypassing Safe (SSBS)", 2444 .capability = ARM64_SSBS, 2445 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2446 .matches = has_cpuid_feature, 2447 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2448 }, 2449 #ifdef CONFIG_ARM64_CNP 2450 { 2451 .desc = "Common not Private translations", 2452 .capability = ARM64_HAS_CNP, 2453 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2454 .matches = has_useable_cnp, 2455 .cpu_enable = cpu_enable_cnp, 2456 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2457 }, 2458 #endif 2459 { 2460 .desc = "Speculation barrier (SB)", 2461 .capability = ARM64_HAS_SB, 2462 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2463 .matches = has_cpuid_feature, 2464 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2465 }, 2466 #ifdef CONFIG_ARM64_PTR_AUTH 2467 { 2468 .desc = "Address authentication (architected QARMA5 algorithm)", 2469 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2470 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2471 .matches = has_address_auth_cpucap, 2472 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2473 }, 2474 { 2475 .desc = "Address authentication (architected QARMA3 algorithm)", 2476 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2477 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2478 .matches = has_address_auth_cpucap, 2479 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2480 }, 2481 { 2482 .desc = "Address authentication (IMP DEF algorithm)", 2483 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2484 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2485 .matches = has_address_auth_cpucap, 2486 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2487 }, 2488 { 2489 .capability = ARM64_HAS_ADDRESS_AUTH, 2490 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2491 .matches = has_address_auth_metacap, 2492 }, 2493 { 2494 .desc = "Generic authentication (architected QARMA5 algorithm)", 2495 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2497 .matches = has_cpuid_feature, 2498 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2499 }, 2500 { 2501 .desc = "Generic authentication (architected QARMA3 algorithm)", 2502 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2503 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2504 .matches = has_cpuid_feature, 2505 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2506 }, 2507 { 2508 .desc = "Generic authentication (IMP DEF algorithm)", 2509 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2510 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2511 .matches = has_cpuid_feature, 2512 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2513 }, 2514 { 2515 .capability = ARM64_HAS_GENERIC_AUTH, 2516 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2517 .matches = has_generic_auth, 2518 }, 2519 #endif /* CONFIG_ARM64_PTR_AUTH */ 2520 #ifdef CONFIG_ARM64_PSEUDO_NMI 2521 { 2522 /* 2523 * Depends on having GICv3 2524 */ 2525 .desc = "IRQ priority masking", 2526 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2527 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2528 .matches = can_use_gic_priorities, 2529 }, 2530 { 2531 /* 2532 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2533 */ 2534 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2535 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2536 .matches = has_gic_prio_relaxed_sync, 2537 }, 2538 #endif 2539 #ifdef CONFIG_ARM64_E0PD 2540 { 2541 .desc = "E0PD", 2542 .capability = ARM64_HAS_E0PD, 2543 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2544 .cpu_enable = cpu_enable_e0pd, 2545 .matches = has_cpuid_feature, 2546 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2547 }, 2548 #endif 2549 { 2550 .desc = "Random Number Generator", 2551 .capability = ARM64_HAS_RNG, 2552 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2553 .matches = has_cpuid_feature, 2554 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2555 }, 2556 #ifdef CONFIG_ARM64_BTI 2557 { 2558 .desc = "Branch Target Identification", 2559 .capability = ARM64_BTI, 2560 #ifdef CONFIG_ARM64_BTI_KERNEL 2561 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2562 #else 2563 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2564 #endif 2565 .matches = has_cpuid_feature, 2566 .cpu_enable = bti_enable, 2567 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2568 }, 2569 #endif 2570 #ifdef CONFIG_ARM64_MTE 2571 { 2572 .desc = "Memory Tagging Extension", 2573 .capability = ARM64_MTE, 2574 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2575 .matches = has_cpuid_feature, 2576 .cpu_enable = cpu_enable_mte, 2577 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2578 }, 2579 { 2580 .desc = "Asymmetric MTE Tag Check Fault", 2581 .capability = ARM64_MTE_ASYMM, 2582 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2583 .matches = has_cpuid_feature, 2584 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2585 }, 2586 #endif /* CONFIG_ARM64_MTE */ 2587 { 2588 .desc = "RCpc load-acquire (LDAPR)", 2589 .capability = ARM64_HAS_LDAPR, 2590 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2591 .matches = has_cpuid_feature, 2592 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2593 }, 2594 #ifdef CONFIG_ARM64_SME 2595 { 2596 .desc = "Scalable Matrix Extension", 2597 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2598 .capability = ARM64_SME, 2599 .matches = has_cpuid_feature, 2600 .cpu_enable = sme_kernel_enable, 2601 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2602 }, 2603 /* FA64 should be sorted after the base SME capability */ 2604 { 2605 .desc = "FA64", 2606 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2607 .capability = ARM64_SME_FA64, 2608 .matches = has_cpuid_feature, 2609 .cpu_enable = fa64_kernel_enable, 2610 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2611 }, 2612 { 2613 .desc = "SME2", 2614 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2615 .capability = ARM64_SME2, 2616 .matches = has_cpuid_feature, 2617 .cpu_enable = sme2_kernel_enable, 2618 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2619 }, 2620 #endif /* CONFIG_ARM64_SME */ 2621 { 2622 .desc = "WFx with timeout", 2623 .capability = ARM64_HAS_WFXT, 2624 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2625 .matches = has_cpuid_feature, 2626 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2627 }, 2628 { 2629 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2630 .capability = ARM64_HAS_TIDCP1, 2631 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2632 .matches = has_cpuid_feature, 2633 .cpu_enable = cpu_trap_el0_impdef, 2634 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2635 }, 2636 { 2637 .desc = "Data independent timing control (DIT)", 2638 .capability = ARM64_HAS_DIT, 2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2640 .matches = has_cpuid_feature, 2641 .cpu_enable = cpu_enable_dit, 2642 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2643 }, 2644 {}, 2645 }; 2646 2647 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2648 .matches = has_user_cpuid_feature, \ 2649 ARM64_CPUID_FIELDS(reg, field, min_value) 2650 2651 #define __HWCAP_CAP(name, cap_type, cap) \ 2652 .desc = name, \ 2653 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2654 .hwcap_type = cap_type, \ 2655 .hwcap = cap, \ 2656 2657 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2658 { \ 2659 __HWCAP_CAP(#cap, cap_type, cap) \ 2660 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2661 } 2662 2663 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2664 { \ 2665 __HWCAP_CAP(#cap, cap_type, cap) \ 2666 .matches = cpucap_multi_entry_cap_matches, \ 2667 .match_list = list, \ 2668 } 2669 2670 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2671 { \ 2672 __HWCAP_CAP(#cap, cap_type, cap) \ 2673 .matches = match, \ 2674 } 2675 2676 #ifdef CONFIG_ARM64_PTR_AUTH 2677 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2678 { 2679 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2680 }, 2681 { 2682 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2683 }, 2684 { 2685 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2686 }, 2687 {}, 2688 }; 2689 2690 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2691 { 2692 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2693 }, 2694 { 2695 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2696 }, 2697 { 2698 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2699 }, 2700 {}, 2701 }; 2702 #endif 2703 2704 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2705 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2706 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2707 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2708 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2709 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2710 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2711 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2712 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2713 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2714 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 2715 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 2716 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2717 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2718 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2719 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2720 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 2721 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 2722 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2723 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2724 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2725 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 2726 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2727 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2728 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2729 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2730 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2731 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2732 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2733 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 2734 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 2735 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2736 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 2737 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2738 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2739 #ifdef CONFIG_ARM64_SVE 2740 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2741 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2742 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2743 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2744 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2745 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2746 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2747 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2748 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2749 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2750 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2751 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2752 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2753 #endif 2754 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2755 #ifdef CONFIG_ARM64_BTI 2756 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2757 #endif 2758 #ifdef CONFIG_ARM64_PTR_AUTH 2759 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2760 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2761 #endif 2762 #ifdef CONFIG_ARM64_MTE 2763 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2764 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2765 #endif /* CONFIG_ARM64_MTE */ 2766 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 2767 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 2768 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2769 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 2770 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2771 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2772 #ifdef CONFIG_ARM64_SME 2773 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2774 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2775 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 2776 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 2777 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2778 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2779 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 2780 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 2781 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 2782 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2783 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2784 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2785 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 2786 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2787 #endif /* CONFIG_ARM64_SME */ 2788 {}, 2789 }; 2790 2791 #ifdef CONFIG_COMPAT 2792 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2793 { 2794 /* 2795 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2796 * in line with that of arm32 as in vfp_init(). We make sure that the 2797 * check is future proof, by making sure value is non-zero. 2798 */ 2799 u32 mvfr1; 2800 2801 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2802 if (scope == SCOPE_SYSTEM) 2803 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2804 else 2805 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2806 2807 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 2808 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 2809 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 2810 } 2811 #endif 2812 2813 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2814 #ifdef CONFIG_COMPAT 2815 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2816 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2817 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2818 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2819 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2820 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 2821 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 2822 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2823 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2824 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2825 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2826 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2827 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 2828 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 2829 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 2830 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 2831 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 2832 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 2833 #endif 2834 {}, 2835 }; 2836 2837 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2838 { 2839 switch (cap->hwcap_type) { 2840 case CAP_HWCAP: 2841 cpu_set_feature(cap->hwcap); 2842 break; 2843 #ifdef CONFIG_COMPAT 2844 case CAP_COMPAT_HWCAP: 2845 compat_elf_hwcap |= (u32)cap->hwcap; 2846 break; 2847 case CAP_COMPAT_HWCAP2: 2848 compat_elf_hwcap2 |= (u32)cap->hwcap; 2849 break; 2850 #endif 2851 default: 2852 WARN_ON(1); 2853 break; 2854 } 2855 } 2856 2857 /* Check if we have a particular HWCAP enabled */ 2858 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2859 { 2860 bool rc; 2861 2862 switch (cap->hwcap_type) { 2863 case CAP_HWCAP: 2864 rc = cpu_have_feature(cap->hwcap); 2865 break; 2866 #ifdef CONFIG_COMPAT 2867 case CAP_COMPAT_HWCAP: 2868 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2869 break; 2870 case CAP_COMPAT_HWCAP2: 2871 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2872 break; 2873 #endif 2874 default: 2875 WARN_ON(1); 2876 rc = false; 2877 } 2878 2879 return rc; 2880 } 2881 2882 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2883 { 2884 /* We support emulation of accesses to CPU ID feature registers */ 2885 cpu_set_named_feature(CPUID); 2886 for (; hwcaps->matches; hwcaps++) 2887 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2888 cap_set_elf_hwcap(hwcaps); 2889 } 2890 2891 static void update_cpu_capabilities(u16 scope_mask) 2892 { 2893 int i; 2894 const struct arm64_cpu_capabilities *caps; 2895 2896 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2897 for (i = 0; i < ARM64_NCAPS; i++) { 2898 caps = cpu_hwcaps_ptrs[i]; 2899 if (!caps || !(caps->type & scope_mask) || 2900 cpus_have_cap(caps->capability) || 2901 !caps->matches(caps, cpucap_default_scope(caps))) 2902 continue; 2903 2904 if (caps->desc) 2905 pr_info("detected: %s\n", caps->desc); 2906 cpus_set_cap(caps->capability); 2907 2908 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2909 set_bit(caps->capability, boot_capabilities); 2910 } 2911 } 2912 2913 /* 2914 * Enable all the available capabilities on this CPU. The capabilities 2915 * with BOOT_CPU scope are handled separately and hence skipped here. 2916 */ 2917 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2918 { 2919 int i; 2920 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2921 2922 for_each_available_cap(i) { 2923 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2924 2925 if (WARN_ON(!cap)) 2926 continue; 2927 2928 if (!(cap->type & non_boot_scope)) 2929 continue; 2930 2931 if (cap->cpu_enable) 2932 cap->cpu_enable(cap); 2933 } 2934 return 0; 2935 } 2936 2937 /* 2938 * Run through the enabled capabilities and enable() it on all active 2939 * CPUs 2940 */ 2941 static void __init enable_cpu_capabilities(u16 scope_mask) 2942 { 2943 int i; 2944 const struct arm64_cpu_capabilities *caps; 2945 bool boot_scope; 2946 2947 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2948 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2949 2950 for (i = 0; i < ARM64_NCAPS; i++) { 2951 unsigned int num; 2952 2953 caps = cpu_hwcaps_ptrs[i]; 2954 if (!caps || !(caps->type & scope_mask)) 2955 continue; 2956 num = caps->capability; 2957 if (!cpus_have_cap(num)) 2958 continue; 2959 2960 if (boot_scope && caps->cpu_enable) 2961 /* 2962 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2963 * before any secondary CPU boots. Thus, each secondary 2964 * will enable the capability as appropriate via 2965 * check_local_cpu_capabilities(). The only exception is 2966 * the boot CPU, for which the capability must be 2967 * enabled here. This approach avoids costly 2968 * stop_machine() calls for this case. 2969 */ 2970 caps->cpu_enable(caps); 2971 } 2972 2973 /* 2974 * For all non-boot scope capabilities, use stop_machine() 2975 * as it schedules the work allowing us to modify PSTATE, 2976 * instead of on_each_cpu() which uses an IPI, giving us a 2977 * PSTATE that disappears when we return. 2978 */ 2979 if (!boot_scope) 2980 stop_machine(cpu_enable_non_boot_scope_capabilities, 2981 NULL, cpu_online_mask); 2982 } 2983 2984 /* 2985 * Run through the list of capabilities to check for conflicts. 2986 * If the system has already detected a capability, take necessary 2987 * action on this CPU. 2988 */ 2989 static void verify_local_cpu_caps(u16 scope_mask) 2990 { 2991 int i; 2992 bool cpu_has_cap, system_has_cap; 2993 const struct arm64_cpu_capabilities *caps; 2994 2995 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2996 2997 for (i = 0; i < ARM64_NCAPS; i++) { 2998 caps = cpu_hwcaps_ptrs[i]; 2999 if (!caps || !(caps->type & scope_mask)) 3000 continue; 3001 3002 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3003 system_has_cap = cpus_have_cap(caps->capability); 3004 3005 if (system_has_cap) { 3006 /* 3007 * Check if the new CPU misses an advertised feature, 3008 * which is not safe to miss. 3009 */ 3010 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3011 break; 3012 /* 3013 * We have to issue cpu_enable() irrespective of 3014 * whether the CPU has it or not, as it is enabeld 3015 * system wide. It is upto the call back to take 3016 * appropriate action on this CPU. 3017 */ 3018 if (caps->cpu_enable) 3019 caps->cpu_enable(caps); 3020 } else { 3021 /* 3022 * Check if the CPU has this capability if it isn't 3023 * safe to have when the system doesn't. 3024 */ 3025 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3026 break; 3027 } 3028 } 3029 3030 if (i < ARM64_NCAPS) { 3031 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3032 smp_processor_id(), caps->capability, 3033 caps->desc, system_has_cap, cpu_has_cap); 3034 3035 if (cpucap_panic_on_conflict(caps)) 3036 cpu_panic_kernel(); 3037 else 3038 cpu_die_early(); 3039 } 3040 } 3041 3042 /* 3043 * Check for CPU features that are used in early boot 3044 * based on the Boot CPU value. 3045 */ 3046 static void check_early_cpu_features(void) 3047 { 3048 verify_cpu_asid_bits(); 3049 3050 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3051 } 3052 3053 static void 3054 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3055 { 3056 3057 for (; caps->matches; caps++) 3058 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3059 pr_crit("CPU%d: missing HWCAP: %s\n", 3060 smp_processor_id(), caps->desc); 3061 cpu_die_early(); 3062 } 3063 } 3064 3065 static void verify_local_elf_hwcaps(void) 3066 { 3067 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3068 3069 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3070 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3071 } 3072 3073 static void verify_sve_features(void) 3074 { 3075 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 3076 u64 zcr = read_zcr_features(); 3077 3078 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 3079 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 3080 3081 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 3082 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3083 smp_processor_id()); 3084 cpu_die_early(); 3085 } 3086 3087 /* Add checks on other ZCR bits here if necessary */ 3088 } 3089 3090 static void verify_sme_features(void) 3091 { 3092 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 3093 u64 smcr = read_smcr_features(); 3094 3095 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK; 3096 unsigned int len = smcr & SMCR_ELx_LEN_MASK; 3097 3098 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) { 3099 pr_crit("CPU%d: SME: vector length support mismatch\n", 3100 smp_processor_id()); 3101 cpu_die_early(); 3102 } 3103 3104 /* Add checks on other SMCR bits here if necessary */ 3105 } 3106 3107 static void verify_hyp_capabilities(void) 3108 { 3109 u64 safe_mmfr1, mmfr0, mmfr1; 3110 int parange, ipa_max; 3111 unsigned int safe_vmid_bits, vmid_bits; 3112 3113 if (!IS_ENABLED(CONFIG_KVM)) 3114 return; 3115 3116 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3117 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3118 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3119 3120 /* Verify VMID bits */ 3121 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3122 vmid_bits = get_vmid_bits(mmfr1); 3123 if (vmid_bits < safe_vmid_bits) { 3124 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3125 cpu_die_early(); 3126 } 3127 3128 /* Verify IPA range */ 3129 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3130 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3131 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3132 if (ipa_max < get_kvm_ipa_limit()) { 3133 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3134 cpu_die_early(); 3135 } 3136 } 3137 3138 /* 3139 * Run through the enabled system capabilities and enable() it on this CPU. 3140 * The capabilities were decided based on the available CPUs at the boot time. 3141 * Any new CPU should match the system wide status of the capability. If the 3142 * new CPU doesn't have a capability which the system now has enabled, we 3143 * cannot do anything to fix it up and could cause unexpected failures. So 3144 * we park the CPU. 3145 */ 3146 static void verify_local_cpu_capabilities(void) 3147 { 3148 /* 3149 * The capabilities with SCOPE_BOOT_CPU are checked from 3150 * check_early_cpu_features(), as they need to be verified 3151 * on all secondary CPUs. 3152 */ 3153 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3154 verify_local_elf_hwcaps(); 3155 3156 if (system_supports_sve()) 3157 verify_sve_features(); 3158 3159 if (system_supports_sme()) 3160 verify_sme_features(); 3161 3162 if (is_hyp_mode_available()) 3163 verify_hyp_capabilities(); 3164 } 3165 3166 void check_local_cpu_capabilities(void) 3167 { 3168 /* 3169 * All secondary CPUs should conform to the early CPU features 3170 * in use by the kernel based on boot CPU. 3171 */ 3172 check_early_cpu_features(); 3173 3174 /* 3175 * If we haven't finalised the system capabilities, this CPU gets 3176 * a chance to update the errata work arounds and local features. 3177 * Otherwise, this CPU should verify that it has all the system 3178 * advertised capabilities. 3179 */ 3180 if (!system_capabilities_finalized()) 3181 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3182 else 3183 verify_local_cpu_capabilities(); 3184 } 3185 3186 static void __init setup_boot_cpu_capabilities(void) 3187 { 3188 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3189 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3190 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3191 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3192 } 3193 3194 bool this_cpu_has_cap(unsigned int n) 3195 { 3196 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3197 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3198 3199 if (cap) 3200 return cap->matches(cap, SCOPE_LOCAL_CPU); 3201 } 3202 3203 return false; 3204 } 3205 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3206 3207 /* 3208 * This helper function is used in a narrow window when, 3209 * - The system wide safe registers are set with all the SMP CPUs and, 3210 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 3211 * In all other cases cpus_have_{const_}cap() should be used. 3212 */ 3213 static bool __maybe_unused __system_matches_cap(unsigned int n) 3214 { 3215 if (n < ARM64_NCAPS) { 3216 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3217 3218 if (cap) 3219 return cap->matches(cap, SCOPE_SYSTEM); 3220 } 3221 return false; 3222 } 3223 3224 void cpu_set_feature(unsigned int num) 3225 { 3226 set_bit(num, elf_hwcap); 3227 } 3228 3229 bool cpu_have_feature(unsigned int num) 3230 { 3231 return test_bit(num, elf_hwcap); 3232 } 3233 EXPORT_SYMBOL_GPL(cpu_have_feature); 3234 3235 unsigned long cpu_get_elf_hwcap(void) 3236 { 3237 /* 3238 * We currently only populate the first 32 bits of AT_HWCAP. Please 3239 * note that for userspace compatibility we guarantee that bits 62 3240 * and 63 will always be returned as 0. 3241 */ 3242 return elf_hwcap[0]; 3243 } 3244 3245 unsigned long cpu_get_elf_hwcap2(void) 3246 { 3247 return elf_hwcap[1]; 3248 } 3249 3250 static void __init setup_system_capabilities(void) 3251 { 3252 /* 3253 * We have finalised the system-wide safe feature 3254 * registers, finalise the capabilities that depend 3255 * on it. Also enable all the available capabilities, 3256 * that are not enabled already. 3257 */ 3258 update_cpu_capabilities(SCOPE_SYSTEM); 3259 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3260 } 3261 3262 void __init setup_cpu_features(void) 3263 { 3264 u32 cwg; 3265 3266 setup_system_capabilities(); 3267 setup_elf_hwcaps(arm64_elf_hwcaps); 3268 3269 if (system_supports_32bit_el0()) { 3270 setup_elf_hwcaps(compat_elf_hwcaps); 3271 elf_hwcap_fixup(); 3272 } 3273 3274 if (system_uses_ttbr0_pan()) 3275 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3276 3277 sve_setup(); 3278 sme_setup(); 3279 minsigstksz_setup(); 3280 3281 /* 3282 * Check for sane CTR_EL0.CWG value. 3283 */ 3284 cwg = cache_type_cwg(); 3285 if (!cwg) 3286 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3287 ARCH_DMA_MINALIGN); 3288 } 3289 3290 static int enable_mismatched_32bit_el0(unsigned int cpu) 3291 { 3292 /* 3293 * The first 32-bit-capable CPU we detected and so can no longer 3294 * be offlined by userspace. -1 indicates we haven't yet onlined 3295 * a 32-bit-capable CPU. 3296 */ 3297 static int lucky_winner = -1; 3298 3299 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3300 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3301 3302 if (cpu_32bit) { 3303 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3304 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3305 } 3306 3307 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3308 return 0; 3309 3310 if (lucky_winner >= 0) 3311 return 0; 3312 3313 /* 3314 * We've detected a mismatch. We need to keep one of our CPUs with 3315 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3316 * every CPU in the system for a 32-bit task. 3317 */ 3318 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3319 cpu_active_mask); 3320 get_cpu_device(lucky_winner)->offline_disabled = true; 3321 setup_elf_hwcaps(compat_elf_hwcaps); 3322 elf_hwcap_fixup(); 3323 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3324 cpu, lucky_winner); 3325 return 0; 3326 } 3327 3328 static int __init init_32bit_el0_mask(void) 3329 { 3330 if (!allow_mismatched_32bit_el0) 3331 return 0; 3332 3333 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3334 return -ENOMEM; 3335 3336 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3337 "arm64/mismatched_32bit_el0:online", 3338 enable_mismatched_32bit_el0, NULL); 3339 } 3340 subsys_initcall_sync(init_32bit_el0_mask); 3341 3342 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3343 { 3344 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); 3345 } 3346 3347 /* 3348 * We emulate only the following system register space. 3349 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3350 * See Table C5-6 System instruction encodings for System register accesses, 3351 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3352 */ 3353 static inline bool __attribute_const__ is_emulated(u32 id) 3354 { 3355 return (sys_reg_Op0(id) == 0x3 && 3356 sys_reg_CRn(id) == 0x0 && 3357 sys_reg_Op1(id) == 0x0 && 3358 (sys_reg_CRm(id) == 0 || 3359 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3360 } 3361 3362 /* 3363 * With CRm == 0, reg should be one of : 3364 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3365 */ 3366 static inline int emulate_id_reg(u32 id, u64 *valp) 3367 { 3368 switch (id) { 3369 case SYS_MIDR_EL1: 3370 *valp = read_cpuid_id(); 3371 break; 3372 case SYS_MPIDR_EL1: 3373 *valp = SYS_MPIDR_SAFE_VAL; 3374 break; 3375 case SYS_REVIDR_EL1: 3376 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3377 *valp = 0; 3378 break; 3379 default: 3380 return -EINVAL; 3381 } 3382 3383 return 0; 3384 } 3385 3386 static int emulate_sys_reg(u32 id, u64 *valp) 3387 { 3388 struct arm64_ftr_reg *regp; 3389 3390 if (!is_emulated(id)) 3391 return -EINVAL; 3392 3393 if (sys_reg_CRm(id) == 0) 3394 return emulate_id_reg(id, valp); 3395 3396 regp = get_arm64_ftr_reg_nowarn(id); 3397 if (regp) 3398 *valp = arm64_ftr_reg_user_value(regp); 3399 else 3400 /* 3401 * The untracked registers are either IMPLEMENTATION DEFINED 3402 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3403 */ 3404 *valp = 0; 3405 return 0; 3406 } 3407 3408 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3409 { 3410 int rc; 3411 u64 val; 3412 3413 rc = emulate_sys_reg(sys_reg, &val); 3414 if (!rc) { 3415 pt_regs_write_reg(regs, rt, val); 3416 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3417 } 3418 return rc; 3419 } 3420 3421 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3422 { 3423 u32 sys_reg, rt; 3424 3425 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3426 return false; 3427 3428 /* 3429 * sys_reg values are defined as used in mrs/msr instruction. 3430 * shift the imm value to get the encoding. 3431 */ 3432 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3433 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3434 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3435 } 3436 3437 enum mitigation_state arm64_get_meltdown_state(void) 3438 { 3439 if (__meltdown_safe) 3440 return SPECTRE_UNAFFECTED; 3441 3442 if (arm64_kernel_unmapped_at_el0()) 3443 return SPECTRE_MITIGATED; 3444 3445 return SPECTRE_VULNERABLE; 3446 } 3447 3448 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3449 char *buf) 3450 { 3451 switch (arm64_get_meltdown_state()) { 3452 case SPECTRE_UNAFFECTED: 3453 return sprintf(buf, "Not affected\n"); 3454 3455 case SPECTRE_MITIGATED: 3456 return sprintf(buf, "Mitigation: PTI\n"); 3457 3458 default: 3459 return sprintf(buf, "Vulnerable\n"); 3460 } 3461 } 3462