1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <asm/cpu.h> 77 #include <asm/cpufeature.h> 78 #include <asm/cpu_ops.h> 79 #include <asm/fpsimd.h> 80 #include <asm/insn.h> 81 #include <asm/kvm_host.h> 82 #include <asm/mmu_context.h> 83 #include <asm/mte.h> 84 #include <asm/processor.h> 85 #include <asm/smp.h> 86 #include <asm/sysreg.h> 87 #include <asm/traps.h> 88 #include <asm/virt.h> 89 90 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 91 static unsigned long elf_hwcap __read_mostly; 92 93 #ifdef CONFIG_COMPAT 94 #define COMPAT_ELF_HWCAP_DEFAULT \ 95 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 96 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 97 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 98 COMPAT_HWCAP_LPAE) 99 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 100 unsigned int compat_elf_hwcap2 __read_mostly; 101 #endif 102 103 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 104 EXPORT_SYMBOL(cpu_hwcaps); 105 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 106 107 /* Need also bit for ARM64_CB_PATCH */ 108 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 109 110 bool arm64_use_ng_mappings = false; 111 EXPORT_SYMBOL(arm64_use_ng_mappings); 112 113 /* 114 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 115 * support it? 116 */ 117 static bool __read_mostly allow_mismatched_32bit_el0; 118 119 /* 120 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 121 * seen at least one CPU capable of 32-bit EL0. 122 */ 123 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 124 125 /* 126 * Mask of CPUs supporting 32-bit EL0. 127 * Only valid if arm64_mismatched_32bit_el0 is enabled. 128 */ 129 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 130 131 /* 132 * Flag to indicate if we have computed the system wide 133 * capabilities based on the boot time active CPUs. This 134 * will be used to determine if a new booting CPU should 135 * go through the verification process to make sure that it 136 * supports the system capabilities, without using a hotplug 137 * notifier. This is also used to decide if we could use 138 * the fast path for checking constant CPU caps. 139 */ 140 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 141 EXPORT_SYMBOL(arm64_const_caps_ready); 142 static inline void finalize_system_capabilities(void) 143 { 144 static_branch_enable(&arm64_const_caps_ready); 145 } 146 147 void dump_cpu_features(void) 148 { 149 /* file-wide pr_fmt adds "CPU features: " prefix */ 150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 151 } 152 153 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 154 EXPORT_SYMBOL(cpu_hwcap_keys); 155 156 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 157 { \ 158 .sign = SIGNED, \ 159 .visible = VISIBLE, \ 160 .strict = STRICT, \ 161 .type = TYPE, \ 162 .shift = SHIFT, \ 163 .width = WIDTH, \ 164 .safe_val = SAFE_VAL, \ 165 } 166 167 /* Define a feature with unsigned values */ 168 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 169 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 170 171 /* Define a feature with a signed value */ 172 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 173 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 174 175 #define ARM64_FTR_END \ 176 { \ 177 .width = 0, \ 178 } 179 180 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 181 182 static bool __system_matches_cap(unsigned int n); 183 184 /* 185 * NOTE: Any changes to the visibility of features should be kept in 186 * sync with the documentation of the CPU feature register ABI. 187 */ 188 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 203 ARM64_FTR_END, 204 }; 205 206 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 216 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 221 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 223 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 225 ARM64_FTR_END, 226 }; 227 228 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 236 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 239 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 240 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 245 ARM64_FTR_END, 246 }; 247 248 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 256 ARM64_FTR_END, 257 }; 258 259 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 277 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 278 ARM64_FTR_END, 279 }; 280 281 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 285 /* 286 * Page size not being supported at Stage-2 is not fatal. You 287 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 288 * your favourite nesting hypervisor. 289 * 290 * There is a small corner case where the hypervisor explicitly 291 * advertises a given granule size at Stage-2 (value 2) on some 292 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 293 * vCPUs. Although this is not forbidden by the architecture, it 294 * indicates that the hypervisor is being silly (or buggy). 295 * 296 * We make no effort to cope with this and pretend that if these 297 * fields are inconsistent across vCPUs, then it isn't worth 298 * trying to bring KVM up. 299 */ 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 303 /* 304 * We already refuse to boot CPUs that don't support our configured 305 * page size, so we can only detect mismatches for a page size other 306 * than the one we're currently using. Unfortunately, SoCs like this 307 * exist in the wild so, even though we don't like it, we'll have to go 308 * along with it and treat them as non-strict. 309 */ 310 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 311 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 313 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 315 /* Linux shouldn't care about secure memory */ 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 319 /* 320 * Differing PARange is fine as long as all peripherals and memory are mapped 321 * within the minimum PARange of all CPUs 322 */ 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 324 ARM64_FTR_END, 325 }; 326 327 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 338 ARM64_FTR_END, 339 }; 340 341 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 357 ARM64_FTR_END, 358 }; 359 360 static const struct arm64_ftr_bits ftr_ctr[] = { 361 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 362 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 363 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 364 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 367 /* 368 * Linux can handle differing I-cache policies. Userspace JITs will 369 * make use of *minLine. 370 * If we have differing I-cache policies, report it as the weakest - VIPT. 371 */ 372 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 373 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 374 ARM64_FTR_END, 375 }; 376 377 static struct arm64_ftr_override __ro_after_init no_override = { }; 378 379 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 380 .name = "SYS_CTR_EL0", 381 .ftr_bits = ftr_ctr, 382 .override = &no_override, 383 }; 384 385 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 386 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 391 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 394 ARM64_FTR_END, 395 }; 396 397 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 398 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 403 /* 404 * We can instantiate multiple PMU instances with different levels 405 * of support. 406 */ 407 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 409 ARM64_FTR_END, 410 }; 411 412 static const struct arm64_ftr_bits ftr_mvfr2[] = { 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_dczid[] = { 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 421 ARM64_FTR_END, 422 }; 423 424 static const struct arm64_ftr_bits ftr_gmid[] = { 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), 426 ARM64_FTR_END, 427 }; 428 429 static const struct arm64_ftr_bits ftr_id_isar0[] = { 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 437 ARM64_FTR_END, 438 }; 439 440 static const struct arm64_ftr_bits ftr_id_isar5[] = { 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 447 ARM64_FTR_END, 448 }; 449 450 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 458 459 /* 460 * SpecSEI = 1 indicates that the PE might generate an SError on an 461 * external abort on speculative read. It is safe to assume that an 462 * SError might be generated than it will not be. Hence it has been 463 * classified as FTR_HIGHER_SAFE. 464 */ 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 466 ARM64_FTR_END, 467 }; 468 469 static const struct arm64_ftr_bits ftr_id_isar4[] = { 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 483 ARM64_FTR_END, 484 }; 485 486 static const struct arm64_ftr_bits ftr_id_isar6[] = { 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 494 ARM64_FTR_END, 495 }; 496 497 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 504 ARM64_FTR_END, 505 }; 506 507 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 516 ARM64_FTR_END, 517 }; 518 519 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 522 ARM64_FTR_END, 523 }; 524 525 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 526 /* [31:28] TraceFilt */ 527 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 534 ARM64_FTR_END, 535 }; 536 537 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 538 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 539 ARM64_FTR_END, 540 }; 541 542 static const struct arm64_ftr_bits ftr_zcr[] = { 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 544 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 545 ARM64_FTR_END, 546 }; 547 548 /* 549 * Common ftr bits for a 32bit register with all hidden, strict 550 * attributes, with 4bit feature fields and a default safe value of 551 * 0. Covers the following 32bit registers: 552 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 553 */ 554 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 563 ARM64_FTR_END, 564 }; 565 566 /* Table for a single 32bit feature value */ 567 static const struct arm64_ftr_bits ftr_single32[] = { 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 569 ARM64_FTR_END, 570 }; 571 572 static const struct arm64_ftr_bits ftr_raz[] = { 573 ARM64_FTR_END, 574 }; 575 576 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \ 577 .sys_id = id, \ 578 .reg = &(struct arm64_ftr_reg){ \ 579 .name = #id, \ 580 .override = (ovr), \ 581 .ftr_bits = &((table)[0]), \ 582 }} 583 584 #define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override) 585 586 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 587 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 588 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 589 590 static const struct __ftr_reg_entry { 591 u32 sys_id; 592 struct arm64_ftr_reg *reg; 593 } arm64_ftr_regs[] = { 594 595 /* Op1 = 0, CRn = 0, CRm = 1 */ 596 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 597 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 598 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 599 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 600 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 601 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 602 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 603 604 /* Op1 = 0, CRn = 0, CRm = 2 */ 605 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 606 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 607 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 608 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 609 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 610 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 611 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 612 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 613 614 /* Op1 = 0, CRn = 0, CRm = 3 */ 615 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 616 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 617 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 618 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 619 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 620 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 621 622 /* Op1 = 0, CRn = 0, CRm = 4 */ 623 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 624 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 625 &id_aa64pfr1_override), 626 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 627 628 /* Op1 = 0, CRn = 0, CRm = 5 */ 629 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 630 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 631 632 /* Op1 = 0, CRn = 0, CRm = 6 */ 633 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 634 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 635 &id_aa64isar1_override), 636 637 /* Op1 = 0, CRn = 0, CRm = 7 */ 638 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 639 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 640 &id_aa64mmfr1_override), 641 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 642 643 /* Op1 = 0, CRn = 1, CRm = 2 */ 644 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 645 646 /* Op1 = 1, CRn = 0, CRm = 0 */ 647 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 648 649 /* Op1 = 3, CRn = 0, CRm = 0 */ 650 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 651 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 652 653 /* Op1 = 3, CRn = 14, CRm = 0 */ 654 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 655 }; 656 657 static int search_cmp_ftr_reg(const void *id, const void *regp) 658 { 659 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 660 } 661 662 /* 663 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 664 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 665 * ascending order of sys_id, we use binary search to find a matching 666 * entry. 667 * 668 * returns - Upon success, matching ftr_reg entry for id. 669 * - NULL on failure. It is upto the caller to decide 670 * the impact of a failure. 671 */ 672 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 673 { 674 const struct __ftr_reg_entry *ret; 675 676 ret = bsearch((const void *)(unsigned long)sys_id, 677 arm64_ftr_regs, 678 ARRAY_SIZE(arm64_ftr_regs), 679 sizeof(arm64_ftr_regs[0]), 680 search_cmp_ftr_reg); 681 if (ret) 682 return ret->reg; 683 return NULL; 684 } 685 686 /* 687 * get_arm64_ftr_reg - Looks up a feature register entry using 688 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 689 * 690 * returns - Upon success, matching ftr_reg entry for id. 691 * - NULL on failure but with an WARN_ON(). 692 */ 693 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 694 { 695 struct arm64_ftr_reg *reg; 696 697 reg = get_arm64_ftr_reg_nowarn(sys_id); 698 699 /* 700 * Requesting a non-existent register search is an error. Warn 701 * and let the caller handle it. 702 */ 703 WARN_ON(!reg); 704 return reg; 705 } 706 707 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 708 s64 ftr_val) 709 { 710 u64 mask = arm64_ftr_mask(ftrp); 711 712 reg &= ~mask; 713 reg |= (ftr_val << ftrp->shift) & mask; 714 return reg; 715 } 716 717 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 718 s64 cur) 719 { 720 s64 ret = 0; 721 722 switch (ftrp->type) { 723 case FTR_EXACT: 724 ret = ftrp->safe_val; 725 break; 726 case FTR_LOWER_SAFE: 727 ret = min(new, cur); 728 break; 729 case FTR_HIGHER_OR_ZERO_SAFE: 730 if (!cur || !new) 731 break; 732 fallthrough; 733 case FTR_HIGHER_SAFE: 734 ret = max(new, cur); 735 break; 736 default: 737 BUG(); 738 } 739 740 return ret; 741 } 742 743 static void __init sort_ftr_regs(void) 744 { 745 unsigned int i; 746 747 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 748 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 749 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 750 unsigned int j = 0; 751 752 /* 753 * Features here must be sorted in descending order with respect 754 * to their shift values and should not overlap with each other. 755 */ 756 for (; ftr_bits->width != 0; ftr_bits++, j++) { 757 unsigned int width = ftr_reg->ftr_bits[j].width; 758 unsigned int shift = ftr_reg->ftr_bits[j].shift; 759 unsigned int prev_shift; 760 761 WARN((shift + width) > 64, 762 "%s has invalid feature at shift %d\n", 763 ftr_reg->name, shift); 764 765 /* 766 * Skip the first feature. There is nothing to 767 * compare against for now. 768 */ 769 if (j == 0) 770 continue; 771 772 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 773 WARN((shift + width) > prev_shift, 774 "%s has feature overlap at shift %d\n", 775 ftr_reg->name, shift); 776 } 777 778 /* 779 * Skip the first register. There is nothing to 780 * compare against for now. 781 */ 782 if (i == 0) 783 continue; 784 /* 785 * Registers here must be sorted in ascending order with respect 786 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 787 * to work correctly. 788 */ 789 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 790 } 791 } 792 793 /* 794 * Initialise the CPU feature register from Boot CPU values. 795 * Also initiliases the strict_mask for the register. 796 * Any bits that are not covered by an arm64_ftr_bits entry are considered 797 * RES0 for the system-wide value, and must strictly match. 798 */ 799 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 800 { 801 u64 val = 0; 802 u64 strict_mask = ~0x0ULL; 803 u64 user_mask = 0; 804 u64 valid_mask = 0; 805 806 const struct arm64_ftr_bits *ftrp; 807 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 808 809 if (!reg) 810 return; 811 812 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 813 u64 ftr_mask = arm64_ftr_mask(ftrp); 814 s64 ftr_new = arm64_ftr_value(ftrp, new); 815 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 816 817 if ((ftr_mask & reg->override->mask) == ftr_mask) { 818 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 819 char *str = NULL; 820 821 if (ftr_ovr != tmp) { 822 /* Unsafe, remove the override */ 823 reg->override->mask &= ~ftr_mask; 824 reg->override->val &= ~ftr_mask; 825 tmp = ftr_ovr; 826 str = "ignoring override"; 827 } else if (ftr_new != tmp) { 828 /* Override was valid */ 829 ftr_new = tmp; 830 str = "forced"; 831 } else if (ftr_ovr == tmp) { 832 /* Override was the safe value */ 833 str = "already set"; 834 } 835 836 if (str) 837 pr_warn("%s[%d:%d]: %s to %llx\n", 838 reg->name, 839 ftrp->shift + ftrp->width - 1, 840 ftrp->shift, str, tmp); 841 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 842 reg->override->val &= ~ftr_mask; 843 pr_warn("%s[%d:%d]: impossible override, ignored\n", 844 reg->name, 845 ftrp->shift + ftrp->width - 1, 846 ftrp->shift); 847 } 848 849 val = arm64_ftr_set_value(ftrp, val, ftr_new); 850 851 valid_mask |= ftr_mask; 852 if (!ftrp->strict) 853 strict_mask &= ~ftr_mask; 854 if (ftrp->visible) 855 user_mask |= ftr_mask; 856 else 857 reg->user_val = arm64_ftr_set_value(ftrp, 858 reg->user_val, 859 ftrp->safe_val); 860 } 861 862 val &= valid_mask; 863 864 reg->sys_val = val; 865 reg->strict_mask = strict_mask; 866 reg->user_mask = user_mask; 867 } 868 869 extern const struct arm64_cpu_capabilities arm64_errata[]; 870 static const struct arm64_cpu_capabilities arm64_features[]; 871 872 static void __init 873 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 874 { 875 for (; caps->matches; caps++) { 876 if (WARN(caps->capability >= ARM64_NCAPS, 877 "Invalid capability %d\n", caps->capability)) 878 continue; 879 if (WARN(cpu_hwcaps_ptrs[caps->capability], 880 "Duplicate entry for capability %d\n", 881 caps->capability)) 882 continue; 883 cpu_hwcaps_ptrs[caps->capability] = caps; 884 } 885 } 886 887 static void __init init_cpu_hwcaps_indirect_list(void) 888 { 889 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 890 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 891 } 892 893 static void __init setup_boot_cpu_capabilities(void); 894 895 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 896 { 897 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 898 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 899 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 900 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 901 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 902 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 903 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 904 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 905 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 906 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 907 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 908 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 909 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 910 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 911 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 912 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 913 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 914 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 915 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 916 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 917 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 918 } 919 920 void __init init_cpu_features(struct cpuinfo_arm64 *info) 921 { 922 /* Before we start using the tables, make sure it is sorted */ 923 sort_ftr_regs(); 924 925 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 926 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 927 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 928 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 929 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 930 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 931 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 932 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 933 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 934 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 935 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 936 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 937 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 938 939 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 940 init_32bit_cpu_features(&info->aarch32); 941 942 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 943 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 944 sve_init_vq_map(); 945 } 946 947 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 948 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 949 950 /* 951 * Initialize the indirect array of CPU hwcaps capabilities pointers 952 * before we handle the boot CPU below. 953 */ 954 init_cpu_hwcaps_indirect_list(); 955 956 /* 957 * Detect and enable early CPU capabilities based on the boot CPU, 958 * after we have initialised the CPU feature infrastructure. 959 */ 960 setup_boot_cpu_capabilities(); 961 } 962 963 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 964 { 965 const struct arm64_ftr_bits *ftrp; 966 967 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 968 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 969 s64 ftr_new = arm64_ftr_value(ftrp, new); 970 971 if (ftr_cur == ftr_new) 972 continue; 973 /* Find a safe value */ 974 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 975 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 976 } 977 978 } 979 980 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 981 { 982 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 983 984 if (!regp) 985 return 0; 986 987 update_cpu_ftr_reg(regp, val); 988 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 989 return 0; 990 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 991 regp->name, boot, cpu, val); 992 return 1; 993 } 994 995 static void relax_cpu_ftr_reg(u32 sys_id, int field) 996 { 997 const struct arm64_ftr_bits *ftrp; 998 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 999 1000 if (!regp) 1001 return; 1002 1003 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1004 if (ftrp->shift == field) { 1005 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1006 break; 1007 } 1008 } 1009 1010 /* Bogus field? */ 1011 WARN_ON(!ftrp->width); 1012 } 1013 1014 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1015 struct cpuinfo_arm64 *boot) 1016 { 1017 static bool boot_cpu_32bit_regs_overridden = false; 1018 1019 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1020 return; 1021 1022 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1023 return; 1024 1025 boot->aarch32 = info->aarch32; 1026 init_32bit_cpu_features(&boot->aarch32); 1027 boot_cpu_32bit_regs_overridden = true; 1028 } 1029 1030 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1031 struct cpuinfo_32bit *boot) 1032 { 1033 int taint = 0; 1034 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1035 1036 /* 1037 * If we don't have AArch32 at EL1, then relax the strictness of 1038 * EL1-dependent register fields to avoid spurious sanity check fails. 1039 */ 1040 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1041 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1042 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1043 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1044 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1045 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1046 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1047 } 1048 1049 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1050 info->reg_id_dfr0, boot->reg_id_dfr0); 1051 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1052 info->reg_id_dfr1, boot->reg_id_dfr1); 1053 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1054 info->reg_id_isar0, boot->reg_id_isar0); 1055 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1056 info->reg_id_isar1, boot->reg_id_isar1); 1057 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1058 info->reg_id_isar2, boot->reg_id_isar2); 1059 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1060 info->reg_id_isar3, boot->reg_id_isar3); 1061 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1062 info->reg_id_isar4, boot->reg_id_isar4); 1063 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1064 info->reg_id_isar5, boot->reg_id_isar5); 1065 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1066 info->reg_id_isar6, boot->reg_id_isar6); 1067 1068 /* 1069 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1070 * ACTLR formats could differ across CPUs and therefore would have to 1071 * be trapped for virtualization anyway. 1072 */ 1073 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1074 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1075 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1076 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1077 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1078 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1079 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1080 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1081 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1082 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1083 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1084 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1085 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1086 info->reg_id_pfr0, boot->reg_id_pfr0); 1087 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1088 info->reg_id_pfr1, boot->reg_id_pfr1); 1089 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1090 info->reg_id_pfr2, boot->reg_id_pfr2); 1091 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1092 info->reg_mvfr0, boot->reg_mvfr0); 1093 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1094 info->reg_mvfr1, boot->reg_mvfr1); 1095 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1096 info->reg_mvfr2, boot->reg_mvfr2); 1097 1098 return taint; 1099 } 1100 1101 /* 1102 * Update system wide CPU feature registers with the values from a 1103 * non-boot CPU. Also performs SANITY checks to make sure that there 1104 * aren't any insane variations from that of the boot CPU. 1105 */ 1106 void update_cpu_features(int cpu, 1107 struct cpuinfo_arm64 *info, 1108 struct cpuinfo_arm64 *boot) 1109 { 1110 int taint = 0; 1111 1112 /* 1113 * The kernel can handle differing I-cache policies, but otherwise 1114 * caches should look identical. Userspace JITs will make use of 1115 * *minLine. 1116 */ 1117 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1118 info->reg_ctr, boot->reg_ctr); 1119 1120 /* 1121 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1122 * could result in too much or too little memory being zeroed if a 1123 * process is preempted and migrated between CPUs. 1124 */ 1125 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1126 info->reg_dczid, boot->reg_dczid); 1127 1128 /* If different, timekeeping will be broken (especially with KVM) */ 1129 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1130 info->reg_cntfrq, boot->reg_cntfrq); 1131 1132 /* 1133 * The kernel uses self-hosted debug features and expects CPUs to 1134 * support identical debug features. We presently need CTX_CMPs, WRPs, 1135 * and BRPs to be identical. 1136 * ID_AA64DFR1 is currently RES0. 1137 */ 1138 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1139 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1140 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1141 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1142 /* 1143 * Even in big.LITTLE, processors should be identical instruction-set 1144 * wise. 1145 */ 1146 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1147 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1148 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1149 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1150 1151 /* 1152 * Differing PARange support is fine as long as all peripherals and 1153 * memory are mapped within the minimum PARange of all CPUs. 1154 * Linux should not care about secure memory. 1155 */ 1156 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1157 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1158 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1159 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1160 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1161 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1162 1163 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1164 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1165 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1166 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1167 1168 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1169 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1170 1171 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1172 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1173 info->reg_zcr, boot->reg_zcr); 1174 1175 /* Probe vector lengths, unless we already gave up on SVE */ 1176 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1177 !system_capabilities_finalized()) 1178 sve_update_vq_map(); 1179 } 1180 1181 /* 1182 * The kernel uses the LDGM/STGM instructions and the number of tags 1183 * they read/write depends on the GMID_EL1.BS field. Check that the 1184 * value is the same on all CPUs. 1185 */ 1186 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1187 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1188 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1189 info->reg_gmid, boot->reg_gmid); 1190 } 1191 1192 /* 1193 * If we don't have AArch32 at all then skip the checks entirely 1194 * as the register values may be UNKNOWN and we're not going to be 1195 * using them for anything. 1196 * 1197 * This relies on a sanitised view of the AArch64 ID registers 1198 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1199 */ 1200 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1201 lazy_init_32bit_cpu_features(info, boot); 1202 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1203 &boot->aarch32); 1204 } 1205 1206 /* 1207 * Mismatched CPU features are a recipe for disaster. Don't even 1208 * pretend to support them. 1209 */ 1210 if (taint) { 1211 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1212 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1213 } 1214 } 1215 1216 u64 read_sanitised_ftr_reg(u32 id) 1217 { 1218 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1219 1220 if (!regp) 1221 return 0; 1222 return regp->sys_val; 1223 } 1224 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1225 1226 #define read_sysreg_case(r) \ 1227 case r: val = read_sysreg_s(r); break; 1228 1229 /* 1230 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1231 * Read the system register on the current CPU 1232 */ 1233 u64 __read_sysreg_by_encoding(u32 sys_id) 1234 { 1235 struct arm64_ftr_reg *regp; 1236 u64 val; 1237 1238 switch (sys_id) { 1239 read_sysreg_case(SYS_ID_PFR0_EL1); 1240 read_sysreg_case(SYS_ID_PFR1_EL1); 1241 read_sysreg_case(SYS_ID_PFR2_EL1); 1242 read_sysreg_case(SYS_ID_DFR0_EL1); 1243 read_sysreg_case(SYS_ID_DFR1_EL1); 1244 read_sysreg_case(SYS_ID_MMFR0_EL1); 1245 read_sysreg_case(SYS_ID_MMFR1_EL1); 1246 read_sysreg_case(SYS_ID_MMFR2_EL1); 1247 read_sysreg_case(SYS_ID_MMFR3_EL1); 1248 read_sysreg_case(SYS_ID_MMFR4_EL1); 1249 read_sysreg_case(SYS_ID_MMFR5_EL1); 1250 read_sysreg_case(SYS_ID_ISAR0_EL1); 1251 read_sysreg_case(SYS_ID_ISAR1_EL1); 1252 read_sysreg_case(SYS_ID_ISAR2_EL1); 1253 read_sysreg_case(SYS_ID_ISAR3_EL1); 1254 read_sysreg_case(SYS_ID_ISAR4_EL1); 1255 read_sysreg_case(SYS_ID_ISAR5_EL1); 1256 read_sysreg_case(SYS_ID_ISAR6_EL1); 1257 read_sysreg_case(SYS_MVFR0_EL1); 1258 read_sysreg_case(SYS_MVFR1_EL1); 1259 read_sysreg_case(SYS_MVFR2_EL1); 1260 1261 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1262 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1263 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1264 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1265 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1266 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1267 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1268 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1269 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1270 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1271 1272 read_sysreg_case(SYS_CNTFRQ_EL0); 1273 read_sysreg_case(SYS_CTR_EL0); 1274 read_sysreg_case(SYS_DCZID_EL0); 1275 1276 default: 1277 BUG(); 1278 return 0; 1279 } 1280 1281 regp = get_arm64_ftr_reg(sys_id); 1282 if (regp) { 1283 val &= ~regp->override->mask; 1284 val |= (regp->override->val & regp->override->mask); 1285 } 1286 1287 return val; 1288 } 1289 1290 #include <linux/irqchip/arm-gic-v3.h> 1291 1292 static bool 1293 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1294 { 1295 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1296 1297 return val >= entry->min_field_value; 1298 } 1299 1300 static bool 1301 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1302 { 1303 u64 val; 1304 1305 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1306 if (scope == SCOPE_SYSTEM) 1307 val = read_sanitised_ftr_reg(entry->sys_reg); 1308 else 1309 val = __read_sysreg_by_encoding(entry->sys_reg); 1310 1311 return feature_matches(val, entry); 1312 } 1313 1314 const struct cpumask *system_32bit_el0_cpumask(void) 1315 { 1316 if (!system_supports_32bit_el0()) 1317 return cpu_none_mask; 1318 1319 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1320 return cpu_32bit_el0_mask; 1321 1322 return cpu_possible_mask; 1323 } 1324 1325 static int __init parse_32bit_el0_param(char *str) 1326 { 1327 allow_mismatched_32bit_el0 = true; 1328 return 0; 1329 } 1330 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1331 1332 static ssize_t aarch32_el0_show(struct device *dev, 1333 struct device_attribute *attr, char *buf) 1334 { 1335 const struct cpumask *mask = system_32bit_el0_cpumask(); 1336 1337 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1338 } 1339 static const DEVICE_ATTR_RO(aarch32_el0); 1340 1341 static int __init aarch32_el0_sysfs_init(void) 1342 { 1343 if (!allow_mismatched_32bit_el0) 1344 return 0; 1345 1346 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1347 } 1348 device_initcall(aarch32_el0_sysfs_init); 1349 1350 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1351 { 1352 if (!has_cpuid_feature(entry, scope)) 1353 return allow_mismatched_32bit_el0; 1354 1355 if (scope == SCOPE_SYSTEM) 1356 pr_info("detected: 32-bit EL0 Support\n"); 1357 1358 return true; 1359 } 1360 1361 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1362 { 1363 bool has_sre; 1364 1365 if (!has_cpuid_feature(entry, scope)) 1366 return false; 1367 1368 has_sre = gic_enable_sre(); 1369 if (!has_sre) 1370 pr_warn_once("%s present but disabled by higher exception level\n", 1371 entry->desc); 1372 1373 return has_sre; 1374 } 1375 1376 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1377 { 1378 u32 midr = read_cpuid_id(); 1379 1380 /* Cavium ThunderX pass 1.x and 2.x */ 1381 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1382 MIDR_CPU_VAR_REV(0, 0), 1383 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1384 } 1385 1386 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1387 { 1388 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1389 1390 return cpuid_feature_extract_signed_field(pfr0, 1391 ID_AA64PFR0_FP_SHIFT) < 0; 1392 } 1393 1394 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1395 int scope) 1396 { 1397 u64 ctr; 1398 1399 if (scope == SCOPE_SYSTEM) 1400 ctr = arm64_ftr_reg_ctrel0.sys_val; 1401 else 1402 ctr = read_cpuid_effective_cachetype(); 1403 1404 return ctr & BIT(CTR_IDC_SHIFT); 1405 } 1406 1407 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1408 { 1409 /* 1410 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1411 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1412 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1413 * value. 1414 */ 1415 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1416 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1417 } 1418 1419 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1420 int scope) 1421 { 1422 u64 ctr; 1423 1424 if (scope == SCOPE_SYSTEM) 1425 ctr = arm64_ftr_reg_ctrel0.sys_val; 1426 else 1427 ctr = read_cpuid_cachetype(); 1428 1429 return ctr & BIT(CTR_DIC_SHIFT); 1430 } 1431 1432 static bool __maybe_unused 1433 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1434 { 1435 /* 1436 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1437 * may share TLB entries with a CPU stuck in the crashed 1438 * kernel. 1439 */ 1440 if (is_kdump_kernel()) 1441 return false; 1442 1443 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1444 return false; 1445 1446 return has_cpuid_feature(entry, scope); 1447 } 1448 1449 /* 1450 * This check is triggered during the early boot before the cpufeature 1451 * is initialised. Checking the status on the local CPU allows the boot 1452 * CPU to detect the need for non-global mappings and thus avoiding a 1453 * pagetable re-write after all the CPUs are booted. This check will be 1454 * anyway run on individual CPUs, allowing us to get the consistent 1455 * state once the SMP CPUs are up and thus make the switch to non-global 1456 * mappings if required. 1457 */ 1458 bool kaslr_requires_kpti(void) 1459 { 1460 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1461 return false; 1462 1463 /* 1464 * E0PD does a similar job to KPTI so can be used instead 1465 * where available. 1466 */ 1467 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1468 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1469 if (cpuid_feature_extract_unsigned_field(mmfr2, 1470 ID_AA64MMFR2_E0PD_SHIFT)) 1471 return false; 1472 } 1473 1474 /* 1475 * Systems affected by Cavium erratum 24756 are incompatible 1476 * with KPTI. 1477 */ 1478 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1479 extern const struct midr_range cavium_erratum_27456_cpus[]; 1480 1481 if (is_midr_in_range_list(read_cpuid_id(), 1482 cavium_erratum_27456_cpus)) 1483 return false; 1484 } 1485 1486 return kaslr_offset() > 0; 1487 } 1488 1489 static bool __meltdown_safe = true; 1490 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1491 1492 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1493 int scope) 1494 { 1495 /* List of CPUs that are not vulnerable and don't need KPTI */ 1496 static const struct midr_range kpti_safe_list[] = { 1497 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1498 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1499 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1500 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1501 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1502 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1503 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1504 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1505 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1506 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1507 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1508 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1509 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1510 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1511 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1512 { /* sentinel */ } 1513 }; 1514 char const *str = "kpti command line option"; 1515 bool meltdown_safe; 1516 1517 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1518 1519 /* Defer to CPU feature registers */ 1520 if (has_cpuid_feature(entry, scope)) 1521 meltdown_safe = true; 1522 1523 if (!meltdown_safe) 1524 __meltdown_safe = false; 1525 1526 /* 1527 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1528 * ThunderX leads to apparent I-cache corruption of kernel text, which 1529 * ends as well as you might imagine. Don't even try. 1530 */ 1531 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1532 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1533 __kpti_forced = -1; 1534 } 1535 1536 /* Useful for KASLR robustness */ 1537 if (kaslr_requires_kpti()) { 1538 if (!__kpti_forced) { 1539 str = "KASLR"; 1540 __kpti_forced = 1; 1541 } 1542 } 1543 1544 if (cpu_mitigations_off() && !__kpti_forced) { 1545 str = "mitigations=off"; 1546 __kpti_forced = -1; 1547 } 1548 1549 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1550 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1551 return false; 1552 } 1553 1554 /* Forced? */ 1555 if (__kpti_forced) { 1556 pr_info_once("kernel page table isolation forced %s by %s\n", 1557 __kpti_forced > 0 ? "ON" : "OFF", str); 1558 return __kpti_forced > 0; 1559 } 1560 1561 return !meltdown_safe; 1562 } 1563 1564 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1565 static void __nocfi 1566 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1567 { 1568 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1569 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1570 kpti_remap_fn *remap_fn; 1571 1572 int cpu = smp_processor_id(); 1573 1574 /* 1575 * We don't need to rewrite the page-tables if either we've done 1576 * it already or we have KASLR enabled and therefore have not 1577 * created any global mappings at all. 1578 */ 1579 if (arm64_use_ng_mappings) 1580 return; 1581 1582 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings)); 1583 1584 cpu_install_idmap(); 1585 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1586 cpu_uninstall_idmap(); 1587 1588 if (!cpu) 1589 arm64_use_ng_mappings = true; 1590 } 1591 #else 1592 static void 1593 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1594 { 1595 } 1596 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1597 1598 static int __init parse_kpti(char *str) 1599 { 1600 bool enabled; 1601 int ret = strtobool(str, &enabled); 1602 1603 if (ret) 1604 return ret; 1605 1606 __kpti_forced = enabled ? 1 : -1; 1607 return 0; 1608 } 1609 early_param("kpti", parse_kpti); 1610 1611 #ifdef CONFIG_ARM64_HW_AFDBM 1612 static inline void __cpu_enable_hw_dbm(void) 1613 { 1614 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1615 1616 write_sysreg(tcr, tcr_el1); 1617 isb(); 1618 local_flush_tlb_all(); 1619 } 1620 1621 static bool cpu_has_broken_dbm(void) 1622 { 1623 /* List of CPUs which have broken DBM support. */ 1624 static const struct midr_range cpus[] = { 1625 #ifdef CONFIG_ARM64_ERRATUM_1024718 1626 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1627 /* Kryo4xx Silver (rdpe => r1p0) */ 1628 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1629 #endif 1630 {}, 1631 }; 1632 1633 return is_midr_in_range_list(read_cpuid_id(), cpus); 1634 } 1635 1636 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1637 { 1638 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1639 !cpu_has_broken_dbm(); 1640 } 1641 1642 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1643 { 1644 if (cpu_can_use_dbm(cap)) 1645 __cpu_enable_hw_dbm(); 1646 } 1647 1648 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1649 int __unused) 1650 { 1651 static bool detected = false; 1652 /* 1653 * DBM is a non-conflicting feature. i.e, the kernel can safely 1654 * run a mix of CPUs with and without the feature. So, we 1655 * unconditionally enable the capability to allow any late CPU 1656 * to use the feature. We only enable the control bits on the 1657 * CPU, if it actually supports. 1658 * 1659 * We have to make sure we print the "feature" detection only 1660 * when at least one CPU actually uses it. So check if this CPU 1661 * can actually use it and print the message exactly once. 1662 * 1663 * This is safe as all CPUs (including secondary CPUs - due to the 1664 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1665 * goes through the "matches" check exactly once. Also if a CPU 1666 * matches the criteria, it is guaranteed that the CPU will turn 1667 * the DBM on, as the capability is unconditionally enabled. 1668 */ 1669 if (!detected && cpu_can_use_dbm(cap)) { 1670 detected = true; 1671 pr_info("detected: Hardware dirty bit management\n"); 1672 } 1673 1674 return true; 1675 } 1676 1677 #endif 1678 1679 #ifdef CONFIG_ARM64_AMU_EXTN 1680 1681 /* 1682 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1683 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1684 * information regarding all the events that it supports. When a CPU bit is 1685 * set in the cpumask, the user of this feature can only rely on the presence 1686 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1687 * counters are enabled or access to these counters is enabled by code 1688 * executed at higher exception levels (firmware). 1689 */ 1690 static struct cpumask amu_cpus __read_mostly; 1691 1692 bool cpu_has_amu_feat(int cpu) 1693 { 1694 return cpumask_test_cpu(cpu, &amu_cpus); 1695 } 1696 1697 int get_cpu_with_amu_feat(void) 1698 { 1699 return cpumask_any(&amu_cpus); 1700 } 1701 1702 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1703 { 1704 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1705 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1706 smp_processor_id()); 1707 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1708 update_freq_counters_refs(); 1709 } 1710 } 1711 1712 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1713 int __unused) 1714 { 1715 /* 1716 * The AMU extension is a non-conflicting feature: the kernel can 1717 * safely run a mix of CPUs with and without support for the 1718 * activity monitors extension. Therefore, unconditionally enable 1719 * the capability to allow any late CPU to use the feature. 1720 * 1721 * With this feature unconditionally enabled, the cpu_enable 1722 * function will be called for all CPUs that match the criteria, 1723 * including secondary and hotplugged, marking this feature as 1724 * present on that respective CPU. The enable function will also 1725 * print a detection message. 1726 */ 1727 1728 return true; 1729 } 1730 #else 1731 int get_cpu_with_amu_feat(void) 1732 { 1733 return nr_cpu_ids; 1734 } 1735 #endif 1736 1737 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1738 { 1739 return is_kernel_in_hyp_mode(); 1740 } 1741 1742 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1743 { 1744 /* 1745 * Copy register values that aren't redirected by hardware. 1746 * 1747 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1748 * this value to tpidr_el2 before we patch the code. Once we've done 1749 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1750 * do anything here. 1751 */ 1752 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1753 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1754 } 1755 1756 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1757 { 1758 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1759 1760 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1761 WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val)); 1762 } 1763 1764 #ifdef CONFIG_ARM64_PAN 1765 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1766 { 1767 /* 1768 * We modify PSTATE. This won't work from irq context as the PSTATE 1769 * is discarded once we return from the exception. 1770 */ 1771 WARN_ON_ONCE(in_interrupt()); 1772 1773 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1774 set_pstate_pan(1); 1775 } 1776 #endif /* CONFIG_ARM64_PAN */ 1777 1778 #ifdef CONFIG_ARM64_RAS_EXTN 1779 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1780 { 1781 /* Firmware may have left a deferred SError in this register. */ 1782 write_sysreg_s(0, SYS_DISR_EL1); 1783 } 1784 #endif /* CONFIG_ARM64_RAS_EXTN */ 1785 1786 #ifdef CONFIG_ARM64_PTR_AUTH 1787 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1788 { 1789 int boot_val, sec_val; 1790 1791 /* We don't expect to be called with SCOPE_SYSTEM */ 1792 WARN_ON(scope == SCOPE_SYSTEM); 1793 /* 1794 * The ptr-auth feature levels are not intercompatible with lower 1795 * levels. Hence we must match ptr-auth feature level of the secondary 1796 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1797 * from the sanitised register whereas direct register read is done for 1798 * the secondary CPUs. 1799 * The sanitised feature state is guaranteed to match that of the 1800 * boot CPU as a mismatched secondary CPU is parked before it gets 1801 * a chance to update the state, with the capability. 1802 */ 1803 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1804 entry->field_pos, entry->sign); 1805 if (scope & SCOPE_BOOT_CPU) 1806 return boot_val >= entry->min_field_value; 1807 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1808 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1809 entry->field_pos, entry->sign); 1810 return sec_val == boot_val; 1811 } 1812 1813 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1814 int scope) 1815 { 1816 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1817 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1818 } 1819 1820 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1821 int __unused) 1822 { 1823 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1824 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1825 } 1826 #endif /* CONFIG_ARM64_PTR_AUTH */ 1827 1828 #ifdef CONFIG_ARM64_E0PD 1829 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1830 { 1831 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1832 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1833 } 1834 #endif /* CONFIG_ARM64_E0PD */ 1835 1836 #ifdef CONFIG_ARM64_PSEUDO_NMI 1837 static bool enable_pseudo_nmi; 1838 1839 static int __init early_enable_pseudo_nmi(char *p) 1840 { 1841 return strtobool(p, &enable_pseudo_nmi); 1842 } 1843 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1844 1845 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1846 int scope) 1847 { 1848 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1849 } 1850 #endif 1851 1852 #ifdef CONFIG_ARM64_BTI 1853 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1854 { 1855 /* 1856 * Use of X16/X17 for tail-calls and trampolines that jump to 1857 * function entry points using BR is a requirement for 1858 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1859 * So, be strict and forbid other BRs using other registers to 1860 * jump onto a PACIxSP instruction: 1861 */ 1862 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1863 isb(); 1864 } 1865 #endif /* CONFIG_ARM64_BTI */ 1866 1867 #ifdef CONFIG_ARM64_MTE 1868 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1869 { 1870 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 1871 isb(); 1872 1873 /* 1874 * Clear the tags in the zero page. This needs to be done via the 1875 * linear map which has the Tagged attribute. 1876 */ 1877 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1878 mte_clear_page_tags(lm_alias(empty_zero_page)); 1879 1880 kasan_init_hw_tags_cpu(); 1881 } 1882 #endif /* CONFIG_ARM64_MTE */ 1883 1884 #ifdef CONFIG_KVM 1885 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1886 { 1887 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1888 return false; 1889 1890 if (is_kernel_in_hyp_mode()) { 1891 pr_warn("Protected KVM not available with VHE\n"); 1892 return false; 1893 } 1894 1895 return true; 1896 } 1897 #endif /* CONFIG_KVM */ 1898 1899 /* Internal helper functions to match cpu capability type */ 1900 static bool 1901 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1902 { 1903 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1904 } 1905 1906 static bool 1907 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1908 { 1909 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1910 } 1911 1912 static bool 1913 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1914 { 1915 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1916 } 1917 1918 static const struct arm64_cpu_capabilities arm64_features[] = { 1919 { 1920 .desc = "GIC system register CPU interface", 1921 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1922 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1923 .matches = has_useable_gicv3_cpuif, 1924 .sys_reg = SYS_ID_AA64PFR0_EL1, 1925 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1926 .sign = FTR_UNSIGNED, 1927 .min_field_value = 1, 1928 }, 1929 #ifdef CONFIG_ARM64_PAN 1930 { 1931 .desc = "Privileged Access Never", 1932 .capability = ARM64_HAS_PAN, 1933 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1934 .matches = has_cpuid_feature, 1935 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1936 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1937 .sign = FTR_UNSIGNED, 1938 .min_field_value = 1, 1939 .cpu_enable = cpu_enable_pan, 1940 }, 1941 #endif /* CONFIG_ARM64_PAN */ 1942 #ifdef CONFIG_ARM64_EPAN 1943 { 1944 .desc = "Enhanced Privileged Access Never", 1945 .capability = ARM64_HAS_EPAN, 1946 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1947 .matches = has_cpuid_feature, 1948 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1949 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1950 .sign = FTR_UNSIGNED, 1951 .min_field_value = 3, 1952 }, 1953 #endif /* CONFIG_ARM64_EPAN */ 1954 #ifdef CONFIG_ARM64_LSE_ATOMICS 1955 { 1956 .desc = "LSE atomic instructions", 1957 .capability = ARM64_HAS_LSE_ATOMICS, 1958 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1959 .matches = has_cpuid_feature, 1960 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1961 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1962 .sign = FTR_UNSIGNED, 1963 .min_field_value = 2, 1964 }, 1965 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1966 { 1967 .desc = "Software prefetching using PRFM", 1968 .capability = ARM64_HAS_NO_HW_PREFETCH, 1969 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1970 .matches = has_no_hw_prefetch, 1971 }, 1972 { 1973 .desc = "Virtualization Host Extensions", 1974 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1975 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1976 .matches = runs_at_el2, 1977 .cpu_enable = cpu_copy_el2regs, 1978 }, 1979 { 1980 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 1981 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1982 .matches = has_32bit_el0, 1983 .sys_reg = SYS_ID_AA64PFR0_EL1, 1984 .sign = FTR_UNSIGNED, 1985 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1986 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 1987 }, 1988 #ifdef CONFIG_KVM 1989 { 1990 .desc = "32-bit EL1 Support", 1991 .capability = ARM64_HAS_32BIT_EL1, 1992 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1993 .matches = has_cpuid_feature, 1994 .sys_reg = SYS_ID_AA64PFR0_EL1, 1995 .sign = FTR_UNSIGNED, 1996 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1997 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 1998 }, 1999 { 2000 .desc = "Protected KVM", 2001 .capability = ARM64_KVM_PROTECTED_MODE, 2002 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2003 .matches = is_kvm_protected_mode, 2004 }, 2005 #endif 2006 { 2007 .desc = "Kernel page table isolation (KPTI)", 2008 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2009 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2010 /* 2011 * The ID feature fields below are used to indicate that 2012 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2013 * more details. 2014 */ 2015 .sys_reg = SYS_ID_AA64PFR0_EL1, 2016 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 2017 .min_field_value = 1, 2018 .matches = unmap_kernel_at_el0, 2019 .cpu_enable = kpti_install_ng_mappings, 2020 }, 2021 { 2022 /* FP/SIMD is not implemented */ 2023 .capability = ARM64_HAS_NO_FPSIMD, 2024 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2025 .min_field_value = 0, 2026 .matches = has_no_fpsimd, 2027 }, 2028 #ifdef CONFIG_ARM64_PMEM 2029 { 2030 .desc = "Data cache clean to Point of Persistence", 2031 .capability = ARM64_HAS_DCPOP, 2032 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2033 .matches = has_cpuid_feature, 2034 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2035 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2036 .min_field_value = 1, 2037 }, 2038 { 2039 .desc = "Data cache clean to Point of Deep Persistence", 2040 .capability = ARM64_HAS_DCPODP, 2041 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2042 .matches = has_cpuid_feature, 2043 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2044 .sign = FTR_UNSIGNED, 2045 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2046 .min_field_value = 2, 2047 }, 2048 #endif 2049 #ifdef CONFIG_ARM64_SVE 2050 { 2051 .desc = "Scalable Vector Extension", 2052 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2053 .capability = ARM64_SVE, 2054 .sys_reg = SYS_ID_AA64PFR0_EL1, 2055 .sign = FTR_UNSIGNED, 2056 .field_pos = ID_AA64PFR0_SVE_SHIFT, 2057 .min_field_value = ID_AA64PFR0_SVE, 2058 .matches = has_cpuid_feature, 2059 .cpu_enable = sve_kernel_enable, 2060 }, 2061 #endif /* CONFIG_ARM64_SVE */ 2062 #ifdef CONFIG_ARM64_RAS_EXTN 2063 { 2064 .desc = "RAS Extension Support", 2065 .capability = ARM64_HAS_RAS_EXTN, 2066 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2067 .matches = has_cpuid_feature, 2068 .sys_reg = SYS_ID_AA64PFR0_EL1, 2069 .sign = FTR_UNSIGNED, 2070 .field_pos = ID_AA64PFR0_RAS_SHIFT, 2071 .min_field_value = ID_AA64PFR0_RAS_V1, 2072 .cpu_enable = cpu_clear_disr, 2073 }, 2074 #endif /* CONFIG_ARM64_RAS_EXTN */ 2075 #ifdef CONFIG_ARM64_AMU_EXTN 2076 { 2077 /* 2078 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2079 * Therefore, don't provide .desc as we don't want the detection 2080 * message to be shown until at least one CPU is detected to 2081 * support the feature. 2082 */ 2083 .capability = ARM64_HAS_AMU_EXTN, 2084 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2085 .matches = has_amu, 2086 .sys_reg = SYS_ID_AA64PFR0_EL1, 2087 .sign = FTR_UNSIGNED, 2088 .field_pos = ID_AA64PFR0_AMU_SHIFT, 2089 .min_field_value = ID_AA64PFR0_AMU, 2090 .cpu_enable = cpu_amu_enable, 2091 }, 2092 #endif /* CONFIG_ARM64_AMU_EXTN */ 2093 { 2094 .desc = "Data cache clean to the PoU not required for I/D coherence", 2095 .capability = ARM64_HAS_CACHE_IDC, 2096 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2097 .matches = has_cache_idc, 2098 .cpu_enable = cpu_emulate_effective_ctr, 2099 }, 2100 { 2101 .desc = "Instruction cache invalidation not required for I/D coherence", 2102 .capability = ARM64_HAS_CACHE_DIC, 2103 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2104 .matches = has_cache_dic, 2105 }, 2106 { 2107 .desc = "Stage-2 Force Write-Back", 2108 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2109 .capability = ARM64_HAS_STAGE2_FWB, 2110 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2111 .sign = FTR_UNSIGNED, 2112 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 2113 .min_field_value = 1, 2114 .matches = has_cpuid_feature, 2115 .cpu_enable = cpu_has_fwb, 2116 }, 2117 { 2118 .desc = "ARMv8.4 Translation Table Level", 2119 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2120 .capability = ARM64_HAS_ARMv8_4_TTL, 2121 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2122 .sign = FTR_UNSIGNED, 2123 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2124 .min_field_value = 1, 2125 .matches = has_cpuid_feature, 2126 }, 2127 { 2128 .desc = "TLB range maintenance instructions", 2129 .capability = ARM64_HAS_TLB_RANGE, 2130 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2131 .matches = has_cpuid_feature, 2132 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2133 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2134 .sign = FTR_UNSIGNED, 2135 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2136 }, 2137 #ifdef CONFIG_ARM64_HW_AFDBM 2138 { 2139 /* 2140 * Since we turn this on always, we don't want the user to 2141 * think that the feature is available when it may not be. 2142 * So hide the description. 2143 * 2144 * .desc = "Hardware pagetable Dirty Bit Management", 2145 * 2146 */ 2147 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2148 .capability = ARM64_HW_DBM, 2149 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2150 .sign = FTR_UNSIGNED, 2151 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2152 .min_field_value = 2, 2153 .matches = has_hw_dbm, 2154 .cpu_enable = cpu_enable_hw_dbm, 2155 }, 2156 #endif 2157 { 2158 .desc = "CRC32 instructions", 2159 .capability = ARM64_HAS_CRC32, 2160 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2161 .matches = has_cpuid_feature, 2162 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2163 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2164 .min_field_value = 1, 2165 }, 2166 { 2167 .desc = "Speculative Store Bypassing Safe (SSBS)", 2168 .capability = ARM64_SSBS, 2169 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2170 .matches = has_cpuid_feature, 2171 .sys_reg = SYS_ID_AA64PFR1_EL1, 2172 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2173 .sign = FTR_UNSIGNED, 2174 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2175 }, 2176 #ifdef CONFIG_ARM64_CNP 2177 { 2178 .desc = "Common not Private translations", 2179 .capability = ARM64_HAS_CNP, 2180 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2181 .matches = has_useable_cnp, 2182 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2183 .sign = FTR_UNSIGNED, 2184 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2185 .min_field_value = 1, 2186 .cpu_enable = cpu_enable_cnp, 2187 }, 2188 #endif 2189 { 2190 .desc = "Speculation barrier (SB)", 2191 .capability = ARM64_HAS_SB, 2192 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2193 .matches = has_cpuid_feature, 2194 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2195 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2196 .sign = FTR_UNSIGNED, 2197 .min_field_value = 1, 2198 }, 2199 #ifdef CONFIG_ARM64_PTR_AUTH 2200 { 2201 .desc = "Address authentication (architected algorithm)", 2202 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2203 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2204 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2205 .sign = FTR_UNSIGNED, 2206 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2207 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2208 .matches = has_address_auth_cpucap, 2209 }, 2210 { 2211 .desc = "Address authentication (IMP DEF algorithm)", 2212 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2213 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2214 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2215 .sign = FTR_UNSIGNED, 2216 .field_pos = ID_AA64ISAR1_API_SHIFT, 2217 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2218 .matches = has_address_auth_cpucap, 2219 }, 2220 { 2221 .capability = ARM64_HAS_ADDRESS_AUTH, 2222 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2223 .matches = has_address_auth_metacap, 2224 }, 2225 { 2226 .desc = "Generic authentication (architected algorithm)", 2227 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2228 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2229 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2230 .sign = FTR_UNSIGNED, 2231 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2232 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2233 .matches = has_cpuid_feature, 2234 }, 2235 { 2236 .desc = "Generic authentication (IMP DEF algorithm)", 2237 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2238 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2239 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2240 .sign = FTR_UNSIGNED, 2241 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2242 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2243 .matches = has_cpuid_feature, 2244 }, 2245 { 2246 .capability = ARM64_HAS_GENERIC_AUTH, 2247 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2248 .matches = has_generic_auth, 2249 }, 2250 #endif /* CONFIG_ARM64_PTR_AUTH */ 2251 #ifdef CONFIG_ARM64_PSEUDO_NMI 2252 { 2253 /* 2254 * Depends on having GICv3 2255 */ 2256 .desc = "IRQ priority masking", 2257 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2258 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2259 .matches = can_use_gic_priorities, 2260 .sys_reg = SYS_ID_AA64PFR0_EL1, 2261 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2262 .sign = FTR_UNSIGNED, 2263 .min_field_value = 1, 2264 }, 2265 #endif 2266 #ifdef CONFIG_ARM64_E0PD 2267 { 2268 .desc = "E0PD", 2269 .capability = ARM64_HAS_E0PD, 2270 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2271 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2272 .sign = FTR_UNSIGNED, 2273 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2274 .matches = has_cpuid_feature, 2275 .min_field_value = 1, 2276 .cpu_enable = cpu_enable_e0pd, 2277 }, 2278 #endif 2279 #ifdef CONFIG_ARCH_RANDOM 2280 { 2281 .desc = "Random Number Generator", 2282 .capability = ARM64_HAS_RNG, 2283 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2284 .matches = has_cpuid_feature, 2285 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2286 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2287 .sign = FTR_UNSIGNED, 2288 .min_field_value = 1, 2289 }, 2290 #endif 2291 #ifdef CONFIG_ARM64_BTI 2292 { 2293 .desc = "Branch Target Identification", 2294 .capability = ARM64_BTI, 2295 #ifdef CONFIG_ARM64_BTI_KERNEL 2296 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2297 #else 2298 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2299 #endif 2300 .matches = has_cpuid_feature, 2301 .cpu_enable = bti_enable, 2302 .sys_reg = SYS_ID_AA64PFR1_EL1, 2303 .field_pos = ID_AA64PFR1_BT_SHIFT, 2304 .min_field_value = ID_AA64PFR1_BT_BTI, 2305 .sign = FTR_UNSIGNED, 2306 }, 2307 #endif 2308 #ifdef CONFIG_ARM64_MTE 2309 { 2310 .desc = "Memory Tagging Extension", 2311 .capability = ARM64_MTE, 2312 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2313 .matches = has_cpuid_feature, 2314 .sys_reg = SYS_ID_AA64PFR1_EL1, 2315 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2316 .min_field_value = ID_AA64PFR1_MTE, 2317 .sign = FTR_UNSIGNED, 2318 .cpu_enable = cpu_enable_mte, 2319 }, 2320 #endif /* CONFIG_ARM64_MTE */ 2321 { 2322 .desc = "RCpc load-acquire (LDAPR)", 2323 .capability = ARM64_HAS_LDAPR, 2324 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2325 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2326 .sign = FTR_UNSIGNED, 2327 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2328 .matches = has_cpuid_feature, 2329 .min_field_value = 1, 2330 }, 2331 {}, 2332 }; 2333 2334 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2335 .matches = has_cpuid_feature, \ 2336 .sys_reg = reg, \ 2337 .field_pos = field, \ 2338 .sign = s, \ 2339 .min_field_value = min_value, 2340 2341 #define __HWCAP_CAP(name, cap_type, cap) \ 2342 .desc = name, \ 2343 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2344 .hwcap_type = cap_type, \ 2345 .hwcap = cap, \ 2346 2347 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2348 { \ 2349 __HWCAP_CAP(#cap, cap_type, cap) \ 2350 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2351 } 2352 2353 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2354 { \ 2355 __HWCAP_CAP(#cap, cap_type, cap) \ 2356 .matches = cpucap_multi_entry_cap_matches, \ 2357 .match_list = list, \ 2358 } 2359 2360 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2361 { \ 2362 __HWCAP_CAP(#cap, cap_type, cap) \ 2363 .matches = match, \ 2364 } 2365 2366 #ifdef CONFIG_ARM64_PTR_AUTH 2367 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2368 { 2369 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2370 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2371 }, 2372 { 2373 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2374 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2375 }, 2376 {}, 2377 }; 2378 2379 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2380 { 2381 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2382 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2383 }, 2384 { 2385 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2386 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2387 }, 2388 {}, 2389 }; 2390 #endif 2391 2392 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2393 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2394 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2395 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2396 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2397 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2398 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2399 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2400 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2401 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2402 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2403 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2404 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2405 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2406 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2407 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2408 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2409 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2410 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2411 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2412 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2413 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2414 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2415 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2416 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2417 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2418 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2419 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2420 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2421 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2422 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2423 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2424 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2425 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2426 #ifdef CONFIG_ARM64_SVE 2427 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2428 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2429 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2430 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2431 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2432 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2433 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2434 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2435 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2436 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2437 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2438 #endif 2439 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2440 #ifdef CONFIG_ARM64_BTI 2441 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2442 #endif 2443 #ifdef CONFIG_ARM64_PTR_AUTH 2444 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2445 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2446 #endif 2447 #ifdef CONFIG_ARM64_MTE 2448 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2449 #endif /* CONFIG_ARM64_MTE */ 2450 {}, 2451 }; 2452 2453 #ifdef CONFIG_COMPAT 2454 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2455 { 2456 /* 2457 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2458 * in line with that of arm32 as in vfp_init(). We make sure that the 2459 * check is future proof, by making sure value is non-zero. 2460 */ 2461 u32 mvfr1; 2462 2463 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2464 if (scope == SCOPE_SYSTEM) 2465 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2466 else 2467 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2468 2469 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2470 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2471 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2472 } 2473 #endif 2474 2475 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2476 #ifdef CONFIG_COMPAT 2477 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2478 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2479 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2480 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2481 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2482 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2483 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2484 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2485 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2486 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2487 #endif 2488 {}, 2489 }; 2490 2491 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2492 { 2493 switch (cap->hwcap_type) { 2494 case CAP_HWCAP: 2495 cpu_set_feature(cap->hwcap); 2496 break; 2497 #ifdef CONFIG_COMPAT 2498 case CAP_COMPAT_HWCAP: 2499 compat_elf_hwcap |= (u32)cap->hwcap; 2500 break; 2501 case CAP_COMPAT_HWCAP2: 2502 compat_elf_hwcap2 |= (u32)cap->hwcap; 2503 break; 2504 #endif 2505 default: 2506 WARN_ON(1); 2507 break; 2508 } 2509 } 2510 2511 /* Check if we have a particular HWCAP enabled */ 2512 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2513 { 2514 bool rc; 2515 2516 switch (cap->hwcap_type) { 2517 case CAP_HWCAP: 2518 rc = cpu_have_feature(cap->hwcap); 2519 break; 2520 #ifdef CONFIG_COMPAT 2521 case CAP_COMPAT_HWCAP: 2522 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2523 break; 2524 case CAP_COMPAT_HWCAP2: 2525 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2526 break; 2527 #endif 2528 default: 2529 WARN_ON(1); 2530 rc = false; 2531 } 2532 2533 return rc; 2534 } 2535 2536 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2537 { 2538 /* We support emulation of accesses to CPU ID feature registers */ 2539 cpu_set_named_feature(CPUID); 2540 for (; hwcaps->matches; hwcaps++) 2541 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2542 cap_set_elf_hwcap(hwcaps); 2543 } 2544 2545 static void update_cpu_capabilities(u16 scope_mask) 2546 { 2547 int i; 2548 const struct arm64_cpu_capabilities *caps; 2549 2550 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2551 for (i = 0; i < ARM64_NCAPS; i++) { 2552 caps = cpu_hwcaps_ptrs[i]; 2553 if (!caps || !(caps->type & scope_mask) || 2554 cpus_have_cap(caps->capability) || 2555 !caps->matches(caps, cpucap_default_scope(caps))) 2556 continue; 2557 2558 if (caps->desc) 2559 pr_info("detected: %s\n", caps->desc); 2560 cpus_set_cap(caps->capability); 2561 2562 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2563 set_bit(caps->capability, boot_capabilities); 2564 } 2565 } 2566 2567 /* 2568 * Enable all the available capabilities on this CPU. The capabilities 2569 * with BOOT_CPU scope are handled separately and hence skipped here. 2570 */ 2571 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2572 { 2573 int i; 2574 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2575 2576 for_each_available_cap(i) { 2577 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2578 2579 if (WARN_ON(!cap)) 2580 continue; 2581 2582 if (!(cap->type & non_boot_scope)) 2583 continue; 2584 2585 if (cap->cpu_enable) 2586 cap->cpu_enable(cap); 2587 } 2588 return 0; 2589 } 2590 2591 /* 2592 * Run through the enabled capabilities and enable() it on all active 2593 * CPUs 2594 */ 2595 static void __init enable_cpu_capabilities(u16 scope_mask) 2596 { 2597 int i; 2598 const struct arm64_cpu_capabilities *caps; 2599 bool boot_scope; 2600 2601 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2602 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2603 2604 for (i = 0; i < ARM64_NCAPS; i++) { 2605 unsigned int num; 2606 2607 caps = cpu_hwcaps_ptrs[i]; 2608 if (!caps || !(caps->type & scope_mask)) 2609 continue; 2610 num = caps->capability; 2611 if (!cpus_have_cap(num)) 2612 continue; 2613 2614 /* Ensure cpus_have_const_cap(num) works */ 2615 static_branch_enable(&cpu_hwcap_keys[num]); 2616 2617 if (boot_scope && caps->cpu_enable) 2618 /* 2619 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2620 * before any secondary CPU boots. Thus, each secondary 2621 * will enable the capability as appropriate via 2622 * check_local_cpu_capabilities(). The only exception is 2623 * the boot CPU, for which the capability must be 2624 * enabled here. This approach avoids costly 2625 * stop_machine() calls for this case. 2626 */ 2627 caps->cpu_enable(caps); 2628 } 2629 2630 /* 2631 * For all non-boot scope capabilities, use stop_machine() 2632 * as it schedules the work allowing us to modify PSTATE, 2633 * instead of on_each_cpu() which uses an IPI, giving us a 2634 * PSTATE that disappears when we return. 2635 */ 2636 if (!boot_scope) 2637 stop_machine(cpu_enable_non_boot_scope_capabilities, 2638 NULL, cpu_online_mask); 2639 } 2640 2641 /* 2642 * Run through the list of capabilities to check for conflicts. 2643 * If the system has already detected a capability, take necessary 2644 * action on this CPU. 2645 */ 2646 static void verify_local_cpu_caps(u16 scope_mask) 2647 { 2648 int i; 2649 bool cpu_has_cap, system_has_cap; 2650 const struct arm64_cpu_capabilities *caps; 2651 2652 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2653 2654 for (i = 0; i < ARM64_NCAPS; i++) { 2655 caps = cpu_hwcaps_ptrs[i]; 2656 if (!caps || !(caps->type & scope_mask)) 2657 continue; 2658 2659 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2660 system_has_cap = cpus_have_cap(caps->capability); 2661 2662 if (system_has_cap) { 2663 /* 2664 * Check if the new CPU misses an advertised feature, 2665 * which is not safe to miss. 2666 */ 2667 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2668 break; 2669 /* 2670 * We have to issue cpu_enable() irrespective of 2671 * whether the CPU has it or not, as it is enabeld 2672 * system wide. It is upto the call back to take 2673 * appropriate action on this CPU. 2674 */ 2675 if (caps->cpu_enable) 2676 caps->cpu_enable(caps); 2677 } else { 2678 /* 2679 * Check if the CPU has this capability if it isn't 2680 * safe to have when the system doesn't. 2681 */ 2682 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2683 break; 2684 } 2685 } 2686 2687 if (i < ARM64_NCAPS) { 2688 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2689 smp_processor_id(), caps->capability, 2690 caps->desc, system_has_cap, cpu_has_cap); 2691 2692 if (cpucap_panic_on_conflict(caps)) 2693 cpu_panic_kernel(); 2694 else 2695 cpu_die_early(); 2696 } 2697 } 2698 2699 /* 2700 * Check for CPU features that are used in early boot 2701 * based on the Boot CPU value. 2702 */ 2703 static void check_early_cpu_features(void) 2704 { 2705 verify_cpu_asid_bits(); 2706 2707 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2708 } 2709 2710 static void 2711 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2712 { 2713 2714 for (; caps->matches; caps++) 2715 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2716 pr_crit("CPU%d: missing HWCAP: %s\n", 2717 smp_processor_id(), caps->desc); 2718 cpu_die_early(); 2719 } 2720 } 2721 2722 static void verify_local_elf_hwcaps(void) 2723 { 2724 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 2725 2726 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 2727 __verify_local_elf_hwcaps(compat_elf_hwcaps); 2728 } 2729 2730 static void verify_sve_features(void) 2731 { 2732 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2733 u64 zcr = read_zcr_features(); 2734 2735 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2736 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2737 2738 if (len < safe_len || sve_verify_vq_map()) { 2739 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2740 smp_processor_id()); 2741 cpu_die_early(); 2742 } 2743 2744 /* Add checks on other ZCR bits here if necessary */ 2745 } 2746 2747 static void verify_hyp_capabilities(void) 2748 { 2749 u64 safe_mmfr1, mmfr0, mmfr1; 2750 int parange, ipa_max; 2751 unsigned int safe_vmid_bits, vmid_bits; 2752 2753 if (!IS_ENABLED(CONFIG_KVM)) 2754 return; 2755 2756 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2757 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2758 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2759 2760 /* Verify VMID bits */ 2761 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2762 vmid_bits = get_vmid_bits(mmfr1); 2763 if (vmid_bits < safe_vmid_bits) { 2764 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2765 cpu_die_early(); 2766 } 2767 2768 /* Verify IPA range */ 2769 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2770 ID_AA64MMFR0_PARANGE_SHIFT); 2771 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2772 if (ipa_max < get_kvm_ipa_limit()) { 2773 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2774 cpu_die_early(); 2775 } 2776 } 2777 2778 /* 2779 * Run through the enabled system capabilities and enable() it on this CPU. 2780 * The capabilities were decided based on the available CPUs at the boot time. 2781 * Any new CPU should match the system wide status of the capability. If the 2782 * new CPU doesn't have a capability which the system now has enabled, we 2783 * cannot do anything to fix it up and could cause unexpected failures. So 2784 * we park the CPU. 2785 */ 2786 static void verify_local_cpu_capabilities(void) 2787 { 2788 /* 2789 * The capabilities with SCOPE_BOOT_CPU are checked from 2790 * check_early_cpu_features(), as they need to be verified 2791 * on all secondary CPUs. 2792 */ 2793 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2794 verify_local_elf_hwcaps(); 2795 2796 if (system_supports_sve()) 2797 verify_sve_features(); 2798 2799 if (is_hyp_mode_available()) 2800 verify_hyp_capabilities(); 2801 } 2802 2803 void check_local_cpu_capabilities(void) 2804 { 2805 /* 2806 * All secondary CPUs should conform to the early CPU features 2807 * in use by the kernel based on boot CPU. 2808 */ 2809 check_early_cpu_features(); 2810 2811 /* 2812 * If we haven't finalised the system capabilities, this CPU gets 2813 * a chance to update the errata work arounds and local features. 2814 * Otherwise, this CPU should verify that it has all the system 2815 * advertised capabilities. 2816 */ 2817 if (!system_capabilities_finalized()) 2818 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2819 else 2820 verify_local_cpu_capabilities(); 2821 } 2822 2823 static void __init setup_boot_cpu_capabilities(void) 2824 { 2825 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2826 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2827 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2828 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2829 } 2830 2831 bool this_cpu_has_cap(unsigned int n) 2832 { 2833 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2834 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2835 2836 if (cap) 2837 return cap->matches(cap, SCOPE_LOCAL_CPU); 2838 } 2839 2840 return false; 2841 } 2842 2843 /* 2844 * This helper function is used in a narrow window when, 2845 * - The system wide safe registers are set with all the SMP CPUs and, 2846 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2847 * In all other cases cpus_have_{const_}cap() should be used. 2848 */ 2849 static bool __maybe_unused __system_matches_cap(unsigned int n) 2850 { 2851 if (n < ARM64_NCAPS) { 2852 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2853 2854 if (cap) 2855 return cap->matches(cap, SCOPE_SYSTEM); 2856 } 2857 return false; 2858 } 2859 2860 void cpu_set_feature(unsigned int num) 2861 { 2862 WARN_ON(num >= MAX_CPU_FEATURES); 2863 elf_hwcap |= BIT(num); 2864 } 2865 EXPORT_SYMBOL_GPL(cpu_set_feature); 2866 2867 bool cpu_have_feature(unsigned int num) 2868 { 2869 WARN_ON(num >= MAX_CPU_FEATURES); 2870 return elf_hwcap & BIT(num); 2871 } 2872 EXPORT_SYMBOL_GPL(cpu_have_feature); 2873 2874 unsigned long cpu_get_elf_hwcap(void) 2875 { 2876 /* 2877 * We currently only populate the first 32 bits of AT_HWCAP. Please 2878 * note that for userspace compatibility we guarantee that bits 62 2879 * and 63 will always be returned as 0. 2880 */ 2881 return lower_32_bits(elf_hwcap); 2882 } 2883 2884 unsigned long cpu_get_elf_hwcap2(void) 2885 { 2886 return upper_32_bits(elf_hwcap); 2887 } 2888 2889 static void __init setup_system_capabilities(void) 2890 { 2891 /* 2892 * We have finalised the system-wide safe feature 2893 * registers, finalise the capabilities that depend 2894 * on it. Also enable all the available capabilities, 2895 * that are not enabled already. 2896 */ 2897 update_cpu_capabilities(SCOPE_SYSTEM); 2898 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2899 } 2900 2901 void __init setup_cpu_features(void) 2902 { 2903 u32 cwg; 2904 2905 setup_system_capabilities(); 2906 setup_elf_hwcaps(arm64_elf_hwcaps); 2907 2908 if (system_supports_32bit_el0()) 2909 setup_elf_hwcaps(compat_elf_hwcaps); 2910 2911 if (system_uses_ttbr0_pan()) 2912 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2913 2914 sve_setup(); 2915 minsigstksz_setup(); 2916 2917 /* Advertise that we have computed the system capabilities */ 2918 finalize_system_capabilities(); 2919 2920 /* 2921 * Check for sane CTR_EL0.CWG value. 2922 */ 2923 cwg = cache_type_cwg(); 2924 if (!cwg) 2925 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2926 ARCH_DMA_MINALIGN); 2927 } 2928 2929 static int enable_mismatched_32bit_el0(unsigned int cpu) 2930 { 2931 /* 2932 * The first 32-bit-capable CPU we detected and so can no longer 2933 * be offlined by userspace. -1 indicates we haven't yet onlined 2934 * a 32-bit-capable CPU. 2935 */ 2936 static int lucky_winner = -1; 2937 2938 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 2939 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 2940 2941 if (cpu_32bit) { 2942 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 2943 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 2944 } 2945 2946 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 2947 return 0; 2948 2949 if (lucky_winner >= 0) 2950 return 0; 2951 2952 /* 2953 * We've detected a mismatch. We need to keep one of our CPUs with 2954 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 2955 * every CPU in the system for a 32-bit task. 2956 */ 2957 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 2958 cpu_active_mask); 2959 get_cpu_device(lucky_winner)->offline_disabled = true; 2960 setup_elf_hwcaps(compat_elf_hwcaps); 2961 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 2962 cpu, lucky_winner); 2963 return 0; 2964 } 2965 2966 static int __init init_32bit_el0_mask(void) 2967 { 2968 if (!allow_mismatched_32bit_el0) 2969 return 0; 2970 2971 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 2972 return -ENOMEM; 2973 2974 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 2975 "arm64/mismatched_32bit_el0:online", 2976 enable_mismatched_32bit_el0, NULL); 2977 } 2978 subsys_initcall_sync(init_32bit_el0_mask); 2979 2980 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2981 { 2982 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2983 } 2984 2985 /* 2986 * We emulate only the following system register space. 2987 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2988 * See Table C5-6 System instruction encodings for System register accesses, 2989 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2990 */ 2991 static inline bool __attribute_const__ is_emulated(u32 id) 2992 { 2993 return (sys_reg_Op0(id) == 0x3 && 2994 sys_reg_CRn(id) == 0x0 && 2995 sys_reg_Op1(id) == 0x0 && 2996 (sys_reg_CRm(id) == 0 || 2997 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2998 } 2999 3000 /* 3001 * With CRm == 0, reg should be one of : 3002 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3003 */ 3004 static inline int emulate_id_reg(u32 id, u64 *valp) 3005 { 3006 switch (id) { 3007 case SYS_MIDR_EL1: 3008 *valp = read_cpuid_id(); 3009 break; 3010 case SYS_MPIDR_EL1: 3011 *valp = SYS_MPIDR_SAFE_VAL; 3012 break; 3013 case SYS_REVIDR_EL1: 3014 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3015 *valp = 0; 3016 break; 3017 default: 3018 return -EINVAL; 3019 } 3020 3021 return 0; 3022 } 3023 3024 static int emulate_sys_reg(u32 id, u64 *valp) 3025 { 3026 struct arm64_ftr_reg *regp; 3027 3028 if (!is_emulated(id)) 3029 return -EINVAL; 3030 3031 if (sys_reg_CRm(id) == 0) 3032 return emulate_id_reg(id, valp); 3033 3034 regp = get_arm64_ftr_reg_nowarn(id); 3035 if (regp) 3036 *valp = arm64_ftr_reg_user_value(regp); 3037 else 3038 /* 3039 * The untracked registers are either IMPLEMENTATION DEFINED 3040 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3041 */ 3042 *valp = 0; 3043 return 0; 3044 } 3045 3046 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3047 { 3048 int rc; 3049 u64 val; 3050 3051 rc = emulate_sys_reg(sys_reg, &val); 3052 if (!rc) { 3053 pt_regs_write_reg(regs, rt, val); 3054 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3055 } 3056 return rc; 3057 } 3058 3059 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3060 { 3061 u32 sys_reg, rt; 3062 3063 /* 3064 * sys_reg values are defined as used in mrs/msr instruction. 3065 * shift the imm value to get the encoding. 3066 */ 3067 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3068 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3069 return do_emulate_mrs(regs, sys_reg, rt); 3070 } 3071 3072 static struct undef_hook mrs_hook = { 3073 .instr_mask = 0xffff0000, 3074 .instr_val = 0xd5380000, 3075 .pstate_mask = PSR_AA32_MODE_MASK, 3076 .pstate_val = PSR_MODE_EL0t, 3077 .fn = emulate_mrs, 3078 }; 3079 3080 static int __init enable_mrs_emulation(void) 3081 { 3082 register_undef_hook(&mrs_hook); 3083 return 0; 3084 } 3085 3086 core_initcall(enable_mrs_emulation); 3087 3088 enum mitigation_state arm64_get_meltdown_state(void) 3089 { 3090 if (__meltdown_safe) 3091 return SPECTRE_UNAFFECTED; 3092 3093 if (arm64_kernel_unmapped_at_el0()) 3094 return SPECTRE_MITIGATED; 3095 3096 return SPECTRE_VULNERABLE; 3097 } 3098 3099 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3100 char *buf) 3101 { 3102 switch (arm64_get_meltdown_state()) { 3103 case SPECTRE_UNAFFECTED: 3104 return sprintf(buf, "Not affected\n"); 3105 3106 case SPECTRE_MITIGATED: 3107 return sprintf(buf, "Mitigation: PTI\n"); 3108 3109 default: 3110 return sprintf(buf, "Vulnerable\n"); 3111 } 3112 } 3113