1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <linux/percpu.h> 77 78 #include <asm/cpu.h> 79 #include <asm/cpufeature.h> 80 #include <asm/cpu_ops.h> 81 #include <asm/fpsimd.h> 82 #include <asm/insn.h> 83 #include <asm/kvm_host.h> 84 #include <asm/mmu_context.h> 85 #include <asm/mte.h> 86 #include <asm/processor.h> 87 #include <asm/smp.h> 88 #include <asm/sysreg.h> 89 #include <asm/traps.h> 90 #include <asm/vectors.h> 91 #include <asm/virt.h> 92 93 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 94 static unsigned long elf_hwcap __read_mostly; 95 96 #ifdef CONFIG_COMPAT 97 #define COMPAT_ELF_HWCAP_DEFAULT \ 98 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 99 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 100 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 101 COMPAT_HWCAP_LPAE) 102 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 103 unsigned int compat_elf_hwcap2 __read_mostly; 104 #endif 105 106 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 107 EXPORT_SYMBOL(cpu_hwcaps); 108 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 109 110 /* Need also bit for ARM64_CB_PATCH */ 111 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 112 113 bool arm64_use_ng_mappings = false; 114 EXPORT_SYMBOL(arm64_use_ng_mappings); 115 116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 117 118 /* 119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 120 * support it? 121 */ 122 static bool __read_mostly allow_mismatched_32bit_el0; 123 124 /* 125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 126 * seen at least one CPU capable of 32-bit EL0. 127 */ 128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 129 130 /* 131 * Mask of CPUs supporting 32-bit EL0. 132 * Only valid if arm64_mismatched_32bit_el0 is enabled. 133 */ 134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 135 136 /* 137 * Flag to indicate if we have computed the system wide 138 * capabilities based on the boot time active CPUs. This 139 * will be used to determine if a new booting CPU should 140 * go through the verification process to make sure that it 141 * supports the system capabilities, without using a hotplug 142 * notifier. This is also used to decide if we could use 143 * the fast path for checking constant CPU caps. 144 */ 145 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 146 EXPORT_SYMBOL(arm64_const_caps_ready); 147 static inline void finalize_system_capabilities(void) 148 { 149 static_branch_enable(&arm64_const_caps_ready); 150 } 151 152 void dump_cpu_features(void) 153 { 154 /* file-wide pr_fmt adds "CPU features: " prefix */ 155 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 156 } 157 158 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 159 EXPORT_SYMBOL(cpu_hwcap_keys); 160 161 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 162 { \ 163 .sign = SIGNED, \ 164 .visible = VISIBLE, \ 165 .strict = STRICT, \ 166 .type = TYPE, \ 167 .shift = SHIFT, \ 168 .width = WIDTH, \ 169 .safe_val = SAFE_VAL, \ 170 } 171 172 /* Define a feature with unsigned values */ 173 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 174 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 175 176 /* Define a feature with a signed value */ 177 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 178 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 179 180 #define ARM64_FTR_END \ 181 { \ 182 .width = 0, \ 183 } 184 185 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 186 187 static bool __system_matches_cap(unsigned int n); 188 189 /* 190 * NOTE: Any changes to the visibility of features should be kept in 191 * sync with the documentation of the CPU feature register ABI. 192 */ 193 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 208 ARM64_FTR_END, 209 }; 210 211 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 219 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 221 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 226 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 228 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 230 ARM64_FTR_END, 231 }; 232 233 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 236 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 238 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), 240 ARM64_FTR_END, 241 }; 242 243 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 254 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 255 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 260 ARM64_FTR_END, 261 }; 262 263 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SME_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 273 ARM64_FTR_END, 274 }; 275 276 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 292 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 294 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 295 ARM64_FTR_END, 296 }; 297 298 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 300 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_FA64_SHIFT, 1, 0), 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I16I64_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F64F64_SHIFT, 1, 0), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I8I32_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F16F32_SHIFT, 1, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_B16F32_SHIFT, 1, 0), 311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F32F32_SHIFT, 1, 0), 313 ARM64_FTR_END, 314 }; 315 316 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 317 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 320 /* 321 * Page size not being supported at Stage-2 is not fatal. You 322 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 323 * your favourite nesting hypervisor. 324 * 325 * There is a small corner case where the hypervisor explicitly 326 * advertises a given granule size at Stage-2 (value 2) on some 327 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 328 * vCPUs. Although this is not forbidden by the architecture, it 329 * indicates that the hypervisor is being silly (or buggy). 330 * 331 * We make no effort to cope with this and pretend that if these 332 * fields are inconsistent across vCPUs, then it isn't worth 333 * trying to bring KVM up. 334 */ 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 338 /* 339 * We already refuse to boot CPUs that don't support our configured 340 * page size, so we can only detect mismatches for a page size other 341 * than the one we're currently using. Unfortunately, SoCs like this 342 * exist in the wild so, even though we don't like it, we'll have to go 343 * along with it and treat them as non-strict. 344 */ 345 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 346 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 348 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 350 /* Linux shouldn't care about secure memory */ 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 354 /* 355 * Differing PARange is fine as long as all peripherals and memory are mapped 356 * within the minimum PARange of all CPUs 357 */ 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 359 ARM64_FTR_END, 360 }; 361 362 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 363 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 374 ARM64_FTR_END, 375 }; 376 377 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 393 ARM64_FTR_END, 394 }; 395 396 static const struct arm64_ftr_bits ftr_ctr[] = { 397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 403 /* 404 * Linux can handle differing I-cache policies. Userspace JITs will 405 * make use of *minLine. 406 * If we have differing I-cache policies, report it as the weakest - VIPT. 407 */ 408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 410 ARM64_FTR_END, 411 }; 412 413 static struct arm64_ftr_override __ro_after_init no_override = { }; 414 415 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 416 .name = "SYS_CTR_EL0", 417 .ftr_bits = ftr_ctr, 418 .override = &no_override, 419 }; 420 421 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 422 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 427 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 430 ARM64_FTR_END, 431 }; 432 433 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 434 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 439 /* 440 * We can instantiate multiple PMU instances with different levels 441 * of support. 442 */ 443 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 445 ARM64_FTR_END, 446 }; 447 448 static const struct arm64_ftr_bits ftr_mvfr2[] = { 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 451 ARM64_FTR_END, 452 }; 453 454 static const struct arm64_ftr_bits ftr_dczid[] = { 455 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 456 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 457 ARM64_FTR_END, 458 }; 459 460 static const struct arm64_ftr_bits ftr_gmid[] = { 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), 462 ARM64_FTR_END, 463 }; 464 465 static const struct arm64_ftr_bits ftr_id_isar0[] = { 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 473 ARM64_FTR_END, 474 }; 475 476 static const struct arm64_ftr_bits ftr_id_isar5[] = { 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 483 ARM64_FTR_END, 484 }; 485 486 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 494 495 /* 496 * SpecSEI = 1 indicates that the PE might generate an SError on an 497 * external abort on speculative read. It is safe to assume that an 498 * SError might be generated than it will not be. Hence it has been 499 * classified as FTR_HIGHER_SAFE. 500 */ 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 502 ARM64_FTR_END, 503 }; 504 505 static const struct arm64_ftr_bits ftr_id_isar4[] = { 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 514 ARM64_FTR_END, 515 }; 516 517 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 519 ARM64_FTR_END, 520 }; 521 522 static const struct arm64_ftr_bits ftr_id_isar6[] = { 523 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 530 ARM64_FTR_END, 531 }; 532 533 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 540 ARM64_FTR_END, 541 }; 542 543 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 552 ARM64_FTR_END, 553 }; 554 555 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 558 ARM64_FTR_END, 559 }; 560 561 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 562 /* [31:28] TraceFilt */ 563 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 570 ARM64_FTR_END, 571 }; 572 573 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 574 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_zcr[] = { 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 580 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */ 581 ARM64_FTR_END, 582 }; 583 584 static const struct arm64_ftr_bits ftr_smcr[] = { 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 586 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */ 587 ARM64_FTR_END, 588 }; 589 590 /* 591 * Common ftr bits for a 32bit register with all hidden, strict 592 * attributes, with 4bit feature fields and a default safe value of 593 * 0. Covers the following 32bit registers: 594 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 595 */ 596 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 605 ARM64_FTR_END, 606 }; 607 608 /* Table for a single 32bit feature value */ 609 static const struct arm64_ftr_bits ftr_single32[] = { 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 611 ARM64_FTR_END, 612 }; 613 614 static const struct arm64_ftr_bits ftr_raz[] = { 615 ARM64_FTR_END, 616 }; 617 618 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 619 .sys_id = id, \ 620 .reg = &(struct arm64_ftr_reg){ \ 621 .name = id_str, \ 622 .override = (ovr), \ 623 .ftr_bits = &((table)[0]), \ 624 }} 625 626 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 627 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 628 629 #define ARM64_FTR_REG(id, table) \ 630 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 631 632 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 633 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 634 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 635 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 636 637 static const struct __ftr_reg_entry { 638 u32 sys_id; 639 struct arm64_ftr_reg *reg; 640 } arm64_ftr_regs[] = { 641 642 /* Op1 = 0, CRn = 0, CRm = 1 */ 643 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 644 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 645 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 646 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 647 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 648 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 649 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 650 651 /* Op1 = 0, CRn = 0, CRm = 2 */ 652 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 653 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 654 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 655 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 656 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 657 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 658 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 659 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 660 661 /* Op1 = 0, CRn = 0, CRm = 3 */ 662 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 663 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 664 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 665 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 666 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 667 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 668 669 /* Op1 = 0, CRn = 0, CRm = 4 */ 670 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 671 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 672 &id_aa64pfr1_override), 673 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 674 ARM64_FTR_REG(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0), 675 676 /* Op1 = 0, CRn = 0, CRm = 5 */ 677 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 678 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 679 680 /* Op1 = 0, CRn = 0, CRm = 6 */ 681 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 682 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 683 &id_aa64isar1_override), 684 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 685 &id_aa64isar2_override), 686 687 /* Op1 = 0, CRn = 0, CRm = 7 */ 688 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 689 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 690 &id_aa64mmfr1_override), 691 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 692 693 /* Op1 = 0, CRn = 1, CRm = 2 */ 694 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 695 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr), 696 697 /* Op1 = 1, CRn = 0, CRm = 0 */ 698 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 699 700 /* Op1 = 3, CRn = 0, CRm = 0 */ 701 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 702 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 703 704 /* Op1 = 3, CRn = 14, CRm = 0 */ 705 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 706 }; 707 708 static int search_cmp_ftr_reg(const void *id, const void *regp) 709 { 710 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 711 } 712 713 /* 714 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 715 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 716 * ascending order of sys_id, we use binary search to find a matching 717 * entry. 718 * 719 * returns - Upon success, matching ftr_reg entry for id. 720 * - NULL on failure. It is upto the caller to decide 721 * the impact of a failure. 722 */ 723 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 724 { 725 const struct __ftr_reg_entry *ret; 726 727 ret = bsearch((const void *)(unsigned long)sys_id, 728 arm64_ftr_regs, 729 ARRAY_SIZE(arm64_ftr_regs), 730 sizeof(arm64_ftr_regs[0]), 731 search_cmp_ftr_reg); 732 if (ret) 733 return ret->reg; 734 return NULL; 735 } 736 737 /* 738 * get_arm64_ftr_reg - Looks up a feature register entry using 739 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 740 * 741 * returns - Upon success, matching ftr_reg entry for id. 742 * - NULL on failure but with an WARN_ON(). 743 */ 744 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 745 { 746 struct arm64_ftr_reg *reg; 747 748 reg = get_arm64_ftr_reg_nowarn(sys_id); 749 750 /* 751 * Requesting a non-existent register search is an error. Warn 752 * and let the caller handle it. 753 */ 754 WARN_ON(!reg); 755 return reg; 756 } 757 758 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 759 s64 ftr_val) 760 { 761 u64 mask = arm64_ftr_mask(ftrp); 762 763 reg &= ~mask; 764 reg |= (ftr_val << ftrp->shift) & mask; 765 return reg; 766 } 767 768 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 769 s64 cur) 770 { 771 s64 ret = 0; 772 773 switch (ftrp->type) { 774 case FTR_EXACT: 775 ret = ftrp->safe_val; 776 break; 777 case FTR_LOWER_SAFE: 778 ret = min(new, cur); 779 break; 780 case FTR_HIGHER_OR_ZERO_SAFE: 781 if (!cur || !new) 782 break; 783 fallthrough; 784 case FTR_HIGHER_SAFE: 785 ret = max(new, cur); 786 break; 787 default: 788 BUG(); 789 } 790 791 return ret; 792 } 793 794 static void __init sort_ftr_regs(void) 795 { 796 unsigned int i; 797 798 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 799 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 800 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 801 unsigned int j = 0; 802 803 /* 804 * Features here must be sorted in descending order with respect 805 * to their shift values and should not overlap with each other. 806 */ 807 for (; ftr_bits->width != 0; ftr_bits++, j++) { 808 unsigned int width = ftr_reg->ftr_bits[j].width; 809 unsigned int shift = ftr_reg->ftr_bits[j].shift; 810 unsigned int prev_shift; 811 812 WARN((shift + width) > 64, 813 "%s has invalid feature at shift %d\n", 814 ftr_reg->name, shift); 815 816 /* 817 * Skip the first feature. There is nothing to 818 * compare against for now. 819 */ 820 if (j == 0) 821 continue; 822 823 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 824 WARN((shift + width) > prev_shift, 825 "%s has feature overlap at shift %d\n", 826 ftr_reg->name, shift); 827 } 828 829 /* 830 * Skip the first register. There is nothing to 831 * compare against for now. 832 */ 833 if (i == 0) 834 continue; 835 /* 836 * Registers here must be sorted in ascending order with respect 837 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 838 * to work correctly. 839 */ 840 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 841 } 842 } 843 844 /* 845 * Initialise the CPU feature register from Boot CPU values. 846 * Also initiliases the strict_mask for the register. 847 * Any bits that are not covered by an arm64_ftr_bits entry are considered 848 * RES0 for the system-wide value, and must strictly match. 849 */ 850 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 851 { 852 u64 val = 0; 853 u64 strict_mask = ~0x0ULL; 854 u64 user_mask = 0; 855 u64 valid_mask = 0; 856 857 const struct arm64_ftr_bits *ftrp; 858 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 859 860 if (!reg) 861 return; 862 863 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 864 u64 ftr_mask = arm64_ftr_mask(ftrp); 865 s64 ftr_new = arm64_ftr_value(ftrp, new); 866 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 867 868 if ((ftr_mask & reg->override->mask) == ftr_mask) { 869 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 870 char *str = NULL; 871 872 if (ftr_ovr != tmp) { 873 /* Unsafe, remove the override */ 874 reg->override->mask &= ~ftr_mask; 875 reg->override->val &= ~ftr_mask; 876 tmp = ftr_ovr; 877 str = "ignoring override"; 878 } else if (ftr_new != tmp) { 879 /* Override was valid */ 880 ftr_new = tmp; 881 str = "forced"; 882 } else if (ftr_ovr == tmp) { 883 /* Override was the safe value */ 884 str = "already set"; 885 } 886 887 if (str) 888 pr_warn("%s[%d:%d]: %s to %llx\n", 889 reg->name, 890 ftrp->shift + ftrp->width - 1, 891 ftrp->shift, str, tmp); 892 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 893 reg->override->val &= ~ftr_mask; 894 pr_warn("%s[%d:%d]: impossible override, ignored\n", 895 reg->name, 896 ftrp->shift + ftrp->width - 1, 897 ftrp->shift); 898 } 899 900 val = arm64_ftr_set_value(ftrp, val, ftr_new); 901 902 valid_mask |= ftr_mask; 903 if (!ftrp->strict) 904 strict_mask &= ~ftr_mask; 905 if (ftrp->visible) 906 user_mask |= ftr_mask; 907 else 908 reg->user_val = arm64_ftr_set_value(ftrp, 909 reg->user_val, 910 ftrp->safe_val); 911 } 912 913 val &= valid_mask; 914 915 reg->sys_val = val; 916 reg->strict_mask = strict_mask; 917 reg->user_mask = user_mask; 918 } 919 920 extern const struct arm64_cpu_capabilities arm64_errata[]; 921 static const struct arm64_cpu_capabilities arm64_features[]; 922 923 static void __init 924 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 925 { 926 for (; caps->matches; caps++) { 927 if (WARN(caps->capability >= ARM64_NCAPS, 928 "Invalid capability %d\n", caps->capability)) 929 continue; 930 if (WARN(cpu_hwcaps_ptrs[caps->capability], 931 "Duplicate entry for capability %d\n", 932 caps->capability)) 933 continue; 934 cpu_hwcaps_ptrs[caps->capability] = caps; 935 } 936 } 937 938 static void __init init_cpu_hwcaps_indirect_list(void) 939 { 940 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 941 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 942 } 943 944 static void __init setup_boot_cpu_capabilities(void); 945 946 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 947 { 948 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 949 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 950 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 951 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 952 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 953 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 954 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 955 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 956 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 957 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 958 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 959 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 960 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 961 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 962 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 963 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 964 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 965 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 966 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 967 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 968 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 969 } 970 971 void __init init_cpu_features(struct cpuinfo_arm64 *info) 972 { 973 /* Before we start using the tables, make sure it is sorted */ 974 sort_ftr_regs(); 975 976 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 977 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 978 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 979 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 980 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 981 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 982 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 983 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 984 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 985 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 986 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 987 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 988 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 989 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 990 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 991 992 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 993 init_32bit_cpu_features(&info->aarch32); 994 995 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 996 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 997 vec_init_vq_map(ARM64_VEC_SVE); 998 } 999 1000 if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) { 1001 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr); 1002 if (IS_ENABLED(CONFIG_ARM64_SME)) 1003 vec_init_vq_map(ARM64_VEC_SME); 1004 } 1005 1006 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1007 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1008 1009 /* 1010 * Initialize the indirect array of CPU hwcaps capabilities pointers 1011 * before we handle the boot CPU below. 1012 */ 1013 init_cpu_hwcaps_indirect_list(); 1014 1015 /* 1016 * Detect and enable early CPU capabilities based on the boot CPU, 1017 * after we have initialised the CPU feature infrastructure. 1018 */ 1019 setup_boot_cpu_capabilities(); 1020 } 1021 1022 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1023 { 1024 const struct arm64_ftr_bits *ftrp; 1025 1026 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1027 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1028 s64 ftr_new = arm64_ftr_value(ftrp, new); 1029 1030 if (ftr_cur == ftr_new) 1031 continue; 1032 /* Find a safe value */ 1033 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1034 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1035 } 1036 1037 } 1038 1039 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1040 { 1041 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1042 1043 if (!regp) 1044 return 0; 1045 1046 update_cpu_ftr_reg(regp, val); 1047 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1048 return 0; 1049 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1050 regp->name, boot, cpu, val); 1051 return 1; 1052 } 1053 1054 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1055 { 1056 const struct arm64_ftr_bits *ftrp; 1057 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1058 1059 if (!regp) 1060 return; 1061 1062 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1063 if (ftrp->shift == field) { 1064 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1065 break; 1066 } 1067 } 1068 1069 /* Bogus field? */ 1070 WARN_ON(!ftrp->width); 1071 } 1072 1073 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1074 struct cpuinfo_arm64 *boot) 1075 { 1076 static bool boot_cpu_32bit_regs_overridden = false; 1077 1078 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1079 return; 1080 1081 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1082 return; 1083 1084 boot->aarch32 = info->aarch32; 1085 init_32bit_cpu_features(&boot->aarch32); 1086 boot_cpu_32bit_regs_overridden = true; 1087 } 1088 1089 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1090 struct cpuinfo_32bit *boot) 1091 { 1092 int taint = 0; 1093 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1094 1095 /* 1096 * If we don't have AArch32 at EL1, then relax the strictness of 1097 * EL1-dependent register fields to avoid spurious sanity check fails. 1098 */ 1099 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1100 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1101 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1102 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1103 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1104 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1105 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1106 } 1107 1108 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1109 info->reg_id_dfr0, boot->reg_id_dfr0); 1110 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1111 info->reg_id_dfr1, boot->reg_id_dfr1); 1112 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1113 info->reg_id_isar0, boot->reg_id_isar0); 1114 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1115 info->reg_id_isar1, boot->reg_id_isar1); 1116 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1117 info->reg_id_isar2, boot->reg_id_isar2); 1118 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1119 info->reg_id_isar3, boot->reg_id_isar3); 1120 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1121 info->reg_id_isar4, boot->reg_id_isar4); 1122 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1123 info->reg_id_isar5, boot->reg_id_isar5); 1124 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1125 info->reg_id_isar6, boot->reg_id_isar6); 1126 1127 /* 1128 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1129 * ACTLR formats could differ across CPUs and therefore would have to 1130 * be trapped for virtualization anyway. 1131 */ 1132 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1133 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1134 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1135 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1136 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1137 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1138 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1139 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1140 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1141 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1142 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1143 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1144 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1145 info->reg_id_pfr0, boot->reg_id_pfr0); 1146 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1147 info->reg_id_pfr1, boot->reg_id_pfr1); 1148 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1149 info->reg_id_pfr2, boot->reg_id_pfr2); 1150 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1151 info->reg_mvfr0, boot->reg_mvfr0); 1152 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1153 info->reg_mvfr1, boot->reg_mvfr1); 1154 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1155 info->reg_mvfr2, boot->reg_mvfr2); 1156 1157 return taint; 1158 } 1159 1160 /* 1161 * Update system wide CPU feature registers with the values from a 1162 * non-boot CPU. Also performs SANITY checks to make sure that there 1163 * aren't any insane variations from that of the boot CPU. 1164 */ 1165 void update_cpu_features(int cpu, 1166 struct cpuinfo_arm64 *info, 1167 struct cpuinfo_arm64 *boot) 1168 { 1169 int taint = 0; 1170 1171 /* 1172 * The kernel can handle differing I-cache policies, but otherwise 1173 * caches should look identical. Userspace JITs will make use of 1174 * *minLine. 1175 */ 1176 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1177 info->reg_ctr, boot->reg_ctr); 1178 1179 /* 1180 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1181 * could result in too much or too little memory being zeroed if a 1182 * process is preempted and migrated between CPUs. 1183 */ 1184 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1185 info->reg_dczid, boot->reg_dczid); 1186 1187 /* If different, timekeeping will be broken (especially with KVM) */ 1188 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1189 info->reg_cntfrq, boot->reg_cntfrq); 1190 1191 /* 1192 * The kernel uses self-hosted debug features and expects CPUs to 1193 * support identical debug features. We presently need CTX_CMPs, WRPs, 1194 * and BRPs to be identical. 1195 * ID_AA64DFR1 is currently RES0. 1196 */ 1197 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1198 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1199 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1200 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1201 /* 1202 * Even in big.LITTLE, processors should be identical instruction-set 1203 * wise. 1204 */ 1205 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1206 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1207 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1208 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1209 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1210 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1211 1212 /* 1213 * Differing PARange support is fine as long as all peripherals and 1214 * memory are mapped within the minimum PARange of all CPUs. 1215 * Linux should not care about secure memory. 1216 */ 1217 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1218 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1219 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1220 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1221 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1222 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1223 1224 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1225 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1226 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1227 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1228 1229 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1230 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1231 1232 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1233 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1234 1235 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1236 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1237 info->reg_zcr, boot->reg_zcr); 1238 1239 /* Probe vector lengths, unless we already gave up on SVE */ 1240 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1241 !system_capabilities_finalized()) 1242 vec_update_vq_map(ARM64_VEC_SVE); 1243 } 1244 1245 if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) { 1246 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu, 1247 info->reg_smcr, boot->reg_smcr); 1248 1249 /* Probe vector lengths, unless we already gave up on SME */ 1250 if (id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1)) && 1251 !system_capabilities_finalized()) 1252 vec_update_vq_map(ARM64_VEC_SME); 1253 } 1254 1255 /* 1256 * The kernel uses the LDGM/STGM instructions and the number of tags 1257 * they read/write depends on the GMID_EL1.BS field. Check that the 1258 * value is the same on all CPUs. 1259 */ 1260 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1261 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1262 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1263 info->reg_gmid, boot->reg_gmid); 1264 } 1265 1266 /* 1267 * If we don't have AArch32 at all then skip the checks entirely 1268 * as the register values may be UNKNOWN and we're not going to be 1269 * using them for anything. 1270 * 1271 * This relies on a sanitised view of the AArch64 ID registers 1272 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1273 */ 1274 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1275 lazy_init_32bit_cpu_features(info, boot); 1276 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1277 &boot->aarch32); 1278 } 1279 1280 /* 1281 * Mismatched CPU features are a recipe for disaster. Don't even 1282 * pretend to support them. 1283 */ 1284 if (taint) { 1285 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1286 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1287 } 1288 } 1289 1290 u64 read_sanitised_ftr_reg(u32 id) 1291 { 1292 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1293 1294 if (!regp) 1295 return 0; 1296 return regp->sys_val; 1297 } 1298 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1299 1300 #define read_sysreg_case(r) \ 1301 case r: val = read_sysreg_s(r); break; 1302 1303 /* 1304 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1305 * Read the system register on the current CPU 1306 */ 1307 u64 __read_sysreg_by_encoding(u32 sys_id) 1308 { 1309 struct arm64_ftr_reg *regp; 1310 u64 val; 1311 1312 switch (sys_id) { 1313 read_sysreg_case(SYS_ID_PFR0_EL1); 1314 read_sysreg_case(SYS_ID_PFR1_EL1); 1315 read_sysreg_case(SYS_ID_PFR2_EL1); 1316 read_sysreg_case(SYS_ID_DFR0_EL1); 1317 read_sysreg_case(SYS_ID_DFR1_EL1); 1318 read_sysreg_case(SYS_ID_MMFR0_EL1); 1319 read_sysreg_case(SYS_ID_MMFR1_EL1); 1320 read_sysreg_case(SYS_ID_MMFR2_EL1); 1321 read_sysreg_case(SYS_ID_MMFR3_EL1); 1322 read_sysreg_case(SYS_ID_MMFR4_EL1); 1323 read_sysreg_case(SYS_ID_MMFR5_EL1); 1324 read_sysreg_case(SYS_ID_ISAR0_EL1); 1325 read_sysreg_case(SYS_ID_ISAR1_EL1); 1326 read_sysreg_case(SYS_ID_ISAR2_EL1); 1327 read_sysreg_case(SYS_ID_ISAR3_EL1); 1328 read_sysreg_case(SYS_ID_ISAR4_EL1); 1329 read_sysreg_case(SYS_ID_ISAR5_EL1); 1330 read_sysreg_case(SYS_ID_ISAR6_EL1); 1331 read_sysreg_case(SYS_MVFR0_EL1); 1332 read_sysreg_case(SYS_MVFR1_EL1); 1333 read_sysreg_case(SYS_MVFR2_EL1); 1334 1335 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1336 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1337 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1338 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1339 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1340 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1341 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1342 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1343 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1344 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1345 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1346 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1347 1348 read_sysreg_case(SYS_CNTFRQ_EL0); 1349 read_sysreg_case(SYS_CTR_EL0); 1350 read_sysreg_case(SYS_DCZID_EL0); 1351 1352 default: 1353 BUG(); 1354 return 0; 1355 } 1356 1357 regp = get_arm64_ftr_reg(sys_id); 1358 if (regp) { 1359 val &= ~regp->override->mask; 1360 val |= (regp->override->val & regp->override->mask); 1361 } 1362 1363 return val; 1364 } 1365 1366 #include <linux/irqchip/arm-gic-v3.h> 1367 1368 static bool 1369 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1370 { 1371 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1372 entry->field_width, 1373 entry->sign); 1374 1375 return val >= entry->min_field_value; 1376 } 1377 1378 static bool 1379 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1380 { 1381 u64 val; 1382 1383 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1384 if (scope == SCOPE_SYSTEM) 1385 val = read_sanitised_ftr_reg(entry->sys_reg); 1386 else 1387 val = __read_sysreg_by_encoding(entry->sys_reg); 1388 1389 return feature_matches(val, entry); 1390 } 1391 1392 const struct cpumask *system_32bit_el0_cpumask(void) 1393 { 1394 if (!system_supports_32bit_el0()) 1395 return cpu_none_mask; 1396 1397 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1398 return cpu_32bit_el0_mask; 1399 1400 return cpu_possible_mask; 1401 } 1402 1403 static int __init parse_32bit_el0_param(char *str) 1404 { 1405 allow_mismatched_32bit_el0 = true; 1406 return 0; 1407 } 1408 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1409 1410 static ssize_t aarch32_el0_show(struct device *dev, 1411 struct device_attribute *attr, char *buf) 1412 { 1413 const struct cpumask *mask = system_32bit_el0_cpumask(); 1414 1415 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1416 } 1417 static const DEVICE_ATTR_RO(aarch32_el0); 1418 1419 static int __init aarch32_el0_sysfs_init(void) 1420 { 1421 if (!allow_mismatched_32bit_el0) 1422 return 0; 1423 1424 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1425 } 1426 device_initcall(aarch32_el0_sysfs_init); 1427 1428 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1429 { 1430 if (!has_cpuid_feature(entry, scope)) 1431 return allow_mismatched_32bit_el0; 1432 1433 if (scope == SCOPE_SYSTEM) 1434 pr_info("detected: 32-bit EL0 Support\n"); 1435 1436 return true; 1437 } 1438 1439 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1440 { 1441 bool has_sre; 1442 1443 if (!has_cpuid_feature(entry, scope)) 1444 return false; 1445 1446 has_sre = gic_enable_sre(); 1447 if (!has_sre) 1448 pr_warn_once("%s present but disabled by higher exception level\n", 1449 entry->desc); 1450 1451 return has_sre; 1452 } 1453 1454 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1455 { 1456 u32 midr = read_cpuid_id(); 1457 1458 /* Cavium ThunderX pass 1.x and 2.x */ 1459 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1460 MIDR_CPU_VAR_REV(0, 0), 1461 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1462 } 1463 1464 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1465 { 1466 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1467 1468 return cpuid_feature_extract_signed_field(pfr0, 1469 ID_AA64PFR0_FP_SHIFT) < 0; 1470 } 1471 1472 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1473 int scope) 1474 { 1475 u64 ctr; 1476 1477 if (scope == SCOPE_SYSTEM) 1478 ctr = arm64_ftr_reg_ctrel0.sys_val; 1479 else 1480 ctr = read_cpuid_effective_cachetype(); 1481 1482 return ctr & BIT(CTR_IDC_SHIFT); 1483 } 1484 1485 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1486 { 1487 /* 1488 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1489 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1490 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1491 * value. 1492 */ 1493 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1494 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1495 } 1496 1497 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1498 int scope) 1499 { 1500 u64 ctr; 1501 1502 if (scope == SCOPE_SYSTEM) 1503 ctr = arm64_ftr_reg_ctrel0.sys_val; 1504 else 1505 ctr = read_cpuid_cachetype(); 1506 1507 return ctr & BIT(CTR_DIC_SHIFT); 1508 } 1509 1510 static bool __maybe_unused 1511 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1512 { 1513 /* 1514 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1515 * may share TLB entries with a CPU stuck in the crashed 1516 * kernel. 1517 */ 1518 if (is_kdump_kernel()) 1519 return false; 1520 1521 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1522 return false; 1523 1524 return has_cpuid_feature(entry, scope); 1525 } 1526 1527 /* 1528 * This check is triggered during the early boot before the cpufeature 1529 * is initialised. Checking the status on the local CPU allows the boot 1530 * CPU to detect the need for non-global mappings and thus avoiding a 1531 * pagetable re-write after all the CPUs are booted. This check will be 1532 * anyway run on individual CPUs, allowing us to get the consistent 1533 * state once the SMP CPUs are up and thus make the switch to non-global 1534 * mappings if required. 1535 */ 1536 bool kaslr_requires_kpti(void) 1537 { 1538 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1539 return false; 1540 1541 /* 1542 * E0PD does a similar job to KPTI so can be used instead 1543 * where available. 1544 */ 1545 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1546 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1547 if (cpuid_feature_extract_unsigned_field(mmfr2, 1548 ID_AA64MMFR2_E0PD_SHIFT)) 1549 return false; 1550 } 1551 1552 /* 1553 * Systems affected by Cavium erratum 24756 are incompatible 1554 * with KPTI. 1555 */ 1556 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1557 extern const struct midr_range cavium_erratum_27456_cpus[]; 1558 1559 if (is_midr_in_range_list(read_cpuid_id(), 1560 cavium_erratum_27456_cpus)) 1561 return false; 1562 } 1563 1564 return kaslr_offset() > 0; 1565 } 1566 1567 static bool __meltdown_safe = true; 1568 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1569 1570 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1571 int scope) 1572 { 1573 /* List of CPUs that are not vulnerable and don't need KPTI */ 1574 static const struct midr_range kpti_safe_list[] = { 1575 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1576 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1577 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1578 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1579 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1580 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1581 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1582 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1583 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1584 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1585 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1586 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1587 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1588 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1589 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1590 { /* sentinel */ } 1591 }; 1592 char const *str = "kpti command line option"; 1593 bool meltdown_safe; 1594 1595 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1596 1597 /* Defer to CPU feature registers */ 1598 if (has_cpuid_feature(entry, scope)) 1599 meltdown_safe = true; 1600 1601 if (!meltdown_safe) 1602 __meltdown_safe = false; 1603 1604 /* 1605 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1606 * ThunderX leads to apparent I-cache corruption of kernel text, which 1607 * ends as well as you might imagine. Don't even try. We cannot rely 1608 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1609 * because cpucap detection order may change. However, since we know 1610 * affected CPUs are always in a homogeneous configuration, it is 1611 * safe to rely on this_cpu_has_cap() here. 1612 */ 1613 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1614 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1615 __kpti_forced = -1; 1616 } 1617 1618 /* Useful for KASLR robustness */ 1619 if (kaslr_requires_kpti()) { 1620 if (!__kpti_forced) { 1621 str = "KASLR"; 1622 __kpti_forced = 1; 1623 } 1624 } 1625 1626 if (cpu_mitigations_off() && !__kpti_forced) { 1627 str = "mitigations=off"; 1628 __kpti_forced = -1; 1629 } 1630 1631 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1632 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1633 return false; 1634 } 1635 1636 /* Forced? */ 1637 if (__kpti_forced) { 1638 pr_info_once("kernel page table isolation forced %s by %s\n", 1639 __kpti_forced > 0 ? "ON" : "OFF", str); 1640 return __kpti_forced > 0; 1641 } 1642 1643 return !meltdown_safe; 1644 } 1645 1646 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1647 static void __nocfi 1648 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1649 { 1650 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1651 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1652 kpti_remap_fn *remap_fn; 1653 1654 int cpu = smp_processor_id(); 1655 1656 if (__this_cpu_read(this_cpu_vector) == vectors) { 1657 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1658 1659 __this_cpu_write(this_cpu_vector, v); 1660 } 1661 1662 /* 1663 * We don't need to rewrite the page-tables if either we've done 1664 * it already or we have KASLR enabled and therefore have not 1665 * created any global mappings at all. 1666 */ 1667 if (arm64_use_ng_mappings) 1668 return; 1669 1670 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings)); 1671 1672 cpu_install_idmap(); 1673 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1674 cpu_uninstall_idmap(); 1675 1676 if (!cpu) 1677 arm64_use_ng_mappings = true; 1678 } 1679 #else 1680 static void 1681 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1682 { 1683 } 1684 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1685 1686 static int __init parse_kpti(char *str) 1687 { 1688 bool enabled; 1689 int ret = strtobool(str, &enabled); 1690 1691 if (ret) 1692 return ret; 1693 1694 __kpti_forced = enabled ? 1 : -1; 1695 return 0; 1696 } 1697 early_param("kpti", parse_kpti); 1698 1699 #ifdef CONFIG_ARM64_HW_AFDBM 1700 static inline void __cpu_enable_hw_dbm(void) 1701 { 1702 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1703 1704 write_sysreg(tcr, tcr_el1); 1705 isb(); 1706 local_flush_tlb_all(); 1707 } 1708 1709 static bool cpu_has_broken_dbm(void) 1710 { 1711 /* List of CPUs which have broken DBM support. */ 1712 static const struct midr_range cpus[] = { 1713 #ifdef CONFIG_ARM64_ERRATUM_1024718 1714 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1715 /* Kryo4xx Silver (rdpe => r1p0) */ 1716 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1717 #endif 1718 #ifdef CONFIG_ARM64_ERRATUM_2051678 1719 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1720 #endif 1721 {}, 1722 }; 1723 1724 return is_midr_in_range_list(read_cpuid_id(), cpus); 1725 } 1726 1727 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1728 { 1729 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1730 !cpu_has_broken_dbm(); 1731 } 1732 1733 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1734 { 1735 if (cpu_can_use_dbm(cap)) 1736 __cpu_enable_hw_dbm(); 1737 } 1738 1739 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1740 int __unused) 1741 { 1742 static bool detected = false; 1743 /* 1744 * DBM is a non-conflicting feature. i.e, the kernel can safely 1745 * run a mix of CPUs with and without the feature. So, we 1746 * unconditionally enable the capability to allow any late CPU 1747 * to use the feature. We only enable the control bits on the 1748 * CPU, if it actually supports. 1749 * 1750 * We have to make sure we print the "feature" detection only 1751 * when at least one CPU actually uses it. So check if this CPU 1752 * can actually use it and print the message exactly once. 1753 * 1754 * This is safe as all CPUs (including secondary CPUs - due to the 1755 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1756 * goes through the "matches" check exactly once. Also if a CPU 1757 * matches the criteria, it is guaranteed that the CPU will turn 1758 * the DBM on, as the capability is unconditionally enabled. 1759 */ 1760 if (!detected && cpu_can_use_dbm(cap)) { 1761 detected = true; 1762 pr_info("detected: Hardware dirty bit management\n"); 1763 } 1764 1765 return true; 1766 } 1767 1768 #endif 1769 1770 #ifdef CONFIG_ARM64_AMU_EXTN 1771 1772 /* 1773 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1774 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1775 * information regarding all the events that it supports. When a CPU bit is 1776 * set in the cpumask, the user of this feature can only rely on the presence 1777 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1778 * counters are enabled or access to these counters is enabled by code 1779 * executed at higher exception levels (firmware). 1780 */ 1781 static struct cpumask amu_cpus __read_mostly; 1782 1783 bool cpu_has_amu_feat(int cpu) 1784 { 1785 return cpumask_test_cpu(cpu, &amu_cpus); 1786 } 1787 1788 int get_cpu_with_amu_feat(void) 1789 { 1790 return cpumask_any(&amu_cpus); 1791 } 1792 1793 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1794 { 1795 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1796 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1797 smp_processor_id()); 1798 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1799 update_freq_counters_refs(); 1800 } 1801 } 1802 1803 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1804 int __unused) 1805 { 1806 /* 1807 * The AMU extension is a non-conflicting feature: the kernel can 1808 * safely run a mix of CPUs with and without support for the 1809 * activity monitors extension. Therefore, unconditionally enable 1810 * the capability to allow any late CPU to use the feature. 1811 * 1812 * With this feature unconditionally enabled, the cpu_enable 1813 * function will be called for all CPUs that match the criteria, 1814 * including secondary and hotplugged, marking this feature as 1815 * present on that respective CPU. The enable function will also 1816 * print a detection message. 1817 */ 1818 1819 return true; 1820 } 1821 #else 1822 int get_cpu_with_amu_feat(void) 1823 { 1824 return nr_cpu_ids; 1825 } 1826 #endif 1827 1828 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1829 { 1830 return is_kernel_in_hyp_mode(); 1831 } 1832 1833 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1834 { 1835 /* 1836 * Copy register values that aren't redirected by hardware. 1837 * 1838 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1839 * this value to tpidr_el2 before we patch the code. Once we've done 1840 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1841 * do anything here. 1842 */ 1843 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1844 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1845 } 1846 1847 #ifdef CONFIG_ARM64_PAN 1848 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1849 { 1850 /* 1851 * We modify PSTATE. This won't work from irq context as the PSTATE 1852 * is discarded once we return from the exception. 1853 */ 1854 WARN_ON_ONCE(in_interrupt()); 1855 1856 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1857 set_pstate_pan(1); 1858 } 1859 #endif /* CONFIG_ARM64_PAN */ 1860 1861 #ifdef CONFIG_ARM64_RAS_EXTN 1862 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1863 { 1864 /* Firmware may have left a deferred SError in this register. */ 1865 write_sysreg_s(0, SYS_DISR_EL1); 1866 } 1867 #endif /* CONFIG_ARM64_RAS_EXTN */ 1868 1869 #ifdef CONFIG_ARM64_PTR_AUTH 1870 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1871 { 1872 int boot_val, sec_val; 1873 1874 /* We don't expect to be called with SCOPE_SYSTEM */ 1875 WARN_ON(scope == SCOPE_SYSTEM); 1876 /* 1877 * The ptr-auth feature levels are not intercompatible with lower 1878 * levels. Hence we must match ptr-auth feature level of the secondary 1879 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1880 * from the sanitised register whereas direct register read is done for 1881 * the secondary CPUs. 1882 * The sanitised feature state is guaranteed to match that of the 1883 * boot CPU as a mismatched secondary CPU is parked before it gets 1884 * a chance to update the state, with the capability. 1885 */ 1886 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1887 entry->field_pos, entry->sign); 1888 if (scope & SCOPE_BOOT_CPU) 1889 return boot_val >= entry->min_field_value; 1890 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1891 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1892 entry->field_pos, entry->sign); 1893 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 1894 } 1895 1896 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1897 int scope) 1898 { 1899 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1900 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 1901 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 1902 1903 return apa || apa3 || api; 1904 } 1905 1906 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1907 int __unused) 1908 { 1909 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1910 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 1911 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 1912 1913 return gpa || gpa3 || gpi; 1914 } 1915 #endif /* CONFIG_ARM64_PTR_AUTH */ 1916 1917 #ifdef CONFIG_ARM64_E0PD 1918 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1919 { 1920 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1921 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1922 } 1923 #endif /* CONFIG_ARM64_E0PD */ 1924 1925 #ifdef CONFIG_ARM64_PSEUDO_NMI 1926 static bool enable_pseudo_nmi; 1927 1928 static int __init early_enable_pseudo_nmi(char *p) 1929 { 1930 return strtobool(p, &enable_pseudo_nmi); 1931 } 1932 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1933 1934 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1935 int scope) 1936 { 1937 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1938 } 1939 #endif 1940 1941 #ifdef CONFIG_ARM64_BTI 1942 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1943 { 1944 /* 1945 * Use of X16/X17 for tail-calls and trampolines that jump to 1946 * function entry points using BR is a requirement for 1947 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1948 * So, be strict and forbid other BRs using other registers to 1949 * jump onto a PACIxSP instruction: 1950 */ 1951 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1952 isb(); 1953 } 1954 #endif /* CONFIG_ARM64_BTI */ 1955 1956 #ifdef CONFIG_ARM64_MTE 1957 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1958 { 1959 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 1960 isb(); 1961 1962 /* 1963 * Clear the tags in the zero page. This needs to be done via the 1964 * linear map which has the Tagged attribute. 1965 */ 1966 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1967 mte_clear_page_tags(lm_alias(empty_zero_page)); 1968 1969 kasan_init_hw_tags_cpu(); 1970 } 1971 #endif /* CONFIG_ARM64_MTE */ 1972 1973 #ifdef CONFIG_KVM 1974 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1975 { 1976 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1977 return false; 1978 1979 if (is_kernel_in_hyp_mode()) { 1980 pr_warn("Protected KVM not available with VHE\n"); 1981 return false; 1982 } 1983 1984 return true; 1985 } 1986 #endif /* CONFIG_KVM */ 1987 1988 /* Internal helper functions to match cpu capability type */ 1989 static bool 1990 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1991 { 1992 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1993 } 1994 1995 static bool 1996 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1997 { 1998 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1999 } 2000 2001 static bool 2002 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2003 { 2004 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2005 } 2006 2007 static const struct arm64_cpu_capabilities arm64_features[] = { 2008 { 2009 .desc = "GIC system register CPU interface", 2010 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 2011 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2012 .matches = has_useable_gicv3_cpuif, 2013 .sys_reg = SYS_ID_AA64PFR0_EL1, 2014 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2015 .field_width = 4, 2016 .sign = FTR_UNSIGNED, 2017 .min_field_value = 1, 2018 }, 2019 { 2020 .desc = "Enhanced Counter Virtualization", 2021 .capability = ARM64_HAS_ECV, 2022 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2023 .matches = has_cpuid_feature, 2024 .sys_reg = SYS_ID_AA64MMFR0_EL1, 2025 .field_pos = ID_AA64MMFR0_ECV_SHIFT, 2026 .field_width = 4, 2027 .sign = FTR_UNSIGNED, 2028 .min_field_value = 1, 2029 }, 2030 #ifdef CONFIG_ARM64_PAN 2031 { 2032 .desc = "Privileged Access Never", 2033 .capability = ARM64_HAS_PAN, 2034 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2035 .matches = has_cpuid_feature, 2036 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2037 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 2038 .field_width = 4, 2039 .sign = FTR_UNSIGNED, 2040 .min_field_value = 1, 2041 .cpu_enable = cpu_enable_pan, 2042 }, 2043 #endif /* CONFIG_ARM64_PAN */ 2044 #ifdef CONFIG_ARM64_EPAN 2045 { 2046 .desc = "Enhanced Privileged Access Never", 2047 .capability = ARM64_HAS_EPAN, 2048 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2049 .matches = has_cpuid_feature, 2050 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2051 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 2052 .field_width = 4, 2053 .sign = FTR_UNSIGNED, 2054 .min_field_value = 3, 2055 }, 2056 #endif /* CONFIG_ARM64_EPAN */ 2057 #ifdef CONFIG_ARM64_LSE_ATOMICS 2058 { 2059 .desc = "LSE atomic instructions", 2060 .capability = ARM64_HAS_LSE_ATOMICS, 2061 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2062 .matches = has_cpuid_feature, 2063 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2064 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 2065 .field_width = 4, 2066 .sign = FTR_UNSIGNED, 2067 .min_field_value = 2, 2068 }, 2069 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2070 { 2071 .desc = "Software prefetching using PRFM", 2072 .capability = ARM64_HAS_NO_HW_PREFETCH, 2073 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2074 .matches = has_no_hw_prefetch, 2075 }, 2076 { 2077 .desc = "Virtualization Host Extensions", 2078 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2079 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2080 .matches = runs_at_el2, 2081 .cpu_enable = cpu_copy_el2regs, 2082 }, 2083 { 2084 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2085 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2086 .matches = has_32bit_el0, 2087 .sys_reg = SYS_ID_AA64PFR0_EL1, 2088 .sign = FTR_UNSIGNED, 2089 .field_pos = ID_AA64PFR0_EL0_SHIFT, 2090 .field_width = 4, 2091 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2092 }, 2093 #ifdef CONFIG_KVM 2094 { 2095 .desc = "32-bit EL1 Support", 2096 .capability = ARM64_HAS_32BIT_EL1, 2097 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2098 .matches = has_cpuid_feature, 2099 .sys_reg = SYS_ID_AA64PFR0_EL1, 2100 .sign = FTR_UNSIGNED, 2101 .field_pos = ID_AA64PFR0_EL1_SHIFT, 2102 .field_width = 4, 2103 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2104 }, 2105 { 2106 .desc = "Protected KVM", 2107 .capability = ARM64_KVM_PROTECTED_MODE, 2108 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2109 .matches = is_kvm_protected_mode, 2110 }, 2111 #endif 2112 { 2113 .desc = "Kernel page table isolation (KPTI)", 2114 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2115 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2116 /* 2117 * The ID feature fields below are used to indicate that 2118 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2119 * more details. 2120 */ 2121 .sys_reg = SYS_ID_AA64PFR0_EL1, 2122 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 2123 .field_width = 4, 2124 .min_field_value = 1, 2125 .matches = unmap_kernel_at_el0, 2126 .cpu_enable = kpti_install_ng_mappings, 2127 }, 2128 { 2129 /* FP/SIMD is not implemented */ 2130 .capability = ARM64_HAS_NO_FPSIMD, 2131 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2132 .min_field_value = 0, 2133 .matches = has_no_fpsimd, 2134 }, 2135 #ifdef CONFIG_ARM64_PMEM 2136 { 2137 .desc = "Data cache clean to Point of Persistence", 2138 .capability = ARM64_HAS_DCPOP, 2139 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2140 .matches = has_cpuid_feature, 2141 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2142 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2143 .field_width = 4, 2144 .min_field_value = 1, 2145 }, 2146 { 2147 .desc = "Data cache clean to Point of Deep Persistence", 2148 .capability = ARM64_HAS_DCPODP, 2149 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2150 .matches = has_cpuid_feature, 2151 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2152 .sign = FTR_UNSIGNED, 2153 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2154 .field_width = 4, 2155 .min_field_value = 2, 2156 }, 2157 #endif 2158 #ifdef CONFIG_ARM64_SVE 2159 { 2160 .desc = "Scalable Vector Extension", 2161 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2162 .capability = ARM64_SVE, 2163 .sys_reg = SYS_ID_AA64PFR0_EL1, 2164 .sign = FTR_UNSIGNED, 2165 .field_pos = ID_AA64PFR0_SVE_SHIFT, 2166 .field_width = 4, 2167 .min_field_value = ID_AA64PFR0_SVE, 2168 .matches = has_cpuid_feature, 2169 .cpu_enable = sve_kernel_enable, 2170 }, 2171 #endif /* CONFIG_ARM64_SVE */ 2172 #ifdef CONFIG_ARM64_RAS_EXTN 2173 { 2174 .desc = "RAS Extension Support", 2175 .capability = ARM64_HAS_RAS_EXTN, 2176 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2177 .matches = has_cpuid_feature, 2178 .sys_reg = SYS_ID_AA64PFR0_EL1, 2179 .sign = FTR_UNSIGNED, 2180 .field_pos = ID_AA64PFR0_RAS_SHIFT, 2181 .field_width = 4, 2182 .min_field_value = ID_AA64PFR0_RAS_V1, 2183 .cpu_enable = cpu_clear_disr, 2184 }, 2185 #endif /* CONFIG_ARM64_RAS_EXTN */ 2186 #ifdef CONFIG_ARM64_AMU_EXTN 2187 { 2188 /* 2189 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2190 * Therefore, don't provide .desc as we don't want the detection 2191 * message to be shown until at least one CPU is detected to 2192 * support the feature. 2193 */ 2194 .capability = ARM64_HAS_AMU_EXTN, 2195 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2196 .matches = has_amu, 2197 .sys_reg = SYS_ID_AA64PFR0_EL1, 2198 .sign = FTR_UNSIGNED, 2199 .field_pos = ID_AA64PFR0_AMU_SHIFT, 2200 .field_width = 4, 2201 .min_field_value = ID_AA64PFR0_AMU, 2202 .cpu_enable = cpu_amu_enable, 2203 }, 2204 #endif /* CONFIG_ARM64_AMU_EXTN */ 2205 { 2206 .desc = "Data cache clean to the PoU not required for I/D coherence", 2207 .capability = ARM64_HAS_CACHE_IDC, 2208 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2209 .matches = has_cache_idc, 2210 .cpu_enable = cpu_emulate_effective_ctr, 2211 }, 2212 { 2213 .desc = "Instruction cache invalidation not required for I/D coherence", 2214 .capability = ARM64_HAS_CACHE_DIC, 2215 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2216 .matches = has_cache_dic, 2217 }, 2218 { 2219 .desc = "Stage-2 Force Write-Back", 2220 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2221 .capability = ARM64_HAS_STAGE2_FWB, 2222 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2223 .sign = FTR_UNSIGNED, 2224 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 2225 .field_width = 4, 2226 .min_field_value = 1, 2227 .matches = has_cpuid_feature, 2228 }, 2229 { 2230 .desc = "ARMv8.4 Translation Table Level", 2231 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2232 .capability = ARM64_HAS_ARMv8_4_TTL, 2233 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2234 .sign = FTR_UNSIGNED, 2235 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2236 .field_width = 4, 2237 .min_field_value = 1, 2238 .matches = has_cpuid_feature, 2239 }, 2240 { 2241 .desc = "TLB range maintenance instructions", 2242 .capability = ARM64_HAS_TLB_RANGE, 2243 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2244 .matches = has_cpuid_feature, 2245 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2246 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT, 2247 .field_width = 4, 2248 .sign = FTR_UNSIGNED, 2249 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE, 2250 }, 2251 #ifdef CONFIG_ARM64_HW_AFDBM 2252 { 2253 /* 2254 * Since we turn this on always, we don't want the user to 2255 * think that the feature is available when it may not be. 2256 * So hide the description. 2257 * 2258 * .desc = "Hardware pagetable Dirty Bit Management", 2259 * 2260 */ 2261 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2262 .capability = ARM64_HW_DBM, 2263 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2264 .sign = FTR_UNSIGNED, 2265 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2266 .field_width = 4, 2267 .min_field_value = 2, 2268 .matches = has_hw_dbm, 2269 .cpu_enable = cpu_enable_hw_dbm, 2270 }, 2271 #endif 2272 { 2273 .desc = "CRC32 instructions", 2274 .capability = ARM64_HAS_CRC32, 2275 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2276 .matches = has_cpuid_feature, 2277 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2278 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT, 2279 .field_width = 4, 2280 .min_field_value = 1, 2281 }, 2282 { 2283 .desc = "Speculative Store Bypassing Safe (SSBS)", 2284 .capability = ARM64_SSBS, 2285 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2286 .matches = has_cpuid_feature, 2287 .sys_reg = SYS_ID_AA64PFR1_EL1, 2288 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2289 .field_width = 4, 2290 .sign = FTR_UNSIGNED, 2291 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2292 }, 2293 #ifdef CONFIG_ARM64_CNP 2294 { 2295 .desc = "Common not Private translations", 2296 .capability = ARM64_HAS_CNP, 2297 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2298 .matches = has_useable_cnp, 2299 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2300 .sign = FTR_UNSIGNED, 2301 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2302 .field_width = 4, 2303 .min_field_value = 1, 2304 .cpu_enable = cpu_enable_cnp, 2305 }, 2306 #endif 2307 { 2308 .desc = "Speculation barrier (SB)", 2309 .capability = ARM64_HAS_SB, 2310 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2311 .matches = has_cpuid_feature, 2312 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2313 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2314 .field_width = 4, 2315 .sign = FTR_UNSIGNED, 2316 .min_field_value = 1, 2317 }, 2318 #ifdef CONFIG_ARM64_PTR_AUTH 2319 { 2320 .desc = "Address authentication (architected QARMA5 algorithm)", 2321 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2322 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2323 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2324 .sign = FTR_UNSIGNED, 2325 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2326 .field_width = 4, 2327 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2328 .matches = has_address_auth_cpucap, 2329 }, 2330 { 2331 .desc = "Address authentication (architected QARMA3 algorithm)", 2332 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2333 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2334 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2335 .sign = FTR_UNSIGNED, 2336 .field_pos = ID_AA64ISAR2_APA3_SHIFT, 2337 .field_width = 4, 2338 .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED, 2339 .matches = has_address_auth_cpucap, 2340 }, 2341 { 2342 .desc = "Address authentication (IMP DEF algorithm)", 2343 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2344 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2345 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2346 .sign = FTR_UNSIGNED, 2347 .field_pos = ID_AA64ISAR1_API_SHIFT, 2348 .field_width = 4, 2349 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2350 .matches = has_address_auth_cpucap, 2351 }, 2352 { 2353 .capability = ARM64_HAS_ADDRESS_AUTH, 2354 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2355 .matches = has_address_auth_metacap, 2356 }, 2357 { 2358 .desc = "Generic authentication (architected QARMA5 algorithm)", 2359 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2360 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2361 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2362 .sign = FTR_UNSIGNED, 2363 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2364 .field_width = 4, 2365 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2366 .matches = has_cpuid_feature, 2367 }, 2368 { 2369 .desc = "Generic authentication (architected QARMA3 algorithm)", 2370 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2371 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2372 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2373 .sign = FTR_UNSIGNED, 2374 .field_pos = ID_AA64ISAR2_GPA3_SHIFT, 2375 .field_width = 4, 2376 .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED, 2377 .matches = has_cpuid_feature, 2378 }, 2379 { 2380 .desc = "Generic authentication (IMP DEF algorithm)", 2381 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2382 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2383 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2384 .sign = FTR_UNSIGNED, 2385 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2386 .field_width = 4, 2387 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2388 .matches = has_cpuid_feature, 2389 }, 2390 { 2391 .capability = ARM64_HAS_GENERIC_AUTH, 2392 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2393 .matches = has_generic_auth, 2394 }, 2395 #endif /* CONFIG_ARM64_PTR_AUTH */ 2396 #ifdef CONFIG_ARM64_PSEUDO_NMI 2397 { 2398 /* 2399 * Depends on having GICv3 2400 */ 2401 .desc = "IRQ priority masking", 2402 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2403 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2404 .matches = can_use_gic_priorities, 2405 .sys_reg = SYS_ID_AA64PFR0_EL1, 2406 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2407 .field_width = 4, 2408 .sign = FTR_UNSIGNED, 2409 .min_field_value = 1, 2410 }, 2411 #endif 2412 #ifdef CONFIG_ARM64_E0PD 2413 { 2414 .desc = "E0PD", 2415 .capability = ARM64_HAS_E0PD, 2416 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2417 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2418 .sign = FTR_UNSIGNED, 2419 .field_width = 4, 2420 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2421 .matches = has_cpuid_feature, 2422 .min_field_value = 1, 2423 .cpu_enable = cpu_enable_e0pd, 2424 }, 2425 #endif 2426 #ifdef CONFIG_ARCH_RANDOM 2427 { 2428 .desc = "Random Number Generator", 2429 .capability = ARM64_HAS_RNG, 2430 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2431 .matches = has_cpuid_feature, 2432 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2433 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT, 2434 .field_width = 4, 2435 .sign = FTR_UNSIGNED, 2436 .min_field_value = 1, 2437 }, 2438 #endif 2439 #ifdef CONFIG_ARM64_BTI 2440 { 2441 .desc = "Branch Target Identification", 2442 .capability = ARM64_BTI, 2443 #ifdef CONFIG_ARM64_BTI_KERNEL 2444 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2445 #else 2446 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2447 #endif 2448 .matches = has_cpuid_feature, 2449 .cpu_enable = bti_enable, 2450 .sys_reg = SYS_ID_AA64PFR1_EL1, 2451 .field_pos = ID_AA64PFR1_BT_SHIFT, 2452 .field_width = 4, 2453 .min_field_value = ID_AA64PFR1_BT_BTI, 2454 .sign = FTR_UNSIGNED, 2455 }, 2456 #endif 2457 #ifdef CONFIG_ARM64_MTE 2458 { 2459 .desc = "Memory Tagging Extension", 2460 .capability = ARM64_MTE, 2461 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2462 .matches = has_cpuid_feature, 2463 .sys_reg = SYS_ID_AA64PFR1_EL1, 2464 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2465 .field_width = 4, 2466 .min_field_value = ID_AA64PFR1_MTE, 2467 .sign = FTR_UNSIGNED, 2468 .cpu_enable = cpu_enable_mte, 2469 }, 2470 { 2471 .desc = "Asymmetric MTE Tag Check Fault", 2472 .capability = ARM64_MTE_ASYMM, 2473 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2474 .matches = has_cpuid_feature, 2475 .sys_reg = SYS_ID_AA64PFR1_EL1, 2476 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2477 .field_width = 4, 2478 .min_field_value = ID_AA64PFR1_MTE_ASYMM, 2479 .sign = FTR_UNSIGNED, 2480 }, 2481 #endif /* CONFIG_ARM64_MTE */ 2482 { 2483 .desc = "RCpc load-acquire (LDAPR)", 2484 .capability = ARM64_HAS_LDAPR, 2485 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2486 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2487 .sign = FTR_UNSIGNED, 2488 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2489 .field_width = 4, 2490 .matches = has_cpuid_feature, 2491 .min_field_value = 1, 2492 }, 2493 #ifdef CONFIG_ARM64_SME 2494 { 2495 .desc = "Scalable Matrix Extension", 2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2497 .capability = ARM64_SME, 2498 .sys_reg = SYS_ID_AA64PFR1_EL1, 2499 .sign = FTR_UNSIGNED, 2500 .field_pos = ID_AA64PFR1_SME_SHIFT, 2501 .field_width = 4, 2502 .min_field_value = ID_AA64PFR1_SME, 2503 .matches = has_cpuid_feature, 2504 .cpu_enable = sme_kernel_enable, 2505 }, 2506 /* FA64 should be sorted after the base SME capability */ 2507 { 2508 .desc = "FA64", 2509 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2510 .capability = ARM64_SME_FA64, 2511 .sys_reg = SYS_ID_AA64SMFR0_EL1, 2512 .sign = FTR_UNSIGNED, 2513 .field_pos = ID_AA64SMFR0_FA64_SHIFT, 2514 .field_width = 1, 2515 .min_field_value = ID_AA64SMFR0_FA64, 2516 .matches = has_cpuid_feature, 2517 .cpu_enable = fa64_kernel_enable, 2518 }, 2519 #endif /* CONFIG_ARM64_SME */ 2520 {}, 2521 }; 2522 2523 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2524 .matches = has_cpuid_feature, \ 2525 .sys_reg = reg, \ 2526 .field_pos = field, \ 2527 .field_width = width, \ 2528 .sign = s, \ 2529 .min_field_value = min_value, 2530 2531 #define __HWCAP_CAP(name, cap_type, cap) \ 2532 .desc = name, \ 2533 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2534 .hwcap_type = cap_type, \ 2535 .hwcap = cap, \ 2536 2537 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \ 2538 { \ 2539 __HWCAP_CAP(#cap, cap_type, cap) \ 2540 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2541 } 2542 2543 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2544 { \ 2545 __HWCAP_CAP(#cap, cap_type, cap) \ 2546 .matches = cpucap_multi_entry_cap_matches, \ 2547 .match_list = list, \ 2548 } 2549 2550 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2551 { \ 2552 __HWCAP_CAP(#cap, cap_type, cap) \ 2553 .matches = match, \ 2554 } 2555 2556 #ifdef CONFIG_ARM64_PTR_AUTH 2557 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2558 { 2559 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2560 4, FTR_UNSIGNED, 2561 ID_AA64ISAR1_APA_ARCHITECTED) 2562 }, 2563 { 2564 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, 2565 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED) 2566 }, 2567 { 2568 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2569 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2570 }, 2571 {}, 2572 }; 2573 2574 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2575 { 2576 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2577 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2578 }, 2579 { 2580 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, 2581 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED) 2582 }, 2583 { 2584 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2585 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2586 }, 2587 {}, 2588 }; 2589 #endif 2590 2591 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2592 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2593 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2594 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2595 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2596 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2597 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2598 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2599 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2600 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2601 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2602 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2603 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2604 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2605 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2606 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2607 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2608 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2609 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2610 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2611 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2612 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2613 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2614 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2615 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2616 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2617 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2618 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2619 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2620 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2621 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2622 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2623 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2624 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2625 #ifdef CONFIG_ARM64_SVE 2626 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2627 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2628 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2629 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2630 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2631 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2632 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2633 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2634 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2635 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2636 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2637 #endif 2638 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2639 #ifdef CONFIG_ARM64_BTI 2640 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2641 #endif 2642 #ifdef CONFIG_ARM64_PTR_AUTH 2643 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2644 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2645 #endif 2646 #ifdef CONFIG_ARM64_MTE 2647 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2648 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2649 #endif /* CONFIG_ARM64_MTE */ 2650 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2651 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2652 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2653 #ifdef CONFIG_ARM64_SME 2654 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), 2655 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2656 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I16I64, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2657 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F64F64, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2658 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I8I32, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2659 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F16F32, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2660 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_B16F32, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2661 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F32F32, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2662 #endif /* CONFIG_ARM64_SME */ 2663 {}, 2664 }; 2665 2666 #ifdef CONFIG_COMPAT 2667 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2668 { 2669 /* 2670 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2671 * in line with that of arm32 as in vfp_init(). We make sure that the 2672 * check is future proof, by making sure value is non-zero. 2673 */ 2674 u32 mvfr1; 2675 2676 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2677 if (scope == SCOPE_SYSTEM) 2678 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2679 else 2680 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2681 2682 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2683 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2684 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2685 } 2686 #endif 2687 2688 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2689 #ifdef CONFIG_COMPAT 2690 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2691 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2692 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2693 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2694 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2695 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2696 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2697 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2698 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2699 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2700 #endif 2701 {}, 2702 }; 2703 2704 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2705 { 2706 switch (cap->hwcap_type) { 2707 case CAP_HWCAP: 2708 cpu_set_feature(cap->hwcap); 2709 break; 2710 #ifdef CONFIG_COMPAT 2711 case CAP_COMPAT_HWCAP: 2712 compat_elf_hwcap |= (u32)cap->hwcap; 2713 break; 2714 case CAP_COMPAT_HWCAP2: 2715 compat_elf_hwcap2 |= (u32)cap->hwcap; 2716 break; 2717 #endif 2718 default: 2719 WARN_ON(1); 2720 break; 2721 } 2722 } 2723 2724 /* Check if we have a particular HWCAP enabled */ 2725 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2726 { 2727 bool rc; 2728 2729 switch (cap->hwcap_type) { 2730 case CAP_HWCAP: 2731 rc = cpu_have_feature(cap->hwcap); 2732 break; 2733 #ifdef CONFIG_COMPAT 2734 case CAP_COMPAT_HWCAP: 2735 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2736 break; 2737 case CAP_COMPAT_HWCAP2: 2738 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2739 break; 2740 #endif 2741 default: 2742 WARN_ON(1); 2743 rc = false; 2744 } 2745 2746 return rc; 2747 } 2748 2749 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2750 { 2751 /* We support emulation of accesses to CPU ID feature registers */ 2752 cpu_set_named_feature(CPUID); 2753 for (; hwcaps->matches; hwcaps++) 2754 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2755 cap_set_elf_hwcap(hwcaps); 2756 } 2757 2758 static void update_cpu_capabilities(u16 scope_mask) 2759 { 2760 int i; 2761 const struct arm64_cpu_capabilities *caps; 2762 2763 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2764 for (i = 0; i < ARM64_NCAPS; i++) { 2765 caps = cpu_hwcaps_ptrs[i]; 2766 if (!caps || !(caps->type & scope_mask) || 2767 cpus_have_cap(caps->capability) || 2768 !caps->matches(caps, cpucap_default_scope(caps))) 2769 continue; 2770 2771 if (caps->desc) 2772 pr_info("detected: %s\n", caps->desc); 2773 cpus_set_cap(caps->capability); 2774 2775 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2776 set_bit(caps->capability, boot_capabilities); 2777 } 2778 } 2779 2780 /* 2781 * Enable all the available capabilities on this CPU. The capabilities 2782 * with BOOT_CPU scope are handled separately and hence skipped here. 2783 */ 2784 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2785 { 2786 int i; 2787 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2788 2789 for_each_available_cap(i) { 2790 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2791 2792 if (WARN_ON(!cap)) 2793 continue; 2794 2795 if (!(cap->type & non_boot_scope)) 2796 continue; 2797 2798 if (cap->cpu_enable) 2799 cap->cpu_enable(cap); 2800 } 2801 return 0; 2802 } 2803 2804 /* 2805 * Run through the enabled capabilities and enable() it on all active 2806 * CPUs 2807 */ 2808 static void __init enable_cpu_capabilities(u16 scope_mask) 2809 { 2810 int i; 2811 const struct arm64_cpu_capabilities *caps; 2812 bool boot_scope; 2813 2814 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2815 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2816 2817 for (i = 0; i < ARM64_NCAPS; i++) { 2818 unsigned int num; 2819 2820 caps = cpu_hwcaps_ptrs[i]; 2821 if (!caps || !(caps->type & scope_mask)) 2822 continue; 2823 num = caps->capability; 2824 if (!cpus_have_cap(num)) 2825 continue; 2826 2827 /* Ensure cpus_have_const_cap(num) works */ 2828 static_branch_enable(&cpu_hwcap_keys[num]); 2829 2830 if (boot_scope && caps->cpu_enable) 2831 /* 2832 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2833 * before any secondary CPU boots. Thus, each secondary 2834 * will enable the capability as appropriate via 2835 * check_local_cpu_capabilities(). The only exception is 2836 * the boot CPU, for which the capability must be 2837 * enabled here. This approach avoids costly 2838 * stop_machine() calls for this case. 2839 */ 2840 caps->cpu_enable(caps); 2841 } 2842 2843 /* 2844 * For all non-boot scope capabilities, use stop_machine() 2845 * as it schedules the work allowing us to modify PSTATE, 2846 * instead of on_each_cpu() which uses an IPI, giving us a 2847 * PSTATE that disappears when we return. 2848 */ 2849 if (!boot_scope) 2850 stop_machine(cpu_enable_non_boot_scope_capabilities, 2851 NULL, cpu_online_mask); 2852 } 2853 2854 /* 2855 * Run through the list of capabilities to check for conflicts. 2856 * If the system has already detected a capability, take necessary 2857 * action on this CPU. 2858 */ 2859 static void verify_local_cpu_caps(u16 scope_mask) 2860 { 2861 int i; 2862 bool cpu_has_cap, system_has_cap; 2863 const struct arm64_cpu_capabilities *caps; 2864 2865 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2866 2867 for (i = 0; i < ARM64_NCAPS; i++) { 2868 caps = cpu_hwcaps_ptrs[i]; 2869 if (!caps || !(caps->type & scope_mask)) 2870 continue; 2871 2872 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2873 system_has_cap = cpus_have_cap(caps->capability); 2874 2875 if (system_has_cap) { 2876 /* 2877 * Check if the new CPU misses an advertised feature, 2878 * which is not safe to miss. 2879 */ 2880 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2881 break; 2882 /* 2883 * We have to issue cpu_enable() irrespective of 2884 * whether the CPU has it or not, as it is enabeld 2885 * system wide. It is upto the call back to take 2886 * appropriate action on this CPU. 2887 */ 2888 if (caps->cpu_enable) 2889 caps->cpu_enable(caps); 2890 } else { 2891 /* 2892 * Check if the CPU has this capability if it isn't 2893 * safe to have when the system doesn't. 2894 */ 2895 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2896 break; 2897 } 2898 } 2899 2900 if (i < ARM64_NCAPS) { 2901 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2902 smp_processor_id(), caps->capability, 2903 caps->desc, system_has_cap, cpu_has_cap); 2904 2905 if (cpucap_panic_on_conflict(caps)) 2906 cpu_panic_kernel(); 2907 else 2908 cpu_die_early(); 2909 } 2910 } 2911 2912 /* 2913 * Check for CPU features that are used in early boot 2914 * based on the Boot CPU value. 2915 */ 2916 static void check_early_cpu_features(void) 2917 { 2918 verify_cpu_asid_bits(); 2919 2920 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2921 } 2922 2923 static void 2924 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2925 { 2926 2927 for (; caps->matches; caps++) 2928 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2929 pr_crit("CPU%d: missing HWCAP: %s\n", 2930 smp_processor_id(), caps->desc); 2931 cpu_die_early(); 2932 } 2933 } 2934 2935 static void verify_local_elf_hwcaps(void) 2936 { 2937 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 2938 2939 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 2940 __verify_local_elf_hwcaps(compat_elf_hwcaps); 2941 } 2942 2943 static void verify_sve_features(void) 2944 { 2945 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2946 u64 zcr = read_zcr_features(); 2947 2948 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2949 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2950 2951 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 2952 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2953 smp_processor_id()); 2954 cpu_die_early(); 2955 } 2956 2957 /* Add checks on other ZCR bits here if necessary */ 2958 } 2959 2960 static void verify_sme_features(void) 2961 { 2962 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 2963 u64 smcr = read_smcr_features(); 2964 2965 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK; 2966 unsigned int len = smcr & SMCR_ELx_LEN_MASK; 2967 2968 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) { 2969 pr_crit("CPU%d: SME: vector length support mismatch\n", 2970 smp_processor_id()); 2971 cpu_die_early(); 2972 } 2973 2974 /* Add checks on other SMCR bits here if necessary */ 2975 } 2976 2977 static void verify_hyp_capabilities(void) 2978 { 2979 u64 safe_mmfr1, mmfr0, mmfr1; 2980 int parange, ipa_max; 2981 unsigned int safe_vmid_bits, vmid_bits; 2982 2983 if (!IS_ENABLED(CONFIG_KVM)) 2984 return; 2985 2986 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2987 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2988 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2989 2990 /* Verify VMID bits */ 2991 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2992 vmid_bits = get_vmid_bits(mmfr1); 2993 if (vmid_bits < safe_vmid_bits) { 2994 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2995 cpu_die_early(); 2996 } 2997 2998 /* Verify IPA range */ 2999 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3000 ID_AA64MMFR0_PARANGE_SHIFT); 3001 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3002 if (ipa_max < get_kvm_ipa_limit()) { 3003 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3004 cpu_die_early(); 3005 } 3006 } 3007 3008 /* 3009 * Run through the enabled system capabilities and enable() it on this CPU. 3010 * The capabilities were decided based on the available CPUs at the boot time. 3011 * Any new CPU should match the system wide status of the capability. If the 3012 * new CPU doesn't have a capability which the system now has enabled, we 3013 * cannot do anything to fix it up and could cause unexpected failures. So 3014 * we park the CPU. 3015 */ 3016 static void verify_local_cpu_capabilities(void) 3017 { 3018 /* 3019 * The capabilities with SCOPE_BOOT_CPU are checked from 3020 * check_early_cpu_features(), as they need to be verified 3021 * on all secondary CPUs. 3022 */ 3023 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3024 verify_local_elf_hwcaps(); 3025 3026 if (system_supports_sve()) 3027 verify_sve_features(); 3028 3029 if (system_supports_sme()) 3030 verify_sme_features(); 3031 3032 if (is_hyp_mode_available()) 3033 verify_hyp_capabilities(); 3034 } 3035 3036 void check_local_cpu_capabilities(void) 3037 { 3038 /* 3039 * All secondary CPUs should conform to the early CPU features 3040 * in use by the kernel based on boot CPU. 3041 */ 3042 check_early_cpu_features(); 3043 3044 /* 3045 * If we haven't finalised the system capabilities, this CPU gets 3046 * a chance to update the errata work arounds and local features. 3047 * Otherwise, this CPU should verify that it has all the system 3048 * advertised capabilities. 3049 */ 3050 if (!system_capabilities_finalized()) 3051 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3052 else 3053 verify_local_cpu_capabilities(); 3054 } 3055 3056 static void __init setup_boot_cpu_capabilities(void) 3057 { 3058 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3059 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3060 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3061 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3062 } 3063 3064 bool this_cpu_has_cap(unsigned int n) 3065 { 3066 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3067 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3068 3069 if (cap) 3070 return cap->matches(cap, SCOPE_LOCAL_CPU); 3071 } 3072 3073 return false; 3074 } 3075 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3076 3077 /* 3078 * This helper function is used in a narrow window when, 3079 * - The system wide safe registers are set with all the SMP CPUs and, 3080 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 3081 * In all other cases cpus_have_{const_}cap() should be used. 3082 */ 3083 static bool __maybe_unused __system_matches_cap(unsigned int n) 3084 { 3085 if (n < ARM64_NCAPS) { 3086 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3087 3088 if (cap) 3089 return cap->matches(cap, SCOPE_SYSTEM); 3090 } 3091 return false; 3092 } 3093 3094 void cpu_set_feature(unsigned int num) 3095 { 3096 WARN_ON(num >= MAX_CPU_FEATURES); 3097 elf_hwcap |= BIT(num); 3098 } 3099 EXPORT_SYMBOL_GPL(cpu_set_feature); 3100 3101 bool cpu_have_feature(unsigned int num) 3102 { 3103 WARN_ON(num >= MAX_CPU_FEATURES); 3104 return elf_hwcap & BIT(num); 3105 } 3106 EXPORT_SYMBOL_GPL(cpu_have_feature); 3107 3108 unsigned long cpu_get_elf_hwcap(void) 3109 { 3110 /* 3111 * We currently only populate the first 32 bits of AT_HWCAP. Please 3112 * note that for userspace compatibility we guarantee that bits 62 3113 * and 63 will always be returned as 0. 3114 */ 3115 return lower_32_bits(elf_hwcap); 3116 } 3117 3118 unsigned long cpu_get_elf_hwcap2(void) 3119 { 3120 return upper_32_bits(elf_hwcap); 3121 } 3122 3123 static void __init setup_system_capabilities(void) 3124 { 3125 /* 3126 * We have finalised the system-wide safe feature 3127 * registers, finalise the capabilities that depend 3128 * on it. Also enable all the available capabilities, 3129 * that are not enabled already. 3130 */ 3131 update_cpu_capabilities(SCOPE_SYSTEM); 3132 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3133 } 3134 3135 void __init setup_cpu_features(void) 3136 { 3137 u32 cwg; 3138 3139 setup_system_capabilities(); 3140 setup_elf_hwcaps(arm64_elf_hwcaps); 3141 3142 if (system_supports_32bit_el0()) 3143 setup_elf_hwcaps(compat_elf_hwcaps); 3144 3145 if (system_uses_ttbr0_pan()) 3146 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3147 3148 sve_setup(); 3149 sme_setup(); 3150 minsigstksz_setup(); 3151 3152 /* Advertise that we have computed the system capabilities */ 3153 finalize_system_capabilities(); 3154 3155 /* 3156 * Check for sane CTR_EL0.CWG value. 3157 */ 3158 cwg = cache_type_cwg(); 3159 if (!cwg) 3160 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3161 ARCH_DMA_MINALIGN); 3162 } 3163 3164 static int enable_mismatched_32bit_el0(unsigned int cpu) 3165 { 3166 /* 3167 * The first 32-bit-capable CPU we detected and so can no longer 3168 * be offlined by userspace. -1 indicates we haven't yet onlined 3169 * a 32-bit-capable CPU. 3170 */ 3171 static int lucky_winner = -1; 3172 3173 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3174 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3175 3176 if (cpu_32bit) { 3177 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3178 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3179 } 3180 3181 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3182 return 0; 3183 3184 if (lucky_winner >= 0) 3185 return 0; 3186 3187 /* 3188 * We've detected a mismatch. We need to keep one of our CPUs with 3189 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3190 * every CPU in the system for a 32-bit task. 3191 */ 3192 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3193 cpu_active_mask); 3194 get_cpu_device(lucky_winner)->offline_disabled = true; 3195 setup_elf_hwcaps(compat_elf_hwcaps); 3196 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3197 cpu, lucky_winner); 3198 return 0; 3199 } 3200 3201 static int __init init_32bit_el0_mask(void) 3202 { 3203 if (!allow_mismatched_32bit_el0) 3204 return 0; 3205 3206 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3207 return -ENOMEM; 3208 3209 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3210 "arm64/mismatched_32bit_el0:online", 3211 enable_mismatched_32bit_el0, NULL); 3212 } 3213 subsys_initcall_sync(init_32bit_el0_mask); 3214 3215 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3216 { 3217 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 3218 } 3219 3220 /* 3221 * We emulate only the following system register space. 3222 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 3223 * See Table C5-6 System instruction encodings for System register accesses, 3224 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3225 */ 3226 static inline bool __attribute_const__ is_emulated(u32 id) 3227 { 3228 return (sys_reg_Op0(id) == 0x3 && 3229 sys_reg_CRn(id) == 0x0 && 3230 sys_reg_Op1(id) == 0x0 && 3231 (sys_reg_CRm(id) == 0 || 3232 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 3233 } 3234 3235 /* 3236 * With CRm == 0, reg should be one of : 3237 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3238 */ 3239 static inline int emulate_id_reg(u32 id, u64 *valp) 3240 { 3241 switch (id) { 3242 case SYS_MIDR_EL1: 3243 *valp = read_cpuid_id(); 3244 break; 3245 case SYS_MPIDR_EL1: 3246 *valp = SYS_MPIDR_SAFE_VAL; 3247 break; 3248 case SYS_REVIDR_EL1: 3249 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3250 *valp = 0; 3251 break; 3252 default: 3253 return -EINVAL; 3254 } 3255 3256 return 0; 3257 } 3258 3259 static int emulate_sys_reg(u32 id, u64 *valp) 3260 { 3261 struct arm64_ftr_reg *regp; 3262 3263 if (!is_emulated(id)) 3264 return -EINVAL; 3265 3266 if (sys_reg_CRm(id) == 0) 3267 return emulate_id_reg(id, valp); 3268 3269 regp = get_arm64_ftr_reg_nowarn(id); 3270 if (regp) 3271 *valp = arm64_ftr_reg_user_value(regp); 3272 else 3273 /* 3274 * The untracked registers are either IMPLEMENTATION DEFINED 3275 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3276 */ 3277 *valp = 0; 3278 return 0; 3279 } 3280 3281 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3282 { 3283 int rc; 3284 u64 val; 3285 3286 rc = emulate_sys_reg(sys_reg, &val); 3287 if (!rc) { 3288 pt_regs_write_reg(regs, rt, val); 3289 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3290 } 3291 return rc; 3292 } 3293 3294 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3295 { 3296 u32 sys_reg, rt; 3297 3298 /* 3299 * sys_reg values are defined as used in mrs/msr instruction. 3300 * shift the imm value to get the encoding. 3301 */ 3302 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3303 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3304 return do_emulate_mrs(regs, sys_reg, rt); 3305 } 3306 3307 static struct undef_hook mrs_hook = { 3308 .instr_mask = 0xffff0000, 3309 .instr_val = 0xd5380000, 3310 .pstate_mask = PSR_AA32_MODE_MASK, 3311 .pstate_val = PSR_MODE_EL0t, 3312 .fn = emulate_mrs, 3313 }; 3314 3315 static int __init enable_mrs_emulation(void) 3316 { 3317 register_undef_hook(&mrs_hook); 3318 return 0; 3319 } 3320 3321 core_initcall(enable_mrs_emulation); 3322 3323 enum mitigation_state arm64_get_meltdown_state(void) 3324 { 3325 if (__meltdown_safe) 3326 return SPECTRE_UNAFFECTED; 3327 3328 if (arm64_kernel_unmapped_at_el0()) 3329 return SPECTRE_MITIGATED; 3330 3331 return SPECTRE_VULNERABLE; 3332 } 3333 3334 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3335 char *buf) 3336 { 3337 switch (arm64_get_meltdown_state()) { 3338 case SPECTRE_UNAFFECTED: 3339 return sprintf(buf, "Not affected\n"); 3340 3341 case SPECTRE_MITIGATED: 3342 return sprintf(buf, "Mitigation: PTI\n"); 3343 3344 default: 3345 return sprintf(buf, "Vulnerable\n"); 3346 } 3347 } 3348