1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/mm.h> 72 #include <linux/cpu.h> 73 #include <linux/kasan.h> 74 #include <asm/cpu.h> 75 #include <asm/cpufeature.h> 76 #include <asm/cpu_ops.h> 77 #include <asm/fpsimd.h> 78 #include <asm/kvm_host.h> 79 #include <asm/mmu_context.h> 80 #include <asm/mte.h> 81 #include <asm/processor.h> 82 #include <asm/sysreg.h> 83 #include <asm/traps.h> 84 #include <asm/virt.h> 85 86 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 87 static unsigned long elf_hwcap __read_mostly; 88 89 #ifdef CONFIG_COMPAT 90 #define COMPAT_ELF_HWCAP_DEFAULT \ 91 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 92 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 93 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 94 COMPAT_HWCAP_LPAE) 95 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 96 unsigned int compat_elf_hwcap2 __read_mostly; 97 #endif 98 99 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 100 EXPORT_SYMBOL(cpu_hwcaps); 101 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 102 103 /* Need also bit for ARM64_CB_PATCH */ 104 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 105 106 bool arm64_use_ng_mappings = false; 107 EXPORT_SYMBOL(arm64_use_ng_mappings); 108 109 /* 110 * Flag to indicate if we have computed the system wide 111 * capabilities based on the boot time active CPUs. This 112 * will be used to determine if a new booting CPU should 113 * go through the verification process to make sure that it 114 * supports the system capabilities, without using a hotplug 115 * notifier. This is also used to decide if we could use 116 * the fast path for checking constant CPU caps. 117 */ 118 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 119 EXPORT_SYMBOL(arm64_const_caps_ready); 120 static inline void finalize_system_capabilities(void) 121 { 122 static_branch_enable(&arm64_const_caps_ready); 123 } 124 125 void dump_cpu_features(void) 126 { 127 /* file-wide pr_fmt adds "CPU features: " prefix */ 128 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 129 } 130 131 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 132 EXPORT_SYMBOL(cpu_hwcap_keys); 133 134 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 135 { \ 136 .sign = SIGNED, \ 137 .visible = VISIBLE, \ 138 .strict = STRICT, \ 139 .type = TYPE, \ 140 .shift = SHIFT, \ 141 .width = WIDTH, \ 142 .safe_val = SAFE_VAL, \ 143 } 144 145 /* Define a feature with unsigned values */ 146 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 147 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 148 149 /* Define a feature with a signed value */ 150 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 152 153 #define ARM64_FTR_END \ 154 { \ 155 .width = 0, \ 156 } 157 158 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 159 160 static bool __system_matches_cap(unsigned int n); 161 162 /* 163 * NOTE: Any changes to the visibility of features should be kept in 164 * sync with the documentation of the CPU feature register ABI. 165 */ 166 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 181 ARM64_FTR_END, 182 }; 183 184 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 192 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 194 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 199 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 201 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 203 ARM64_FTR_END, 204 }; 205 206 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 217 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 218 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 223 ARM64_FTR_END, 224 }; 225 226 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 230 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 232 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 233 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 234 ARM64_FTR_END, 235 }; 236 237 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 256 ARM64_FTR_END, 257 }; 258 259 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 263 /* 264 * Page size not being supported at Stage-2 is not fatal. You 265 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 266 * your favourite nesting hypervisor. 267 * 268 * There is a small corner case where the hypervisor explicitly 269 * advertises a given granule size at Stage-2 (value 2) on some 270 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 271 * vCPUs. Although this is not forbidden by the architecture, it 272 * indicates that the hypervisor is being silly (or buggy). 273 * 274 * We make no effort to cope with this and pretend that if these 275 * fields are inconsistent across vCPUs, then it isn't worth 276 * trying to bring KVM up. 277 */ 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 281 /* 282 * We already refuse to boot CPUs that don't support our configured 283 * page size, so we can only detect mismatches for a page size other 284 * than the one we're currently using. Unfortunately, SoCs like this 285 * exist in the wild so, even though we don't like it, we'll have to go 286 * along with it and treat them as non-strict. 287 */ 288 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 289 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 291 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 293 /* Linux shouldn't care about secure memory */ 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 297 /* 298 * Differing PARange is fine as long as all peripherals and memory are mapped 299 * within the minimum PARange of all CPUs 300 */ 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 316 ARM64_FTR_END, 317 }; 318 319 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_ctr[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 345 /* 346 * Linux can handle differing I-cache policies. Userspace JITs will 347 * make use of *minLine. 348 * If we have differing I-cache policies, report it as the weakest - VIPT. 349 */ 350 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 352 ARM64_FTR_END, 353 }; 354 355 static struct arm64_ftr_override __ro_after_init no_override = { }; 356 357 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 358 .name = "SYS_CTR_EL0", 359 .ftr_bits = ftr_ctr, 360 .override = &no_override, 361 }; 362 363 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 364 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 369 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 372 ARM64_FTR_END, 373 }; 374 375 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 376 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 381 /* 382 * We can instantiate multiple PMU instances with different levels 383 * of support. 384 */ 385 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 388 ARM64_FTR_END, 389 }; 390 391 static const struct arm64_ftr_bits ftr_mvfr2[] = { 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 394 ARM64_FTR_END, 395 }; 396 397 static const struct arm64_ftr_bits ftr_dczid[] = { 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 400 ARM64_FTR_END, 401 }; 402 403 static const struct arm64_ftr_bits ftr_id_isar0[] = { 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 411 ARM64_FTR_END, 412 }; 413 414 static const struct arm64_ftr_bits ftr_id_isar5[] = { 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 421 ARM64_FTR_END, 422 }; 423 424 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 432 433 /* 434 * SpecSEI = 1 indicates that the PE might generate an SError on an 435 * external abort on speculative read. It is safe to assume that an 436 * SError might be generated than it will not be. Hence it has been 437 * classified as FTR_HIGHER_SAFE. 438 */ 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 440 ARM64_FTR_END, 441 }; 442 443 static const struct arm64_ftr_bits ftr_id_isar4[] = { 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 452 ARM64_FTR_END, 453 }; 454 455 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 457 ARM64_FTR_END, 458 }; 459 460 static const struct arm64_ftr_bits ftr_id_isar6[] = { 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 468 ARM64_FTR_END, 469 }; 470 471 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 490 ARM64_FTR_END, 491 }; 492 493 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 496 ARM64_FTR_END, 497 }; 498 499 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 500 /* [31:28] TraceFilt */ 501 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 508 ARM64_FTR_END, 509 }; 510 511 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 512 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 513 ARM64_FTR_END, 514 }; 515 516 static const struct arm64_ftr_bits ftr_zcr[] = { 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 518 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 519 ARM64_FTR_END, 520 }; 521 522 /* 523 * Common ftr bits for a 32bit register with all hidden, strict 524 * attributes, with 4bit feature fields and a default safe value of 525 * 0. Covers the following 32bit registers: 526 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 527 */ 528 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 537 ARM64_FTR_END, 538 }; 539 540 /* Table for a single 32bit feature value */ 541 static const struct arm64_ftr_bits ftr_single32[] = { 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 543 ARM64_FTR_END, 544 }; 545 546 static const struct arm64_ftr_bits ftr_raz[] = { 547 ARM64_FTR_END, 548 }; 549 550 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \ 551 .sys_id = id, \ 552 .reg = &(struct arm64_ftr_reg){ \ 553 .name = #id, \ 554 .override = (ovr), \ 555 .ftr_bits = &((table)[0]), \ 556 }} 557 558 #define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override) 559 560 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 561 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 562 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 563 564 static const struct __ftr_reg_entry { 565 u32 sys_id; 566 struct arm64_ftr_reg *reg; 567 } arm64_ftr_regs[] = { 568 569 /* Op1 = 0, CRn = 0, CRm = 1 */ 570 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 571 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 572 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 573 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 574 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 575 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 576 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 577 578 /* Op1 = 0, CRn = 0, CRm = 2 */ 579 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 580 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 581 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 582 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 583 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 584 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 585 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 586 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 587 588 /* Op1 = 0, CRn = 0, CRm = 3 */ 589 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 590 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 591 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 592 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 593 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 594 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 595 596 /* Op1 = 0, CRn = 0, CRm = 4 */ 597 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 598 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 599 &id_aa64pfr1_override), 600 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 601 602 /* Op1 = 0, CRn = 0, CRm = 5 */ 603 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 604 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 605 606 /* Op1 = 0, CRn = 0, CRm = 6 */ 607 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 608 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 609 &id_aa64isar1_override), 610 611 /* Op1 = 0, CRn = 0, CRm = 7 */ 612 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 613 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 614 &id_aa64mmfr1_override), 615 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 616 617 /* Op1 = 0, CRn = 1, CRm = 2 */ 618 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 619 620 /* Op1 = 3, CRn = 0, CRm = 0 */ 621 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 622 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 623 624 /* Op1 = 3, CRn = 14, CRm = 0 */ 625 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 626 }; 627 628 static int search_cmp_ftr_reg(const void *id, const void *regp) 629 { 630 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 631 } 632 633 /* 634 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 635 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 636 * ascending order of sys_id, we use binary search to find a matching 637 * entry. 638 * 639 * returns - Upon success, matching ftr_reg entry for id. 640 * - NULL on failure. It is upto the caller to decide 641 * the impact of a failure. 642 */ 643 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 644 { 645 const struct __ftr_reg_entry *ret; 646 647 ret = bsearch((const void *)(unsigned long)sys_id, 648 arm64_ftr_regs, 649 ARRAY_SIZE(arm64_ftr_regs), 650 sizeof(arm64_ftr_regs[0]), 651 search_cmp_ftr_reg); 652 if (ret) 653 return ret->reg; 654 return NULL; 655 } 656 657 /* 658 * get_arm64_ftr_reg - Looks up a feature register entry using 659 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 660 * 661 * returns - Upon success, matching ftr_reg entry for id. 662 * - NULL on failure but with an WARN_ON(). 663 */ 664 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 665 { 666 struct arm64_ftr_reg *reg; 667 668 reg = get_arm64_ftr_reg_nowarn(sys_id); 669 670 /* 671 * Requesting a non-existent register search is an error. Warn 672 * and let the caller handle it. 673 */ 674 WARN_ON(!reg); 675 return reg; 676 } 677 678 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 679 s64 ftr_val) 680 { 681 u64 mask = arm64_ftr_mask(ftrp); 682 683 reg &= ~mask; 684 reg |= (ftr_val << ftrp->shift) & mask; 685 return reg; 686 } 687 688 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 689 s64 cur) 690 { 691 s64 ret = 0; 692 693 switch (ftrp->type) { 694 case FTR_EXACT: 695 ret = ftrp->safe_val; 696 break; 697 case FTR_LOWER_SAFE: 698 ret = new < cur ? new : cur; 699 break; 700 case FTR_HIGHER_OR_ZERO_SAFE: 701 if (!cur || !new) 702 break; 703 fallthrough; 704 case FTR_HIGHER_SAFE: 705 ret = new > cur ? new : cur; 706 break; 707 default: 708 BUG(); 709 } 710 711 return ret; 712 } 713 714 static void __init sort_ftr_regs(void) 715 { 716 unsigned int i; 717 718 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 719 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 720 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 721 unsigned int j = 0; 722 723 /* 724 * Features here must be sorted in descending order with respect 725 * to their shift values and should not overlap with each other. 726 */ 727 for (; ftr_bits->width != 0; ftr_bits++, j++) { 728 unsigned int width = ftr_reg->ftr_bits[j].width; 729 unsigned int shift = ftr_reg->ftr_bits[j].shift; 730 unsigned int prev_shift; 731 732 WARN((shift + width) > 64, 733 "%s has invalid feature at shift %d\n", 734 ftr_reg->name, shift); 735 736 /* 737 * Skip the first feature. There is nothing to 738 * compare against for now. 739 */ 740 if (j == 0) 741 continue; 742 743 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 744 WARN((shift + width) > prev_shift, 745 "%s has feature overlap at shift %d\n", 746 ftr_reg->name, shift); 747 } 748 749 /* 750 * Skip the first register. There is nothing to 751 * compare against for now. 752 */ 753 if (i == 0) 754 continue; 755 /* 756 * Registers here must be sorted in ascending order with respect 757 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 758 * to work correctly. 759 */ 760 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 761 } 762 } 763 764 /* 765 * Initialise the CPU feature register from Boot CPU values. 766 * Also initiliases the strict_mask for the register. 767 * Any bits that are not covered by an arm64_ftr_bits entry are considered 768 * RES0 for the system-wide value, and must strictly match. 769 */ 770 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 771 { 772 u64 val = 0; 773 u64 strict_mask = ~0x0ULL; 774 u64 user_mask = 0; 775 u64 valid_mask = 0; 776 777 const struct arm64_ftr_bits *ftrp; 778 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 779 780 if (!reg) 781 return; 782 783 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 784 u64 ftr_mask = arm64_ftr_mask(ftrp); 785 s64 ftr_new = arm64_ftr_value(ftrp, new); 786 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 787 788 if ((ftr_mask & reg->override->mask) == ftr_mask) { 789 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 790 char *str = NULL; 791 792 if (ftr_ovr != tmp) { 793 /* Unsafe, remove the override */ 794 reg->override->mask &= ~ftr_mask; 795 reg->override->val &= ~ftr_mask; 796 tmp = ftr_ovr; 797 str = "ignoring override"; 798 } else if (ftr_new != tmp) { 799 /* Override was valid */ 800 ftr_new = tmp; 801 str = "forced"; 802 } else if (ftr_ovr == tmp) { 803 /* Override was the safe value */ 804 str = "already set"; 805 } 806 807 if (str) 808 pr_warn("%s[%d:%d]: %s to %llx\n", 809 reg->name, 810 ftrp->shift + ftrp->width - 1, 811 ftrp->shift, str, tmp); 812 } 813 814 val = arm64_ftr_set_value(ftrp, val, ftr_new); 815 816 valid_mask |= ftr_mask; 817 if (!ftrp->strict) 818 strict_mask &= ~ftr_mask; 819 if (ftrp->visible) 820 user_mask |= ftr_mask; 821 else 822 reg->user_val = arm64_ftr_set_value(ftrp, 823 reg->user_val, 824 ftrp->safe_val); 825 } 826 827 val &= valid_mask; 828 829 reg->sys_val = val; 830 reg->strict_mask = strict_mask; 831 reg->user_mask = user_mask; 832 } 833 834 extern const struct arm64_cpu_capabilities arm64_errata[]; 835 static const struct arm64_cpu_capabilities arm64_features[]; 836 837 static void __init 838 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 839 { 840 for (; caps->matches; caps++) { 841 if (WARN(caps->capability >= ARM64_NCAPS, 842 "Invalid capability %d\n", caps->capability)) 843 continue; 844 if (WARN(cpu_hwcaps_ptrs[caps->capability], 845 "Duplicate entry for capability %d\n", 846 caps->capability)) 847 continue; 848 cpu_hwcaps_ptrs[caps->capability] = caps; 849 } 850 } 851 852 static void __init init_cpu_hwcaps_indirect_list(void) 853 { 854 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 855 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 856 } 857 858 static void __init setup_boot_cpu_capabilities(void); 859 860 void __init init_cpu_features(struct cpuinfo_arm64 *info) 861 { 862 /* Before we start using the tables, make sure it is sorted */ 863 sort_ftr_regs(); 864 865 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 866 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 867 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 868 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 869 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 870 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 871 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 872 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 873 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 874 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 875 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 876 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 877 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 878 879 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 880 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 881 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 882 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 883 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 884 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 885 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 886 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 887 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 888 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 889 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 890 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 891 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 892 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 893 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 894 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 895 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 896 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 897 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 898 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 899 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 900 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 901 } 902 903 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 904 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 905 sve_init_vq_map(); 906 } 907 908 /* 909 * Initialize the indirect array of CPU hwcaps capabilities pointers 910 * before we handle the boot CPU below. 911 */ 912 init_cpu_hwcaps_indirect_list(); 913 914 /* 915 * Detect and enable early CPU capabilities based on the boot CPU, 916 * after we have initialised the CPU feature infrastructure. 917 */ 918 setup_boot_cpu_capabilities(); 919 } 920 921 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 922 { 923 const struct arm64_ftr_bits *ftrp; 924 925 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 926 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 927 s64 ftr_new = arm64_ftr_value(ftrp, new); 928 929 if (ftr_cur == ftr_new) 930 continue; 931 /* Find a safe value */ 932 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 933 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 934 } 935 936 } 937 938 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 939 { 940 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 941 942 if (!regp) 943 return 0; 944 945 update_cpu_ftr_reg(regp, val); 946 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 947 return 0; 948 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 949 regp->name, boot, cpu, val); 950 return 1; 951 } 952 953 static void relax_cpu_ftr_reg(u32 sys_id, int field) 954 { 955 const struct arm64_ftr_bits *ftrp; 956 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 957 958 if (!regp) 959 return; 960 961 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 962 if (ftrp->shift == field) { 963 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 964 break; 965 } 966 } 967 968 /* Bogus field? */ 969 WARN_ON(!ftrp->width); 970 } 971 972 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 973 struct cpuinfo_arm64 *boot) 974 { 975 int taint = 0; 976 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 977 978 /* 979 * If we don't have AArch32 at all then skip the checks entirely 980 * as the register values may be UNKNOWN and we're not going to be 981 * using them for anything. 982 */ 983 if (!id_aa64pfr0_32bit_el0(pfr0)) 984 return taint; 985 986 /* 987 * If we don't have AArch32 at EL1, then relax the strictness of 988 * EL1-dependent register fields to avoid spurious sanity check fails. 989 */ 990 if (!id_aa64pfr0_32bit_el1(pfr0)) { 991 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 992 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 993 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 994 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 995 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 996 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 997 } 998 999 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1000 info->reg_id_dfr0, boot->reg_id_dfr0); 1001 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1002 info->reg_id_dfr1, boot->reg_id_dfr1); 1003 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1004 info->reg_id_isar0, boot->reg_id_isar0); 1005 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1006 info->reg_id_isar1, boot->reg_id_isar1); 1007 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1008 info->reg_id_isar2, boot->reg_id_isar2); 1009 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1010 info->reg_id_isar3, boot->reg_id_isar3); 1011 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1012 info->reg_id_isar4, boot->reg_id_isar4); 1013 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1014 info->reg_id_isar5, boot->reg_id_isar5); 1015 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1016 info->reg_id_isar6, boot->reg_id_isar6); 1017 1018 /* 1019 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1020 * ACTLR formats could differ across CPUs and therefore would have to 1021 * be trapped for virtualization anyway. 1022 */ 1023 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1024 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1025 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1026 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1027 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1028 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1029 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1030 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1031 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1032 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1033 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1034 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1035 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1036 info->reg_id_pfr0, boot->reg_id_pfr0); 1037 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1038 info->reg_id_pfr1, boot->reg_id_pfr1); 1039 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1040 info->reg_id_pfr2, boot->reg_id_pfr2); 1041 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1042 info->reg_mvfr0, boot->reg_mvfr0); 1043 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1044 info->reg_mvfr1, boot->reg_mvfr1); 1045 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1046 info->reg_mvfr2, boot->reg_mvfr2); 1047 1048 return taint; 1049 } 1050 1051 /* 1052 * Update system wide CPU feature registers with the values from a 1053 * non-boot CPU. Also performs SANITY checks to make sure that there 1054 * aren't any insane variations from that of the boot CPU. 1055 */ 1056 void update_cpu_features(int cpu, 1057 struct cpuinfo_arm64 *info, 1058 struct cpuinfo_arm64 *boot) 1059 { 1060 int taint = 0; 1061 1062 /* 1063 * The kernel can handle differing I-cache policies, but otherwise 1064 * caches should look identical. Userspace JITs will make use of 1065 * *minLine. 1066 */ 1067 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1068 info->reg_ctr, boot->reg_ctr); 1069 1070 /* 1071 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1072 * could result in too much or too little memory being zeroed if a 1073 * process is preempted and migrated between CPUs. 1074 */ 1075 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1076 info->reg_dczid, boot->reg_dczid); 1077 1078 /* If different, timekeeping will be broken (especially with KVM) */ 1079 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1080 info->reg_cntfrq, boot->reg_cntfrq); 1081 1082 /* 1083 * The kernel uses self-hosted debug features and expects CPUs to 1084 * support identical debug features. We presently need CTX_CMPs, WRPs, 1085 * and BRPs to be identical. 1086 * ID_AA64DFR1 is currently RES0. 1087 */ 1088 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1089 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1090 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1091 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1092 /* 1093 * Even in big.LITTLE, processors should be identical instruction-set 1094 * wise. 1095 */ 1096 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1097 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1098 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1099 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1100 1101 /* 1102 * Differing PARange support is fine as long as all peripherals and 1103 * memory are mapped within the minimum PARange of all CPUs. 1104 * Linux should not care about secure memory. 1105 */ 1106 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1107 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1108 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1109 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1110 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1111 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1112 1113 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1114 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1115 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1116 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1117 1118 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1119 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1120 1121 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1122 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1123 info->reg_zcr, boot->reg_zcr); 1124 1125 /* Probe vector lengths, unless we already gave up on SVE */ 1126 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1127 !system_capabilities_finalized()) 1128 sve_update_vq_map(); 1129 } 1130 1131 /* 1132 * This relies on a sanitised view of the AArch64 ID registers 1133 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1134 */ 1135 taint |= update_32bit_cpu_features(cpu, info, boot); 1136 1137 /* 1138 * Mismatched CPU features are a recipe for disaster. Don't even 1139 * pretend to support them. 1140 */ 1141 if (taint) { 1142 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1143 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1144 } 1145 } 1146 1147 u64 read_sanitised_ftr_reg(u32 id) 1148 { 1149 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1150 1151 if (!regp) 1152 return 0; 1153 return regp->sys_val; 1154 } 1155 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1156 1157 #define read_sysreg_case(r) \ 1158 case r: val = read_sysreg_s(r); break; 1159 1160 /* 1161 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1162 * Read the system register on the current CPU 1163 */ 1164 u64 __read_sysreg_by_encoding(u32 sys_id) 1165 { 1166 struct arm64_ftr_reg *regp; 1167 u64 val; 1168 1169 switch (sys_id) { 1170 read_sysreg_case(SYS_ID_PFR0_EL1); 1171 read_sysreg_case(SYS_ID_PFR1_EL1); 1172 read_sysreg_case(SYS_ID_PFR2_EL1); 1173 read_sysreg_case(SYS_ID_DFR0_EL1); 1174 read_sysreg_case(SYS_ID_DFR1_EL1); 1175 read_sysreg_case(SYS_ID_MMFR0_EL1); 1176 read_sysreg_case(SYS_ID_MMFR1_EL1); 1177 read_sysreg_case(SYS_ID_MMFR2_EL1); 1178 read_sysreg_case(SYS_ID_MMFR3_EL1); 1179 read_sysreg_case(SYS_ID_MMFR4_EL1); 1180 read_sysreg_case(SYS_ID_MMFR5_EL1); 1181 read_sysreg_case(SYS_ID_ISAR0_EL1); 1182 read_sysreg_case(SYS_ID_ISAR1_EL1); 1183 read_sysreg_case(SYS_ID_ISAR2_EL1); 1184 read_sysreg_case(SYS_ID_ISAR3_EL1); 1185 read_sysreg_case(SYS_ID_ISAR4_EL1); 1186 read_sysreg_case(SYS_ID_ISAR5_EL1); 1187 read_sysreg_case(SYS_ID_ISAR6_EL1); 1188 read_sysreg_case(SYS_MVFR0_EL1); 1189 read_sysreg_case(SYS_MVFR1_EL1); 1190 read_sysreg_case(SYS_MVFR2_EL1); 1191 1192 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1193 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1194 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1195 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1196 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1197 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1198 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1199 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1200 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1201 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1202 1203 read_sysreg_case(SYS_CNTFRQ_EL0); 1204 read_sysreg_case(SYS_CTR_EL0); 1205 read_sysreg_case(SYS_DCZID_EL0); 1206 1207 default: 1208 BUG(); 1209 return 0; 1210 } 1211 1212 regp = get_arm64_ftr_reg(sys_id); 1213 if (regp) { 1214 val &= ~regp->override->mask; 1215 val |= (regp->override->val & regp->override->mask); 1216 } 1217 1218 return val; 1219 } 1220 1221 #include <linux/irqchip/arm-gic-v3.h> 1222 1223 static bool 1224 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1225 { 1226 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1227 1228 return val >= entry->min_field_value; 1229 } 1230 1231 static bool 1232 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1233 { 1234 u64 val; 1235 1236 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1237 if (scope == SCOPE_SYSTEM) 1238 val = read_sanitised_ftr_reg(entry->sys_reg); 1239 else 1240 val = __read_sysreg_by_encoding(entry->sys_reg); 1241 1242 return feature_matches(val, entry); 1243 } 1244 1245 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1246 { 1247 bool has_sre; 1248 1249 if (!has_cpuid_feature(entry, scope)) 1250 return false; 1251 1252 has_sre = gic_enable_sre(); 1253 if (!has_sre) 1254 pr_warn_once("%s present but disabled by higher exception level\n", 1255 entry->desc); 1256 1257 return has_sre; 1258 } 1259 1260 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1261 { 1262 u32 midr = read_cpuid_id(); 1263 1264 /* Cavium ThunderX pass 1.x and 2.x */ 1265 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1266 MIDR_CPU_VAR_REV(0, 0), 1267 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1268 } 1269 1270 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1271 { 1272 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1273 1274 return cpuid_feature_extract_signed_field(pfr0, 1275 ID_AA64PFR0_FP_SHIFT) < 0; 1276 } 1277 1278 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1279 int scope) 1280 { 1281 u64 ctr; 1282 1283 if (scope == SCOPE_SYSTEM) 1284 ctr = arm64_ftr_reg_ctrel0.sys_val; 1285 else 1286 ctr = read_cpuid_effective_cachetype(); 1287 1288 return ctr & BIT(CTR_IDC_SHIFT); 1289 } 1290 1291 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1292 { 1293 /* 1294 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1295 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1296 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1297 * value. 1298 */ 1299 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1300 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1301 } 1302 1303 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1304 int scope) 1305 { 1306 u64 ctr; 1307 1308 if (scope == SCOPE_SYSTEM) 1309 ctr = arm64_ftr_reg_ctrel0.sys_val; 1310 else 1311 ctr = read_cpuid_cachetype(); 1312 1313 return ctr & BIT(CTR_DIC_SHIFT); 1314 } 1315 1316 static bool __maybe_unused 1317 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1318 { 1319 /* 1320 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1321 * may share TLB entries with a CPU stuck in the crashed 1322 * kernel. 1323 */ 1324 if (is_kdump_kernel()) 1325 return false; 1326 1327 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1328 return false; 1329 1330 return has_cpuid_feature(entry, scope); 1331 } 1332 1333 /* 1334 * This check is triggered during the early boot before the cpufeature 1335 * is initialised. Checking the status on the local CPU allows the boot 1336 * CPU to detect the need for non-global mappings and thus avoiding a 1337 * pagetable re-write after all the CPUs are booted. This check will be 1338 * anyway run on individual CPUs, allowing us to get the consistent 1339 * state once the SMP CPUs are up and thus make the switch to non-global 1340 * mappings if required. 1341 */ 1342 bool kaslr_requires_kpti(void) 1343 { 1344 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1345 return false; 1346 1347 /* 1348 * E0PD does a similar job to KPTI so can be used instead 1349 * where available. 1350 */ 1351 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1352 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1353 if (cpuid_feature_extract_unsigned_field(mmfr2, 1354 ID_AA64MMFR2_E0PD_SHIFT)) 1355 return false; 1356 } 1357 1358 /* 1359 * Systems affected by Cavium erratum 24756 are incompatible 1360 * with KPTI. 1361 */ 1362 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1363 extern const struct midr_range cavium_erratum_27456_cpus[]; 1364 1365 if (is_midr_in_range_list(read_cpuid_id(), 1366 cavium_erratum_27456_cpus)) 1367 return false; 1368 } 1369 1370 return kaslr_offset() > 0; 1371 } 1372 1373 static bool __meltdown_safe = true; 1374 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1375 1376 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1377 int scope) 1378 { 1379 /* List of CPUs that are not vulnerable and don't need KPTI */ 1380 static const struct midr_range kpti_safe_list[] = { 1381 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1382 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1383 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1384 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1385 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1386 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1387 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1388 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1389 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1390 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1391 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1392 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1393 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1394 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1395 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1396 { /* sentinel */ } 1397 }; 1398 char const *str = "kpti command line option"; 1399 bool meltdown_safe; 1400 1401 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1402 1403 /* Defer to CPU feature registers */ 1404 if (has_cpuid_feature(entry, scope)) 1405 meltdown_safe = true; 1406 1407 if (!meltdown_safe) 1408 __meltdown_safe = false; 1409 1410 /* 1411 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1412 * ThunderX leads to apparent I-cache corruption of kernel text, which 1413 * ends as well as you might imagine. Don't even try. 1414 */ 1415 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1416 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1417 __kpti_forced = -1; 1418 } 1419 1420 /* Useful for KASLR robustness */ 1421 if (kaslr_requires_kpti()) { 1422 if (!__kpti_forced) { 1423 str = "KASLR"; 1424 __kpti_forced = 1; 1425 } 1426 } 1427 1428 if (cpu_mitigations_off() && !__kpti_forced) { 1429 str = "mitigations=off"; 1430 __kpti_forced = -1; 1431 } 1432 1433 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1434 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1435 return false; 1436 } 1437 1438 /* Forced? */ 1439 if (__kpti_forced) { 1440 pr_info_once("kernel page table isolation forced %s by %s\n", 1441 __kpti_forced > 0 ? "ON" : "OFF", str); 1442 return __kpti_forced > 0; 1443 } 1444 1445 return !meltdown_safe; 1446 } 1447 1448 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1449 static void 1450 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1451 { 1452 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1453 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1454 kpti_remap_fn *remap_fn; 1455 1456 int cpu = smp_processor_id(); 1457 1458 /* 1459 * We don't need to rewrite the page-tables if either we've done 1460 * it already or we have KASLR enabled and therefore have not 1461 * created any global mappings at all. 1462 */ 1463 if (arm64_use_ng_mappings) 1464 return; 1465 1466 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1467 1468 cpu_install_idmap(); 1469 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1470 cpu_uninstall_idmap(); 1471 1472 if (!cpu) 1473 arm64_use_ng_mappings = true; 1474 1475 return; 1476 } 1477 #else 1478 static void 1479 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1480 { 1481 } 1482 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1483 1484 static int __init parse_kpti(char *str) 1485 { 1486 bool enabled; 1487 int ret = strtobool(str, &enabled); 1488 1489 if (ret) 1490 return ret; 1491 1492 __kpti_forced = enabled ? 1 : -1; 1493 return 0; 1494 } 1495 early_param("kpti", parse_kpti); 1496 1497 #ifdef CONFIG_ARM64_HW_AFDBM 1498 static inline void __cpu_enable_hw_dbm(void) 1499 { 1500 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1501 1502 write_sysreg(tcr, tcr_el1); 1503 isb(); 1504 local_flush_tlb_all(); 1505 } 1506 1507 static bool cpu_has_broken_dbm(void) 1508 { 1509 /* List of CPUs which have broken DBM support. */ 1510 static const struct midr_range cpus[] = { 1511 #ifdef CONFIG_ARM64_ERRATUM_1024718 1512 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1513 /* Kryo4xx Silver (rdpe => r1p0) */ 1514 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1515 #endif 1516 {}, 1517 }; 1518 1519 return is_midr_in_range_list(read_cpuid_id(), cpus); 1520 } 1521 1522 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1523 { 1524 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1525 !cpu_has_broken_dbm(); 1526 } 1527 1528 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1529 { 1530 if (cpu_can_use_dbm(cap)) 1531 __cpu_enable_hw_dbm(); 1532 } 1533 1534 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1535 int __unused) 1536 { 1537 static bool detected = false; 1538 /* 1539 * DBM is a non-conflicting feature. i.e, the kernel can safely 1540 * run a mix of CPUs with and without the feature. So, we 1541 * unconditionally enable the capability to allow any late CPU 1542 * to use the feature. We only enable the control bits on the 1543 * CPU, if it actually supports. 1544 * 1545 * We have to make sure we print the "feature" detection only 1546 * when at least one CPU actually uses it. So check if this CPU 1547 * can actually use it and print the message exactly once. 1548 * 1549 * This is safe as all CPUs (including secondary CPUs - due to the 1550 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1551 * goes through the "matches" check exactly once. Also if a CPU 1552 * matches the criteria, it is guaranteed that the CPU will turn 1553 * the DBM on, as the capability is unconditionally enabled. 1554 */ 1555 if (!detected && cpu_can_use_dbm(cap)) { 1556 detected = true; 1557 pr_info("detected: Hardware dirty bit management\n"); 1558 } 1559 1560 return true; 1561 } 1562 1563 #endif 1564 1565 #ifdef CONFIG_ARM64_AMU_EXTN 1566 1567 /* 1568 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1569 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1570 * information regarding all the events that it supports. When a CPU bit is 1571 * set in the cpumask, the user of this feature can only rely on the presence 1572 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1573 * counters are enabled or access to these counters is enabled by code 1574 * executed at higher exception levels (firmware). 1575 */ 1576 static struct cpumask amu_cpus __read_mostly; 1577 1578 bool cpu_has_amu_feat(int cpu) 1579 { 1580 return cpumask_test_cpu(cpu, &amu_cpus); 1581 } 1582 1583 int get_cpu_with_amu_feat(void) 1584 { 1585 return cpumask_any(&amu_cpus); 1586 } 1587 1588 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1589 { 1590 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1591 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1592 smp_processor_id()); 1593 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1594 update_freq_counters_refs(); 1595 } 1596 } 1597 1598 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1599 int __unused) 1600 { 1601 /* 1602 * The AMU extension is a non-conflicting feature: the kernel can 1603 * safely run a mix of CPUs with and without support for the 1604 * activity monitors extension. Therefore, unconditionally enable 1605 * the capability to allow any late CPU to use the feature. 1606 * 1607 * With this feature unconditionally enabled, the cpu_enable 1608 * function will be called for all CPUs that match the criteria, 1609 * including secondary and hotplugged, marking this feature as 1610 * present on that respective CPU. The enable function will also 1611 * print a detection message. 1612 */ 1613 1614 return true; 1615 } 1616 #else 1617 int get_cpu_with_amu_feat(void) 1618 { 1619 return nr_cpu_ids; 1620 } 1621 #endif 1622 1623 #ifdef CONFIG_ARM64_VHE 1624 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1625 { 1626 return is_kernel_in_hyp_mode(); 1627 } 1628 1629 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1630 { 1631 /* 1632 * Copy register values that aren't redirected by hardware. 1633 * 1634 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1635 * this value to tpidr_el2 before we patch the code. Once we've done 1636 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1637 * do anything here. 1638 */ 1639 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1640 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1641 } 1642 #endif 1643 1644 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1645 { 1646 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1647 1648 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1649 WARN_ON(val & (7 << 27 | 7 << 21)); 1650 } 1651 1652 #ifdef CONFIG_ARM64_PAN 1653 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1654 { 1655 /* 1656 * We modify PSTATE. This won't work from irq context as the PSTATE 1657 * is discarded once we return from the exception. 1658 */ 1659 WARN_ON_ONCE(in_interrupt()); 1660 1661 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1662 set_pstate_pan(1); 1663 } 1664 #endif /* CONFIG_ARM64_PAN */ 1665 1666 #ifdef CONFIG_ARM64_RAS_EXTN 1667 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1668 { 1669 /* Firmware may have left a deferred SError in this register. */ 1670 write_sysreg_s(0, SYS_DISR_EL1); 1671 } 1672 #endif /* CONFIG_ARM64_RAS_EXTN */ 1673 1674 #ifdef CONFIG_ARM64_PTR_AUTH 1675 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1676 { 1677 int boot_val, sec_val; 1678 1679 /* We don't expect to be called with SCOPE_SYSTEM */ 1680 WARN_ON(scope == SCOPE_SYSTEM); 1681 /* 1682 * The ptr-auth feature levels are not intercompatible with lower 1683 * levels. Hence we must match ptr-auth feature level of the secondary 1684 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1685 * from the sanitised register whereas direct register read is done for 1686 * the secondary CPUs. 1687 * The sanitised feature state is guaranteed to match that of the 1688 * boot CPU as a mismatched secondary CPU is parked before it gets 1689 * a chance to update the state, with the capability. 1690 */ 1691 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1692 entry->field_pos, entry->sign); 1693 if (scope & SCOPE_BOOT_CPU) 1694 return boot_val >= entry->min_field_value; 1695 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1696 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1697 entry->field_pos, entry->sign); 1698 return sec_val == boot_val; 1699 } 1700 1701 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1702 int scope) 1703 { 1704 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1705 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1706 } 1707 1708 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1709 int __unused) 1710 { 1711 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1712 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1713 } 1714 #endif /* CONFIG_ARM64_PTR_AUTH */ 1715 1716 #ifdef CONFIG_ARM64_E0PD 1717 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1718 { 1719 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1720 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1721 } 1722 #endif /* CONFIG_ARM64_E0PD */ 1723 1724 #ifdef CONFIG_ARM64_PSEUDO_NMI 1725 static bool enable_pseudo_nmi; 1726 1727 static int __init early_enable_pseudo_nmi(char *p) 1728 { 1729 return strtobool(p, &enable_pseudo_nmi); 1730 } 1731 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1732 1733 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1734 int scope) 1735 { 1736 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1737 } 1738 #endif 1739 1740 #ifdef CONFIG_ARM64_BTI 1741 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1742 { 1743 /* 1744 * Use of X16/X17 for tail-calls and trampolines that jump to 1745 * function entry points using BR is a requirement for 1746 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1747 * So, be strict and forbid other BRs using other registers to 1748 * jump onto a PACIxSP instruction: 1749 */ 1750 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1751 isb(); 1752 } 1753 #endif /* CONFIG_ARM64_BTI */ 1754 1755 #ifdef CONFIG_ARM64_MTE 1756 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1757 { 1758 /* 1759 * Clear the tags in the zero page. This needs to be done via the 1760 * linear map which has the Tagged attribute. 1761 */ 1762 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1763 mte_clear_page_tags(lm_alias(empty_zero_page)); 1764 1765 kasan_init_hw_tags_cpu(); 1766 } 1767 #endif /* CONFIG_ARM64_MTE */ 1768 1769 #ifdef CONFIG_KVM 1770 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1771 { 1772 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1773 return false; 1774 1775 if (is_kernel_in_hyp_mode()) { 1776 pr_warn("Protected KVM not available with VHE\n"); 1777 return false; 1778 } 1779 1780 return true; 1781 } 1782 #endif /* CONFIG_KVM */ 1783 1784 /* Internal helper functions to match cpu capability type */ 1785 static bool 1786 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1787 { 1788 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1789 } 1790 1791 static bool 1792 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1793 { 1794 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1795 } 1796 1797 static bool 1798 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1799 { 1800 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1801 } 1802 1803 static const struct arm64_cpu_capabilities arm64_features[] = { 1804 { 1805 .desc = "GIC system register CPU interface", 1806 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1807 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1808 .matches = has_useable_gicv3_cpuif, 1809 .sys_reg = SYS_ID_AA64PFR0_EL1, 1810 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1811 .sign = FTR_UNSIGNED, 1812 .min_field_value = 1, 1813 }, 1814 #ifdef CONFIG_ARM64_PAN 1815 { 1816 .desc = "Privileged Access Never", 1817 .capability = ARM64_HAS_PAN, 1818 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1819 .matches = has_cpuid_feature, 1820 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1821 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1822 .sign = FTR_UNSIGNED, 1823 .min_field_value = 1, 1824 .cpu_enable = cpu_enable_pan, 1825 }, 1826 #endif /* CONFIG_ARM64_PAN */ 1827 #ifdef CONFIG_ARM64_LSE_ATOMICS 1828 { 1829 .desc = "LSE atomic instructions", 1830 .capability = ARM64_HAS_LSE_ATOMICS, 1831 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1832 .matches = has_cpuid_feature, 1833 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1834 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1835 .sign = FTR_UNSIGNED, 1836 .min_field_value = 2, 1837 }, 1838 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1839 { 1840 .desc = "Software prefetching using PRFM", 1841 .capability = ARM64_HAS_NO_HW_PREFETCH, 1842 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1843 .matches = has_no_hw_prefetch, 1844 }, 1845 #ifdef CONFIG_ARM64_VHE 1846 { 1847 .desc = "Virtualization Host Extensions", 1848 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1849 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1850 .matches = runs_at_el2, 1851 .cpu_enable = cpu_copy_el2regs, 1852 }, 1853 #endif /* CONFIG_ARM64_VHE */ 1854 { 1855 .desc = "32-bit EL0 Support", 1856 .capability = ARM64_HAS_32BIT_EL0, 1857 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1858 .matches = has_cpuid_feature, 1859 .sys_reg = SYS_ID_AA64PFR0_EL1, 1860 .sign = FTR_UNSIGNED, 1861 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1862 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1863 }, 1864 #ifdef CONFIG_KVM 1865 { 1866 .desc = "32-bit EL1 Support", 1867 .capability = ARM64_HAS_32BIT_EL1, 1868 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1869 .matches = has_cpuid_feature, 1870 .sys_reg = SYS_ID_AA64PFR0_EL1, 1871 .sign = FTR_UNSIGNED, 1872 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1873 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1874 }, 1875 { 1876 .desc = "Protected KVM", 1877 .capability = ARM64_KVM_PROTECTED_MODE, 1878 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1879 .matches = is_kvm_protected_mode, 1880 }, 1881 #endif 1882 { 1883 .desc = "Kernel page table isolation (KPTI)", 1884 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1885 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1886 /* 1887 * The ID feature fields below are used to indicate that 1888 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1889 * more details. 1890 */ 1891 .sys_reg = SYS_ID_AA64PFR0_EL1, 1892 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1893 .min_field_value = 1, 1894 .matches = unmap_kernel_at_el0, 1895 .cpu_enable = kpti_install_ng_mappings, 1896 }, 1897 { 1898 /* FP/SIMD is not implemented */ 1899 .capability = ARM64_HAS_NO_FPSIMD, 1900 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1901 .min_field_value = 0, 1902 .matches = has_no_fpsimd, 1903 }, 1904 #ifdef CONFIG_ARM64_PMEM 1905 { 1906 .desc = "Data cache clean to Point of Persistence", 1907 .capability = ARM64_HAS_DCPOP, 1908 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1909 .matches = has_cpuid_feature, 1910 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1911 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1912 .min_field_value = 1, 1913 }, 1914 { 1915 .desc = "Data cache clean to Point of Deep Persistence", 1916 .capability = ARM64_HAS_DCPODP, 1917 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1918 .matches = has_cpuid_feature, 1919 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1920 .sign = FTR_UNSIGNED, 1921 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1922 .min_field_value = 2, 1923 }, 1924 #endif 1925 #ifdef CONFIG_ARM64_SVE 1926 { 1927 .desc = "Scalable Vector Extension", 1928 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1929 .capability = ARM64_SVE, 1930 .sys_reg = SYS_ID_AA64PFR0_EL1, 1931 .sign = FTR_UNSIGNED, 1932 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1933 .min_field_value = ID_AA64PFR0_SVE, 1934 .matches = has_cpuid_feature, 1935 .cpu_enable = sve_kernel_enable, 1936 }, 1937 #endif /* CONFIG_ARM64_SVE */ 1938 #ifdef CONFIG_ARM64_RAS_EXTN 1939 { 1940 .desc = "RAS Extension Support", 1941 .capability = ARM64_HAS_RAS_EXTN, 1942 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1943 .matches = has_cpuid_feature, 1944 .sys_reg = SYS_ID_AA64PFR0_EL1, 1945 .sign = FTR_UNSIGNED, 1946 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1947 .min_field_value = ID_AA64PFR0_RAS_V1, 1948 .cpu_enable = cpu_clear_disr, 1949 }, 1950 #endif /* CONFIG_ARM64_RAS_EXTN */ 1951 #ifdef CONFIG_ARM64_AMU_EXTN 1952 { 1953 /* 1954 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1955 * Therefore, don't provide .desc as we don't want the detection 1956 * message to be shown until at least one CPU is detected to 1957 * support the feature. 1958 */ 1959 .capability = ARM64_HAS_AMU_EXTN, 1960 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1961 .matches = has_amu, 1962 .sys_reg = SYS_ID_AA64PFR0_EL1, 1963 .sign = FTR_UNSIGNED, 1964 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1965 .min_field_value = ID_AA64PFR0_AMU, 1966 .cpu_enable = cpu_amu_enable, 1967 }, 1968 #endif /* CONFIG_ARM64_AMU_EXTN */ 1969 { 1970 .desc = "Data cache clean to the PoU not required for I/D coherence", 1971 .capability = ARM64_HAS_CACHE_IDC, 1972 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1973 .matches = has_cache_idc, 1974 .cpu_enable = cpu_emulate_effective_ctr, 1975 }, 1976 { 1977 .desc = "Instruction cache invalidation not required for I/D coherence", 1978 .capability = ARM64_HAS_CACHE_DIC, 1979 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1980 .matches = has_cache_dic, 1981 }, 1982 { 1983 .desc = "Stage-2 Force Write-Back", 1984 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1985 .capability = ARM64_HAS_STAGE2_FWB, 1986 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1987 .sign = FTR_UNSIGNED, 1988 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1989 .min_field_value = 1, 1990 .matches = has_cpuid_feature, 1991 .cpu_enable = cpu_has_fwb, 1992 }, 1993 { 1994 .desc = "ARMv8.4 Translation Table Level", 1995 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1996 .capability = ARM64_HAS_ARMv8_4_TTL, 1997 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1998 .sign = FTR_UNSIGNED, 1999 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2000 .min_field_value = 1, 2001 .matches = has_cpuid_feature, 2002 }, 2003 { 2004 .desc = "TLB range maintenance instructions", 2005 .capability = ARM64_HAS_TLB_RANGE, 2006 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2007 .matches = has_cpuid_feature, 2008 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2009 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2010 .sign = FTR_UNSIGNED, 2011 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2012 }, 2013 #ifdef CONFIG_ARM64_HW_AFDBM 2014 { 2015 /* 2016 * Since we turn this on always, we don't want the user to 2017 * think that the feature is available when it may not be. 2018 * So hide the description. 2019 * 2020 * .desc = "Hardware pagetable Dirty Bit Management", 2021 * 2022 */ 2023 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2024 .capability = ARM64_HW_DBM, 2025 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2026 .sign = FTR_UNSIGNED, 2027 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2028 .min_field_value = 2, 2029 .matches = has_hw_dbm, 2030 .cpu_enable = cpu_enable_hw_dbm, 2031 }, 2032 #endif 2033 { 2034 .desc = "CRC32 instructions", 2035 .capability = ARM64_HAS_CRC32, 2036 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2037 .matches = has_cpuid_feature, 2038 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2039 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2040 .min_field_value = 1, 2041 }, 2042 { 2043 .desc = "Speculative Store Bypassing Safe (SSBS)", 2044 .capability = ARM64_SSBS, 2045 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2046 .matches = has_cpuid_feature, 2047 .sys_reg = SYS_ID_AA64PFR1_EL1, 2048 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2049 .sign = FTR_UNSIGNED, 2050 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2051 }, 2052 #ifdef CONFIG_ARM64_CNP 2053 { 2054 .desc = "Common not Private translations", 2055 .capability = ARM64_HAS_CNP, 2056 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2057 .matches = has_useable_cnp, 2058 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2059 .sign = FTR_UNSIGNED, 2060 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2061 .min_field_value = 1, 2062 .cpu_enable = cpu_enable_cnp, 2063 }, 2064 #endif 2065 { 2066 .desc = "Speculation barrier (SB)", 2067 .capability = ARM64_HAS_SB, 2068 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2069 .matches = has_cpuid_feature, 2070 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2071 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2072 .sign = FTR_UNSIGNED, 2073 .min_field_value = 1, 2074 }, 2075 #ifdef CONFIG_ARM64_PTR_AUTH 2076 { 2077 .desc = "Address authentication (architected algorithm)", 2078 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2079 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2080 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2081 .sign = FTR_UNSIGNED, 2082 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2083 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2084 .matches = has_address_auth_cpucap, 2085 }, 2086 { 2087 .desc = "Address authentication (IMP DEF algorithm)", 2088 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2089 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2090 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2091 .sign = FTR_UNSIGNED, 2092 .field_pos = ID_AA64ISAR1_API_SHIFT, 2093 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2094 .matches = has_address_auth_cpucap, 2095 }, 2096 { 2097 .capability = ARM64_HAS_ADDRESS_AUTH, 2098 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2099 .matches = has_address_auth_metacap, 2100 }, 2101 { 2102 .desc = "Generic authentication (architected algorithm)", 2103 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2104 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2105 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2106 .sign = FTR_UNSIGNED, 2107 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2108 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2109 .matches = has_cpuid_feature, 2110 }, 2111 { 2112 .desc = "Generic authentication (IMP DEF algorithm)", 2113 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2114 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2115 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2116 .sign = FTR_UNSIGNED, 2117 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2118 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2119 .matches = has_cpuid_feature, 2120 }, 2121 { 2122 .capability = ARM64_HAS_GENERIC_AUTH, 2123 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2124 .matches = has_generic_auth, 2125 }, 2126 #endif /* CONFIG_ARM64_PTR_AUTH */ 2127 #ifdef CONFIG_ARM64_PSEUDO_NMI 2128 { 2129 /* 2130 * Depends on having GICv3 2131 */ 2132 .desc = "IRQ priority masking", 2133 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2134 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2135 .matches = can_use_gic_priorities, 2136 .sys_reg = SYS_ID_AA64PFR0_EL1, 2137 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2138 .sign = FTR_UNSIGNED, 2139 .min_field_value = 1, 2140 }, 2141 #endif 2142 #ifdef CONFIG_ARM64_E0PD 2143 { 2144 .desc = "E0PD", 2145 .capability = ARM64_HAS_E0PD, 2146 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2147 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2148 .sign = FTR_UNSIGNED, 2149 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2150 .matches = has_cpuid_feature, 2151 .min_field_value = 1, 2152 .cpu_enable = cpu_enable_e0pd, 2153 }, 2154 #endif 2155 #ifdef CONFIG_ARCH_RANDOM 2156 { 2157 .desc = "Random Number Generator", 2158 .capability = ARM64_HAS_RNG, 2159 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2160 .matches = has_cpuid_feature, 2161 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2162 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2163 .sign = FTR_UNSIGNED, 2164 .min_field_value = 1, 2165 }, 2166 #endif 2167 #ifdef CONFIG_ARM64_BTI 2168 { 2169 .desc = "Branch Target Identification", 2170 .capability = ARM64_BTI, 2171 #ifdef CONFIG_ARM64_BTI_KERNEL 2172 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2173 #else 2174 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2175 #endif 2176 .matches = has_cpuid_feature, 2177 .cpu_enable = bti_enable, 2178 .sys_reg = SYS_ID_AA64PFR1_EL1, 2179 .field_pos = ID_AA64PFR1_BT_SHIFT, 2180 .min_field_value = ID_AA64PFR1_BT_BTI, 2181 .sign = FTR_UNSIGNED, 2182 }, 2183 #endif 2184 #ifdef CONFIG_ARM64_MTE 2185 { 2186 .desc = "Memory Tagging Extension", 2187 .capability = ARM64_MTE, 2188 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2189 .matches = has_cpuid_feature, 2190 .sys_reg = SYS_ID_AA64PFR1_EL1, 2191 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2192 .min_field_value = ID_AA64PFR1_MTE, 2193 .sign = FTR_UNSIGNED, 2194 .cpu_enable = cpu_enable_mte, 2195 }, 2196 #endif /* CONFIG_ARM64_MTE */ 2197 { 2198 .desc = "RCpc load-acquire (LDAPR)", 2199 .capability = ARM64_HAS_LDAPR, 2200 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2201 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2202 .sign = FTR_UNSIGNED, 2203 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2204 .matches = has_cpuid_feature, 2205 .min_field_value = 1, 2206 }, 2207 {}, 2208 }; 2209 2210 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2211 .matches = has_cpuid_feature, \ 2212 .sys_reg = reg, \ 2213 .field_pos = field, \ 2214 .sign = s, \ 2215 .min_field_value = min_value, 2216 2217 #define __HWCAP_CAP(name, cap_type, cap) \ 2218 .desc = name, \ 2219 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2220 .hwcap_type = cap_type, \ 2221 .hwcap = cap, \ 2222 2223 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2224 { \ 2225 __HWCAP_CAP(#cap, cap_type, cap) \ 2226 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2227 } 2228 2229 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2230 { \ 2231 __HWCAP_CAP(#cap, cap_type, cap) \ 2232 .matches = cpucap_multi_entry_cap_matches, \ 2233 .match_list = list, \ 2234 } 2235 2236 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2237 { \ 2238 __HWCAP_CAP(#cap, cap_type, cap) \ 2239 .matches = match, \ 2240 } 2241 2242 #ifdef CONFIG_ARM64_PTR_AUTH 2243 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2244 { 2245 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2246 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2247 }, 2248 { 2249 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2250 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2251 }, 2252 {}, 2253 }; 2254 2255 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2256 { 2257 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2258 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2259 }, 2260 { 2261 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2262 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2263 }, 2264 {}, 2265 }; 2266 #endif 2267 2268 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2269 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2270 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2271 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2272 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2273 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2274 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2275 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2276 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2277 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2278 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2279 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2280 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2281 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2282 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2283 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2284 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2285 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2286 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2287 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2288 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2289 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2290 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2291 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2292 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2293 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2294 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2295 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2296 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2297 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2298 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2299 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2300 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2301 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2302 #ifdef CONFIG_ARM64_SVE 2303 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2304 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2305 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2306 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2307 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2308 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2309 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2310 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2311 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2312 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2313 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2314 #endif 2315 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2316 #ifdef CONFIG_ARM64_BTI 2317 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2318 #endif 2319 #ifdef CONFIG_ARM64_PTR_AUTH 2320 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2321 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2322 #endif 2323 #ifdef CONFIG_ARM64_MTE 2324 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2325 #endif /* CONFIG_ARM64_MTE */ 2326 {}, 2327 }; 2328 2329 #ifdef CONFIG_COMPAT 2330 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2331 { 2332 /* 2333 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2334 * in line with that of arm32 as in vfp_init(). We make sure that the 2335 * check is future proof, by making sure value is non-zero. 2336 */ 2337 u32 mvfr1; 2338 2339 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2340 if (scope == SCOPE_SYSTEM) 2341 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2342 else 2343 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2344 2345 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2346 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2347 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2348 } 2349 #endif 2350 2351 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2352 #ifdef CONFIG_COMPAT 2353 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2354 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2355 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2356 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2357 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2358 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2359 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2360 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2361 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2362 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2363 #endif 2364 {}, 2365 }; 2366 2367 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2368 { 2369 switch (cap->hwcap_type) { 2370 case CAP_HWCAP: 2371 cpu_set_feature(cap->hwcap); 2372 break; 2373 #ifdef CONFIG_COMPAT 2374 case CAP_COMPAT_HWCAP: 2375 compat_elf_hwcap |= (u32)cap->hwcap; 2376 break; 2377 case CAP_COMPAT_HWCAP2: 2378 compat_elf_hwcap2 |= (u32)cap->hwcap; 2379 break; 2380 #endif 2381 default: 2382 WARN_ON(1); 2383 break; 2384 } 2385 } 2386 2387 /* Check if we have a particular HWCAP enabled */ 2388 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2389 { 2390 bool rc; 2391 2392 switch (cap->hwcap_type) { 2393 case CAP_HWCAP: 2394 rc = cpu_have_feature(cap->hwcap); 2395 break; 2396 #ifdef CONFIG_COMPAT 2397 case CAP_COMPAT_HWCAP: 2398 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2399 break; 2400 case CAP_COMPAT_HWCAP2: 2401 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2402 break; 2403 #endif 2404 default: 2405 WARN_ON(1); 2406 rc = false; 2407 } 2408 2409 return rc; 2410 } 2411 2412 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2413 { 2414 /* We support emulation of accesses to CPU ID feature registers */ 2415 cpu_set_named_feature(CPUID); 2416 for (; hwcaps->matches; hwcaps++) 2417 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2418 cap_set_elf_hwcap(hwcaps); 2419 } 2420 2421 static void update_cpu_capabilities(u16 scope_mask) 2422 { 2423 int i; 2424 const struct arm64_cpu_capabilities *caps; 2425 2426 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2427 for (i = 0; i < ARM64_NCAPS; i++) { 2428 caps = cpu_hwcaps_ptrs[i]; 2429 if (!caps || !(caps->type & scope_mask) || 2430 cpus_have_cap(caps->capability) || 2431 !caps->matches(caps, cpucap_default_scope(caps))) 2432 continue; 2433 2434 if (caps->desc) 2435 pr_info("detected: %s\n", caps->desc); 2436 cpus_set_cap(caps->capability); 2437 2438 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2439 set_bit(caps->capability, boot_capabilities); 2440 } 2441 } 2442 2443 /* 2444 * Enable all the available capabilities on this CPU. The capabilities 2445 * with BOOT_CPU scope are handled separately and hence skipped here. 2446 */ 2447 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2448 { 2449 int i; 2450 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2451 2452 for_each_available_cap(i) { 2453 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2454 2455 if (WARN_ON(!cap)) 2456 continue; 2457 2458 if (!(cap->type & non_boot_scope)) 2459 continue; 2460 2461 if (cap->cpu_enable) 2462 cap->cpu_enable(cap); 2463 } 2464 return 0; 2465 } 2466 2467 /* 2468 * Run through the enabled capabilities and enable() it on all active 2469 * CPUs 2470 */ 2471 static void __init enable_cpu_capabilities(u16 scope_mask) 2472 { 2473 int i; 2474 const struct arm64_cpu_capabilities *caps; 2475 bool boot_scope; 2476 2477 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2478 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2479 2480 for (i = 0; i < ARM64_NCAPS; i++) { 2481 unsigned int num; 2482 2483 caps = cpu_hwcaps_ptrs[i]; 2484 if (!caps || !(caps->type & scope_mask)) 2485 continue; 2486 num = caps->capability; 2487 if (!cpus_have_cap(num)) 2488 continue; 2489 2490 /* Ensure cpus_have_const_cap(num) works */ 2491 static_branch_enable(&cpu_hwcap_keys[num]); 2492 2493 if (boot_scope && caps->cpu_enable) 2494 /* 2495 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2496 * before any secondary CPU boots. Thus, each secondary 2497 * will enable the capability as appropriate via 2498 * check_local_cpu_capabilities(). The only exception is 2499 * the boot CPU, for which the capability must be 2500 * enabled here. This approach avoids costly 2501 * stop_machine() calls for this case. 2502 */ 2503 caps->cpu_enable(caps); 2504 } 2505 2506 /* 2507 * For all non-boot scope capabilities, use stop_machine() 2508 * as it schedules the work allowing us to modify PSTATE, 2509 * instead of on_each_cpu() which uses an IPI, giving us a 2510 * PSTATE that disappears when we return. 2511 */ 2512 if (!boot_scope) 2513 stop_machine(cpu_enable_non_boot_scope_capabilities, 2514 NULL, cpu_online_mask); 2515 } 2516 2517 /* 2518 * Run through the list of capabilities to check for conflicts. 2519 * If the system has already detected a capability, take necessary 2520 * action on this CPU. 2521 */ 2522 static void verify_local_cpu_caps(u16 scope_mask) 2523 { 2524 int i; 2525 bool cpu_has_cap, system_has_cap; 2526 const struct arm64_cpu_capabilities *caps; 2527 2528 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2529 2530 for (i = 0; i < ARM64_NCAPS; i++) { 2531 caps = cpu_hwcaps_ptrs[i]; 2532 if (!caps || !(caps->type & scope_mask)) 2533 continue; 2534 2535 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2536 system_has_cap = cpus_have_cap(caps->capability); 2537 2538 if (system_has_cap) { 2539 /* 2540 * Check if the new CPU misses an advertised feature, 2541 * which is not safe to miss. 2542 */ 2543 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2544 break; 2545 /* 2546 * We have to issue cpu_enable() irrespective of 2547 * whether the CPU has it or not, as it is enabeld 2548 * system wide. It is upto the call back to take 2549 * appropriate action on this CPU. 2550 */ 2551 if (caps->cpu_enable) 2552 caps->cpu_enable(caps); 2553 } else { 2554 /* 2555 * Check if the CPU has this capability if it isn't 2556 * safe to have when the system doesn't. 2557 */ 2558 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2559 break; 2560 } 2561 } 2562 2563 if (i < ARM64_NCAPS) { 2564 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2565 smp_processor_id(), caps->capability, 2566 caps->desc, system_has_cap, cpu_has_cap); 2567 2568 if (cpucap_panic_on_conflict(caps)) 2569 cpu_panic_kernel(); 2570 else 2571 cpu_die_early(); 2572 } 2573 } 2574 2575 /* 2576 * Check for CPU features that are used in early boot 2577 * based on the Boot CPU value. 2578 */ 2579 static void check_early_cpu_features(void) 2580 { 2581 verify_cpu_asid_bits(); 2582 2583 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2584 } 2585 2586 static void 2587 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2588 { 2589 2590 for (; caps->matches; caps++) 2591 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2592 pr_crit("CPU%d: missing HWCAP: %s\n", 2593 smp_processor_id(), caps->desc); 2594 cpu_die_early(); 2595 } 2596 } 2597 2598 static void verify_sve_features(void) 2599 { 2600 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2601 u64 zcr = read_zcr_features(); 2602 2603 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2604 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2605 2606 if (len < safe_len || sve_verify_vq_map()) { 2607 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2608 smp_processor_id()); 2609 cpu_die_early(); 2610 } 2611 2612 /* Add checks on other ZCR bits here if necessary */ 2613 } 2614 2615 static void verify_hyp_capabilities(void) 2616 { 2617 u64 safe_mmfr1, mmfr0, mmfr1; 2618 int parange, ipa_max; 2619 unsigned int safe_vmid_bits, vmid_bits; 2620 2621 if (!IS_ENABLED(CONFIG_KVM)) 2622 return; 2623 2624 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2625 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2626 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2627 2628 /* Verify VMID bits */ 2629 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2630 vmid_bits = get_vmid_bits(mmfr1); 2631 if (vmid_bits < safe_vmid_bits) { 2632 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2633 cpu_die_early(); 2634 } 2635 2636 /* Verify IPA range */ 2637 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2638 ID_AA64MMFR0_PARANGE_SHIFT); 2639 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2640 if (ipa_max < get_kvm_ipa_limit()) { 2641 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2642 cpu_die_early(); 2643 } 2644 } 2645 2646 /* 2647 * Run through the enabled system capabilities and enable() it on this CPU. 2648 * The capabilities were decided based on the available CPUs at the boot time. 2649 * Any new CPU should match the system wide status of the capability. If the 2650 * new CPU doesn't have a capability which the system now has enabled, we 2651 * cannot do anything to fix it up and could cause unexpected failures. So 2652 * we park the CPU. 2653 */ 2654 static void verify_local_cpu_capabilities(void) 2655 { 2656 /* 2657 * The capabilities with SCOPE_BOOT_CPU are checked from 2658 * check_early_cpu_features(), as they need to be verified 2659 * on all secondary CPUs. 2660 */ 2661 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2662 2663 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2664 2665 if (system_supports_32bit_el0()) 2666 verify_local_elf_hwcaps(compat_elf_hwcaps); 2667 2668 if (system_supports_sve()) 2669 verify_sve_features(); 2670 2671 if (is_hyp_mode_available()) 2672 verify_hyp_capabilities(); 2673 } 2674 2675 void check_local_cpu_capabilities(void) 2676 { 2677 /* 2678 * All secondary CPUs should conform to the early CPU features 2679 * in use by the kernel based on boot CPU. 2680 */ 2681 check_early_cpu_features(); 2682 2683 /* 2684 * If we haven't finalised the system capabilities, this CPU gets 2685 * a chance to update the errata work arounds and local features. 2686 * Otherwise, this CPU should verify that it has all the system 2687 * advertised capabilities. 2688 */ 2689 if (!system_capabilities_finalized()) 2690 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2691 else 2692 verify_local_cpu_capabilities(); 2693 } 2694 2695 static void __init setup_boot_cpu_capabilities(void) 2696 { 2697 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2698 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2699 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2700 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2701 } 2702 2703 bool this_cpu_has_cap(unsigned int n) 2704 { 2705 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2706 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2707 2708 if (cap) 2709 return cap->matches(cap, SCOPE_LOCAL_CPU); 2710 } 2711 2712 return false; 2713 } 2714 2715 /* 2716 * This helper function is used in a narrow window when, 2717 * - The system wide safe registers are set with all the SMP CPUs and, 2718 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2719 * In all other cases cpus_have_{const_}cap() should be used. 2720 */ 2721 static bool __maybe_unused __system_matches_cap(unsigned int n) 2722 { 2723 if (n < ARM64_NCAPS) { 2724 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2725 2726 if (cap) 2727 return cap->matches(cap, SCOPE_SYSTEM); 2728 } 2729 return false; 2730 } 2731 2732 void cpu_set_feature(unsigned int num) 2733 { 2734 WARN_ON(num >= MAX_CPU_FEATURES); 2735 elf_hwcap |= BIT(num); 2736 } 2737 EXPORT_SYMBOL_GPL(cpu_set_feature); 2738 2739 bool cpu_have_feature(unsigned int num) 2740 { 2741 WARN_ON(num >= MAX_CPU_FEATURES); 2742 return elf_hwcap & BIT(num); 2743 } 2744 EXPORT_SYMBOL_GPL(cpu_have_feature); 2745 2746 unsigned long cpu_get_elf_hwcap(void) 2747 { 2748 /* 2749 * We currently only populate the first 32 bits of AT_HWCAP. Please 2750 * note that for userspace compatibility we guarantee that bits 62 2751 * and 63 will always be returned as 0. 2752 */ 2753 return lower_32_bits(elf_hwcap); 2754 } 2755 2756 unsigned long cpu_get_elf_hwcap2(void) 2757 { 2758 return upper_32_bits(elf_hwcap); 2759 } 2760 2761 static void __init setup_system_capabilities(void) 2762 { 2763 /* 2764 * We have finalised the system-wide safe feature 2765 * registers, finalise the capabilities that depend 2766 * on it. Also enable all the available capabilities, 2767 * that are not enabled already. 2768 */ 2769 update_cpu_capabilities(SCOPE_SYSTEM); 2770 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2771 } 2772 2773 void __init setup_cpu_features(void) 2774 { 2775 u32 cwg; 2776 2777 setup_system_capabilities(); 2778 setup_elf_hwcaps(arm64_elf_hwcaps); 2779 2780 if (system_supports_32bit_el0()) 2781 setup_elf_hwcaps(compat_elf_hwcaps); 2782 2783 if (system_uses_ttbr0_pan()) 2784 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2785 2786 sve_setup(); 2787 minsigstksz_setup(); 2788 2789 /* Advertise that we have computed the system capabilities */ 2790 finalize_system_capabilities(); 2791 2792 /* 2793 * Check for sane CTR_EL0.CWG value. 2794 */ 2795 cwg = cache_type_cwg(); 2796 if (!cwg) 2797 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2798 ARCH_DMA_MINALIGN); 2799 } 2800 2801 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2802 { 2803 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2804 } 2805 2806 /* 2807 * We emulate only the following system register space. 2808 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2809 * See Table C5-6 System instruction encodings for System register accesses, 2810 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2811 */ 2812 static inline bool __attribute_const__ is_emulated(u32 id) 2813 { 2814 return (sys_reg_Op0(id) == 0x3 && 2815 sys_reg_CRn(id) == 0x0 && 2816 sys_reg_Op1(id) == 0x0 && 2817 (sys_reg_CRm(id) == 0 || 2818 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2819 } 2820 2821 /* 2822 * With CRm == 0, reg should be one of : 2823 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2824 */ 2825 static inline int emulate_id_reg(u32 id, u64 *valp) 2826 { 2827 switch (id) { 2828 case SYS_MIDR_EL1: 2829 *valp = read_cpuid_id(); 2830 break; 2831 case SYS_MPIDR_EL1: 2832 *valp = SYS_MPIDR_SAFE_VAL; 2833 break; 2834 case SYS_REVIDR_EL1: 2835 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2836 *valp = 0; 2837 break; 2838 default: 2839 return -EINVAL; 2840 } 2841 2842 return 0; 2843 } 2844 2845 static int emulate_sys_reg(u32 id, u64 *valp) 2846 { 2847 struct arm64_ftr_reg *regp; 2848 2849 if (!is_emulated(id)) 2850 return -EINVAL; 2851 2852 if (sys_reg_CRm(id) == 0) 2853 return emulate_id_reg(id, valp); 2854 2855 regp = get_arm64_ftr_reg_nowarn(id); 2856 if (regp) 2857 *valp = arm64_ftr_reg_user_value(regp); 2858 else 2859 /* 2860 * The untracked registers are either IMPLEMENTATION DEFINED 2861 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2862 */ 2863 *valp = 0; 2864 return 0; 2865 } 2866 2867 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2868 { 2869 int rc; 2870 u64 val; 2871 2872 rc = emulate_sys_reg(sys_reg, &val); 2873 if (!rc) { 2874 pt_regs_write_reg(regs, rt, val); 2875 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2876 } 2877 return rc; 2878 } 2879 2880 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2881 { 2882 u32 sys_reg, rt; 2883 2884 /* 2885 * sys_reg values are defined as used in mrs/msr instruction. 2886 * shift the imm value to get the encoding. 2887 */ 2888 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2889 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2890 return do_emulate_mrs(regs, sys_reg, rt); 2891 } 2892 2893 static struct undef_hook mrs_hook = { 2894 .instr_mask = 0xfff00000, 2895 .instr_val = 0xd5300000, 2896 .pstate_mask = PSR_AA32_MODE_MASK, 2897 .pstate_val = PSR_MODE_EL0t, 2898 .fn = emulate_mrs, 2899 }; 2900 2901 static int __init enable_mrs_emulation(void) 2902 { 2903 register_undef_hook(&mrs_hook); 2904 return 0; 2905 } 2906 2907 core_initcall(enable_mrs_emulation); 2908 2909 enum mitigation_state arm64_get_meltdown_state(void) 2910 { 2911 if (__meltdown_safe) 2912 return SPECTRE_UNAFFECTED; 2913 2914 if (arm64_kernel_unmapped_at_el0()) 2915 return SPECTRE_MITIGATED; 2916 2917 return SPECTRE_VULNERABLE; 2918 } 2919 2920 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2921 char *buf) 2922 { 2923 switch (arm64_get_meltdown_state()) { 2924 case SPECTRE_UNAFFECTED: 2925 return sprintf(buf, "Not affected\n"); 2926 2927 case SPECTRE_MITIGATED: 2928 return sprintf(buf, "Mitigation: PTI\n"); 2929 2930 default: 2931 return sprintf(buf, "Vulnerable\n"); 2932 } 2933 } 2934