1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 */ 7 8 #define pr_fmt(fmt) "CPU features: " fmt 9 10 #include <linux/bsearch.h> 11 #include <linux/cpumask.h> 12 #include <linux/crash_dump.h> 13 #include <linux/sort.h> 14 #include <linux/stop_machine.h> 15 #include <linux/types.h> 16 #include <linux/mm.h> 17 #include <linux/cpu.h> 18 #include <asm/cpu.h> 19 #include <asm/cpufeature.h> 20 #include <asm/cpu_ops.h> 21 #include <asm/fpsimd.h> 22 #include <asm/mmu_context.h> 23 #include <asm/processor.h> 24 #include <asm/sysreg.h> 25 #include <asm/traps.h> 26 #include <asm/virt.h> 27 28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 29 static unsigned long elf_hwcap __read_mostly; 30 31 #ifdef CONFIG_COMPAT 32 #define COMPAT_ELF_HWCAP_DEFAULT \ 33 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 34 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 35 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 36 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 37 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 38 COMPAT_HWCAP_LPAE) 39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 40 unsigned int compat_elf_hwcap2 __read_mostly; 41 #endif 42 43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 44 EXPORT_SYMBOL(cpu_hwcaps); 45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 46 47 /* Need also bit for ARM64_CB_PATCH */ 48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 49 50 /* 51 * Flag to indicate if we have computed the system wide 52 * capabilities based on the boot time active CPUs. This 53 * will be used to determine if a new booting CPU should 54 * go through the verification process to make sure that it 55 * supports the system capabilities, without using a hotplug 56 * notifier. 57 */ 58 static bool sys_caps_initialised; 59 60 static inline void set_sys_caps_initialised(void) 61 { 62 sys_caps_initialised = true; 63 } 64 65 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) 66 { 67 /* file-wide pr_fmt adds "CPU features: " prefix */ 68 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 69 return 0; 70 } 71 72 static struct notifier_block cpu_hwcaps_notifier = { 73 .notifier_call = dump_cpu_hwcaps 74 }; 75 76 static int __init register_cpu_hwcaps_dumper(void) 77 { 78 atomic_notifier_chain_register(&panic_notifier_list, 79 &cpu_hwcaps_notifier); 80 return 0; 81 } 82 __initcall(register_cpu_hwcaps_dumper); 83 84 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 85 EXPORT_SYMBOL(cpu_hwcap_keys); 86 87 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 88 { \ 89 .sign = SIGNED, \ 90 .visible = VISIBLE, \ 91 .strict = STRICT, \ 92 .type = TYPE, \ 93 .shift = SHIFT, \ 94 .width = WIDTH, \ 95 .safe_val = SAFE_VAL, \ 96 } 97 98 /* Define a feature with unsigned values */ 99 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 100 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 101 102 /* Define a feature with a signed value */ 103 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 104 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 105 106 #define ARM64_FTR_END \ 107 { \ 108 .width = 0, \ 109 } 110 111 /* meta feature for alternatives */ 112 static bool __maybe_unused 113 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 114 115 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 116 117 /* 118 * NOTE: Any changes to the visibility of features should be kept in 119 * sync with the documentation of the CPU feature register ABI. 120 */ 121 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 122 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 123 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 124 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 125 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 134 ARM64_FTR_END, 135 }; 136 137 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 139 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 140 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 141 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 142 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 146 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 147 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), 148 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 149 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), 150 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 151 ARM64_FTR_END, 152 }; 153 154 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 155 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 157 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 158 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 159 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 162 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 163 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 164 /* Linux doesn't care about the EL3 */ 165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 169 ARM64_FTR_END, 170 }; 171 172 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 174 ARM64_FTR_END, 175 }; 176 177 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 183 ARM64_FTR_END, 184 }; 185 186 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 187 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 188 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 191 /* Linux shouldn't care about secure memory */ 192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 195 /* 196 * Differing PARange is fine as long as all peripherals and memory are mapped 197 * within the minimum PARange of all CPUs 198 */ 199 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 200 ARM64_FTR_END, 201 }; 202 203 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 210 ARM64_FTR_END, 211 }; 212 213 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 221 ARM64_FTR_END, 222 }; 223 224 static const struct arm64_ftr_bits ftr_ctr[] = { 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 231 /* 232 * Linux can handle differing I-cache policies. Userspace JITs will 233 * make use of *minLine. 234 * If we have differing I-cache policies, report it as the weakest - VIPT. 235 */ 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 238 ARM64_FTR_END, 239 }; 240 241 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 242 .name = "SYS_CTR_EL0", 243 .ftr_bits = ftr_ctr 244 }; 245 246 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 247 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */ 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */ 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */ 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */ 252 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */ 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */ 254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */ 255 ARM64_FTR_END, 256 }; 257 258 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 264 /* 265 * We can instantiate multiple PMU instances with different levels 266 * of support. 267 */ 268 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 271 ARM64_FTR_END, 272 }; 273 274 static const struct arm64_ftr_bits ftr_mvfr2[] = { 275 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */ 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */ 277 ARM64_FTR_END, 278 }; 279 280 static const struct arm64_ftr_bits ftr_dczid[] = { 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 282 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 283 ARM64_FTR_END, 284 }; 285 286 287 static const struct arm64_ftr_bits ftr_id_isar5[] = { 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 294 ARM64_FTR_END, 295 }; 296 297 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ 299 ARM64_FTR_END, 300 }; 301 302 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */ 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */ 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */ 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */ 307 ARM64_FTR_END, 308 }; 309 310 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 312 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 319 ARM64_FTR_END, 320 }; 321 322 static const struct arm64_ftr_bits ftr_zcr[] = { 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 324 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 325 ARM64_FTR_END, 326 }; 327 328 /* 329 * Common ftr bits for a 32bit register with all hidden, strict 330 * attributes, with 4bit feature fields and a default safe value of 331 * 0. Covers the following 32bit registers: 332 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 333 */ 334 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 343 ARM64_FTR_END, 344 }; 345 346 /* Table for a single 32bit feature value */ 347 static const struct arm64_ftr_bits ftr_single32[] = { 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 349 ARM64_FTR_END, 350 }; 351 352 static const struct arm64_ftr_bits ftr_raz[] = { 353 ARM64_FTR_END, 354 }; 355 356 #define ARM64_FTR_REG(id, table) { \ 357 .sys_id = id, \ 358 .reg = &(struct arm64_ftr_reg){ \ 359 .name = #id, \ 360 .ftr_bits = &((table)[0]), \ 361 }} 362 363 static const struct __ftr_reg_entry { 364 u32 sys_id; 365 struct arm64_ftr_reg *reg; 366 } arm64_ftr_regs[] = { 367 368 /* Op1 = 0, CRn = 0, CRm = 1 */ 369 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 370 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), 371 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 372 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 373 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 374 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 375 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 376 377 /* Op1 = 0, CRn = 0, CRm = 2 */ 378 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), 379 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 380 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 381 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 382 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), 383 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 384 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 385 386 /* Op1 = 0, CRn = 0, CRm = 3 */ 387 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 388 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 389 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 390 391 /* Op1 = 0, CRn = 0, CRm = 4 */ 392 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 393 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 394 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 395 396 /* Op1 = 0, CRn = 0, CRm = 5 */ 397 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 398 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 399 400 /* Op1 = 0, CRn = 0, CRm = 6 */ 401 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 402 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 403 404 /* Op1 = 0, CRn = 0, CRm = 7 */ 405 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 406 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 407 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 408 409 /* Op1 = 0, CRn = 1, CRm = 2 */ 410 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 411 412 /* Op1 = 3, CRn = 0, CRm = 0 */ 413 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 414 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 415 416 /* Op1 = 3, CRn = 14, CRm = 0 */ 417 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 418 }; 419 420 static int search_cmp_ftr_reg(const void *id, const void *regp) 421 { 422 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 423 } 424 425 /* 426 * get_arm64_ftr_reg - Lookup a feature register entry using its 427 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the 428 * ascending order of sys_id , we use binary search to find a matching 429 * entry. 430 * 431 * returns - Upon success, matching ftr_reg entry for id. 432 * - NULL on failure. It is upto the caller to decide 433 * the impact of a failure. 434 */ 435 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 436 { 437 const struct __ftr_reg_entry *ret; 438 439 ret = bsearch((const void *)(unsigned long)sys_id, 440 arm64_ftr_regs, 441 ARRAY_SIZE(arm64_ftr_regs), 442 sizeof(arm64_ftr_regs[0]), 443 search_cmp_ftr_reg); 444 if (ret) 445 return ret->reg; 446 return NULL; 447 } 448 449 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 450 s64 ftr_val) 451 { 452 u64 mask = arm64_ftr_mask(ftrp); 453 454 reg &= ~mask; 455 reg |= (ftr_val << ftrp->shift) & mask; 456 return reg; 457 } 458 459 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 460 s64 cur) 461 { 462 s64 ret = 0; 463 464 switch (ftrp->type) { 465 case FTR_EXACT: 466 ret = ftrp->safe_val; 467 break; 468 case FTR_LOWER_SAFE: 469 ret = new < cur ? new : cur; 470 break; 471 case FTR_HIGHER_OR_ZERO_SAFE: 472 if (!cur || !new) 473 break; 474 /* Fallthrough */ 475 case FTR_HIGHER_SAFE: 476 ret = new > cur ? new : cur; 477 break; 478 default: 479 BUG(); 480 } 481 482 return ret; 483 } 484 485 static void __init sort_ftr_regs(void) 486 { 487 int i; 488 489 /* Check that the array is sorted so that we can do the binary search */ 490 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 491 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 492 } 493 494 /* 495 * Initialise the CPU feature register from Boot CPU values. 496 * Also initiliases the strict_mask for the register. 497 * Any bits that are not covered by an arm64_ftr_bits entry are considered 498 * RES0 for the system-wide value, and must strictly match. 499 */ 500 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 501 { 502 u64 val = 0; 503 u64 strict_mask = ~0x0ULL; 504 u64 user_mask = 0; 505 u64 valid_mask = 0; 506 507 const struct arm64_ftr_bits *ftrp; 508 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 509 510 BUG_ON(!reg); 511 512 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 513 u64 ftr_mask = arm64_ftr_mask(ftrp); 514 s64 ftr_new = arm64_ftr_value(ftrp, new); 515 516 val = arm64_ftr_set_value(ftrp, val, ftr_new); 517 518 valid_mask |= ftr_mask; 519 if (!ftrp->strict) 520 strict_mask &= ~ftr_mask; 521 if (ftrp->visible) 522 user_mask |= ftr_mask; 523 else 524 reg->user_val = arm64_ftr_set_value(ftrp, 525 reg->user_val, 526 ftrp->safe_val); 527 } 528 529 val &= valid_mask; 530 531 reg->sys_val = val; 532 reg->strict_mask = strict_mask; 533 reg->user_mask = user_mask; 534 } 535 536 extern const struct arm64_cpu_capabilities arm64_errata[]; 537 static const struct arm64_cpu_capabilities arm64_features[]; 538 539 static void __init 540 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 541 { 542 for (; caps->matches; caps++) { 543 if (WARN(caps->capability >= ARM64_NCAPS, 544 "Invalid capability %d\n", caps->capability)) 545 continue; 546 if (WARN(cpu_hwcaps_ptrs[caps->capability], 547 "Duplicate entry for capability %d\n", 548 caps->capability)) 549 continue; 550 cpu_hwcaps_ptrs[caps->capability] = caps; 551 } 552 } 553 554 static void __init init_cpu_hwcaps_indirect_list(void) 555 { 556 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 557 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 558 } 559 560 static void __init setup_boot_cpu_capabilities(void); 561 562 void __init init_cpu_features(struct cpuinfo_arm64 *info) 563 { 564 /* Before we start using the tables, make sure it is sorted */ 565 sort_ftr_regs(); 566 567 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 568 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 569 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 570 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 571 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 572 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 573 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 574 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 575 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 576 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 577 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 578 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 579 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 580 581 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 582 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 583 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 584 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 585 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 586 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 587 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 588 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 589 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 590 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 591 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 592 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 593 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 594 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 595 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 596 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 597 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 598 } 599 600 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 601 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 602 sve_init_vq_map(); 603 } 604 605 /* 606 * Initialize the indirect array of CPU hwcaps capabilities pointers 607 * before we handle the boot CPU below. 608 */ 609 init_cpu_hwcaps_indirect_list(); 610 611 /* 612 * Detect and enable early CPU capabilities based on the boot CPU, 613 * after we have initialised the CPU feature infrastructure. 614 */ 615 setup_boot_cpu_capabilities(); 616 } 617 618 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 619 { 620 const struct arm64_ftr_bits *ftrp; 621 622 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 623 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 624 s64 ftr_new = arm64_ftr_value(ftrp, new); 625 626 if (ftr_cur == ftr_new) 627 continue; 628 /* Find a safe value */ 629 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 630 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 631 } 632 633 } 634 635 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 636 { 637 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 638 639 BUG_ON(!regp); 640 update_cpu_ftr_reg(regp, val); 641 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 642 return 0; 643 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 644 regp->name, boot, cpu, val); 645 return 1; 646 } 647 648 /* 649 * Update system wide CPU feature registers with the values from a 650 * non-boot CPU. Also performs SANITY checks to make sure that there 651 * aren't any insane variations from that of the boot CPU. 652 */ 653 void update_cpu_features(int cpu, 654 struct cpuinfo_arm64 *info, 655 struct cpuinfo_arm64 *boot) 656 { 657 int taint = 0; 658 659 /* 660 * The kernel can handle differing I-cache policies, but otherwise 661 * caches should look identical. Userspace JITs will make use of 662 * *minLine. 663 */ 664 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 665 info->reg_ctr, boot->reg_ctr); 666 667 /* 668 * Userspace may perform DC ZVA instructions. Mismatched block sizes 669 * could result in too much or too little memory being zeroed if a 670 * process is preempted and migrated between CPUs. 671 */ 672 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 673 info->reg_dczid, boot->reg_dczid); 674 675 /* If different, timekeeping will be broken (especially with KVM) */ 676 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 677 info->reg_cntfrq, boot->reg_cntfrq); 678 679 /* 680 * The kernel uses self-hosted debug features and expects CPUs to 681 * support identical debug features. We presently need CTX_CMPs, WRPs, 682 * and BRPs to be identical. 683 * ID_AA64DFR1 is currently RES0. 684 */ 685 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 686 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 687 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 688 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 689 /* 690 * Even in big.LITTLE, processors should be identical instruction-set 691 * wise. 692 */ 693 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 694 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 695 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 696 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 697 698 /* 699 * Differing PARange support is fine as long as all peripherals and 700 * memory are mapped within the minimum PARange of all CPUs. 701 * Linux should not care about secure memory. 702 */ 703 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 704 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 705 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 706 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 707 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 708 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 709 710 /* 711 * EL3 is not our concern. 712 */ 713 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 714 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 715 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 716 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 717 718 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 719 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 720 721 /* 722 * If we have AArch32, we care about 32-bit features for compat. 723 * If the system doesn't support AArch32, don't update them. 724 */ 725 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 726 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 727 728 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 729 info->reg_id_dfr0, boot->reg_id_dfr0); 730 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 731 info->reg_id_isar0, boot->reg_id_isar0); 732 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 733 info->reg_id_isar1, boot->reg_id_isar1); 734 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 735 info->reg_id_isar2, boot->reg_id_isar2); 736 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 737 info->reg_id_isar3, boot->reg_id_isar3); 738 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 739 info->reg_id_isar4, boot->reg_id_isar4); 740 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 741 info->reg_id_isar5, boot->reg_id_isar5); 742 743 /* 744 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 745 * ACTLR formats could differ across CPUs and therefore would have to 746 * be trapped for virtualization anyway. 747 */ 748 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 749 info->reg_id_mmfr0, boot->reg_id_mmfr0); 750 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 751 info->reg_id_mmfr1, boot->reg_id_mmfr1); 752 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 753 info->reg_id_mmfr2, boot->reg_id_mmfr2); 754 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 755 info->reg_id_mmfr3, boot->reg_id_mmfr3); 756 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 757 info->reg_id_pfr0, boot->reg_id_pfr0); 758 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 759 info->reg_id_pfr1, boot->reg_id_pfr1); 760 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 761 info->reg_mvfr0, boot->reg_mvfr0); 762 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 763 info->reg_mvfr1, boot->reg_mvfr1); 764 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 765 info->reg_mvfr2, boot->reg_mvfr2); 766 } 767 768 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 769 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 770 info->reg_zcr, boot->reg_zcr); 771 772 /* Probe vector lengths, unless we already gave up on SVE */ 773 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 774 !sys_caps_initialised) 775 sve_update_vq_map(); 776 } 777 778 /* 779 * Mismatched CPU features are a recipe for disaster. Don't even 780 * pretend to support them. 781 */ 782 if (taint) { 783 pr_warn_once("Unsupported CPU feature variation detected.\n"); 784 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 785 } 786 } 787 788 u64 read_sanitised_ftr_reg(u32 id) 789 { 790 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 791 792 /* We shouldn't get a request for an unsupported register */ 793 BUG_ON(!regp); 794 return regp->sys_val; 795 } 796 797 #define read_sysreg_case(r) \ 798 case r: return read_sysreg_s(r) 799 800 /* 801 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 802 * Read the system register on the current CPU 803 */ 804 static u64 __read_sysreg_by_encoding(u32 sys_id) 805 { 806 switch (sys_id) { 807 read_sysreg_case(SYS_ID_PFR0_EL1); 808 read_sysreg_case(SYS_ID_PFR1_EL1); 809 read_sysreg_case(SYS_ID_DFR0_EL1); 810 read_sysreg_case(SYS_ID_MMFR0_EL1); 811 read_sysreg_case(SYS_ID_MMFR1_EL1); 812 read_sysreg_case(SYS_ID_MMFR2_EL1); 813 read_sysreg_case(SYS_ID_MMFR3_EL1); 814 read_sysreg_case(SYS_ID_ISAR0_EL1); 815 read_sysreg_case(SYS_ID_ISAR1_EL1); 816 read_sysreg_case(SYS_ID_ISAR2_EL1); 817 read_sysreg_case(SYS_ID_ISAR3_EL1); 818 read_sysreg_case(SYS_ID_ISAR4_EL1); 819 read_sysreg_case(SYS_ID_ISAR5_EL1); 820 read_sysreg_case(SYS_MVFR0_EL1); 821 read_sysreg_case(SYS_MVFR1_EL1); 822 read_sysreg_case(SYS_MVFR2_EL1); 823 824 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 825 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 826 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 827 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 828 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 829 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 830 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 831 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 832 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 833 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 834 835 read_sysreg_case(SYS_CNTFRQ_EL0); 836 read_sysreg_case(SYS_CTR_EL0); 837 read_sysreg_case(SYS_DCZID_EL0); 838 839 default: 840 BUG(); 841 return 0; 842 } 843 } 844 845 #include <linux/irqchip/arm-gic-v3.h> 846 847 static bool 848 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 849 { 850 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 851 852 return val >= entry->min_field_value; 853 } 854 855 static bool 856 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 857 { 858 u64 val; 859 860 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 861 if (scope == SCOPE_SYSTEM) 862 val = read_sanitised_ftr_reg(entry->sys_reg); 863 else 864 val = __read_sysreg_by_encoding(entry->sys_reg); 865 866 return feature_matches(val, entry); 867 } 868 869 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 870 { 871 bool has_sre; 872 873 if (!has_cpuid_feature(entry, scope)) 874 return false; 875 876 has_sre = gic_enable_sre(); 877 if (!has_sre) 878 pr_warn_once("%s present but disabled by higher exception level\n", 879 entry->desc); 880 881 return has_sre; 882 } 883 884 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 885 { 886 u32 midr = read_cpuid_id(); 887 888 /* Cavium ThunderX pass 1.x and 2.x */ 889 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, 890 MIDR_CPU_VAR_REV(0, 0), 891 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 892 } 893 894 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 895 { 896 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 897 898 return cpuid_feature_extract_signed_field(pfr0, 899 ID_AA64PFR0_FP_SHIFT) < 0; 900 } 901 902 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 903 int scope) 904 { 905 u64 ctr; 906 907 if (scope == SCOPE_SYSTEM) 908 ctr = arm64_ftr_reg_ctrel0.sys_val; 909 else 910 ctr = read_cpuid_effective_cachetype(); 911 912 return ctr & BIT(CTR_IDC_SHIFT); 913 } 914 915 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 916 { 917 /* 918 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 919 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 920 * to the CTR_EL0 on this CPU and emulate it with the real/safe 921 * value. 922 */ 923 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 924 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 925 } 926 927 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 928 int scope) 929 { 930 u64 ctr; 931 932 if (scope == SCOPE_SYSTEM) 933 ctr = arm64_ftr_reg_ctrel0.sys_val; 934 else 935 ctr = read_cpuid_cachetype(); 936 937 return ctr & BIT(CTR_DIC_SHIFT); 938 } 939 940 static bool __maybe_unused 941 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 942 { 943 /* 944 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 945 * may share TLB entries with a CPU stuck in the crashed 946 * kernel. 947 */ 948 if (is_kdump_kernel()) 949 return false; 950 951 return has_cpuid_feature(entry, scope); 952 } 953 954 static bool __meltdown_safe = true; 955 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 956 957 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 958 int scope) 959 { 960 /* List of CPUs that are not vulnerable and don't need KPTI */ 961 static const struct midr_range kpti_safe_list[] = { 962 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 963 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 964 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 965 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 966 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 967 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 968 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 969 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 970 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 971 { /* sentinel */ } 972 }; 973 char const *str = "kpti command line option"; 974 bool meltdown_safe; 975 976 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 977 978 /* Defer to CPU feature registers */ 979 if (has_cpuid_feature(entry, scope)) 980 meltdown_safe = true; 981 982 if (!meltdown_safe) 983 __meltdown_safe = false; 984 985 /* 986 * For reasons that aren't entirely clear, enabling KPTI on Cavium 987 * ThunderX leads to apparent I-cache corruption of kernel text, which 988 * ends as well as you might imagine. Don't even try. 989 */ 990 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 991 str = "ARM64_WORKAROUND_CAVIUM_27456"; 992 __kpti_forced = -1; 993 } 994 995 /* Useful for KASLR robustness */ 996 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) { 997 if (!__kpti_forced) { 998 str = "KASLR"; 999 __kpti_forced = 1; 1000 } 1001 } 1002 1003 if (cpu_mitigations_off() && !__kpti_forced) { 1004 str = "mitigations=off"; 1005 __kpti_forced = -1; 1006 } 1007 1008 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1009 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1010 return false; 1011 } 1012 1013 /* Forced? */ 1014 if (__kpti_forced) { 1015 pr_info_once("kernel page table isolation forced %s by %s\n", 1016 __kpti_forced > 0 ? "ON" : "OFF", str); 1017 return __kpti_forced > 0; 1018 } 1019 1020 return !meltdown_safe; 1021 } 1022 1023 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1024 static void 1025 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1026 { 1027 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1028 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1029 kpti_remap_fn *remap_fn; 1030 1031 static bool kpti_applied = false; 1032 int cpu = smp_processor_id(); 1033 1034 /* 1035 * We don't need to rewrite the page-tables if either we've done 1036 * it already or we have KASLR enabled and therefore have not 1037 * created any global mappings at all. 1038 */ 1039 if (kpti_applied || kaslr_offset() > 0) 1040 return; 1041 1042 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1043 1044 cpu_install_idmap(); 1045 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1046 cpu_uninstall_idmap(); 1047 1048 if (!cpu) 1049 kpti_applied = true; 1050 1051 return; 1052 } 1053 #else 1054 static void 1055 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1056 { 1057 } 1058 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1059 1060 static int __init parse_kpti(char *str) 1061 { 1062 bool enabled; 1063 int ret = strtobool(str, &enabled); 1064 1065 if (ret) 1066 return ret; 1067 1068 __kpti_forced = enabled ? 1 : -1; 1069 return 0; 1070 } 1071 early_param("kpti", parse_kpti); 1072 1073 #ifdef CONFIG_ARM64_HW_AFDBM 1074 static inline void __cpu_enable_hw_dbm(void) 1075 { 1076 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1077 1078 write_sysreg(tcr, tcr_el1); 1079 isb(); 1080 } 1081 1082 static bool cpu_has_broken_dbm(void) 1083 { 1084 /* List of CPUs which have broken DBM support. */ 1085 static const struct midr_range cpus[] = { 1086 #ifdef CONFIG_ARM64_ERRATUM_1024718 1087 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1088 #endif 1089 {}, 1090 }; 1091 1092 return is_midr_in_range_list(read_cpuid_id(), cpus); 1093 } 1094 1095 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1096 { 1097 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1098 !cpu_has_broken_dbm(); 1099 } 1100 1101 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1102 { 1103 if (cpu_can_use_dbm(cap)) 1104 __cpu_enable_hw_dbm(); 1105 } 1106 1107 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1108 int __unused) 1109 { 1110 static bool detected = false; 1111 /* 1112 * DBM is a non-conflicting feature. i.e, the kernel can safely 1113 * run a mix of CPUs with and without the feature. So, we 1114 * unconditionally enable the capability to allow any late CPU 1115 * to use the feature. We only enable the control bits on the 1116 * CPU, if it actually supports. 1117 * 1118 * We have to make sure we print the "feature" detection only 1119 * when at least one CPU actually uses it. So check if this CPU 1120 * can actually use it and print the message exactly once. 1121 * 1122 * This is safe as all CPUs (including secondary CPUs - due to the 1123 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1124 * goes through the "matches" check exactly once. Also if a CPU 1125 * matches the criteria, it is guaranteed that the CPU will turn 1126 * the DBM on, as the capability is unconditionally enabled. 1127 */ 1128 if (!detected && cpu_can_use_dbm(cap)) { 1129 detected = true; 1130 pr_info("detected: Hardware dirty bit management\n"); 1131 } 1132 1133 return true; 1134 } 1135 1136 #endif 1137 1138 #ifdef CONFIG_ARM64_VHE 1139 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1140 { 1141 return is_kernel_in_hyp_mode(); 1142 } 1143 1144 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1145 { 1146 /* 1147 * Copy register values that aren't redirected by hardware. 1148 * 1149 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1150 * this value to tpidr_el2 before we patch the code. Once we've done 1151 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1152 * do anything here. 1153 */ 1154 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1155 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1156 } 1157 #endif 1158 1159 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1160 { 1161 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1162 1163 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1164 WARN_ON(val & (7 << 27 | 7 << 21)); 1165 } 1166 1167 #ifdef CONFIG_ARM64_SSBD 1168 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) 1169 { 1170 if (user_mode(regs)) 1171 return 1; 1172 1173 if (instr & BIT(PSTATE_Imm_shift)) 1174 regs->pstate |= PSR_SSBS_BIT; 1175 else 1176 regs->pstate &= ~PSR_SSBS_BIT; 1177 1178 arm64_skip_faulting_instruction(regs, 4); 1179 return 0; 1180 } 1181 1182 static struct undef_hook ssbs_emulation_hook = { 1183 .instr_mask = ~(1U << PSTATE_Imm_shift), 1184 .instr_val = 0xd500401f | PSTATE_SSBS, 1185 .fn = ssbs_emulation_handler, 1186 }; 1187 1188 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) 1189 { 1190 static bool undef_hook_registered = false; 1191 static DEFINE_RAW_SPINLOCK(hook_lock); 1192 1193 raw_spin_lock(&hook_lock); 1194 if (!undef_hook_registered) { 1195 register_undef_hook(&ssbs_emulation_hook); 1196 undef_hook_registered = true; 1197 } 1198 raw_spin_unlock(&hook_lock); 1199 1200 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { 1201 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS); 1202 arm64_set_ssbd_mitigation(false); 1203 } else { 1204 arm64_set_ssbd_mitigation(true); 1205 } 1206 } 1207 #endif /* CONFIG_ARM64_SSBD */ 1208 1209 #ifdef CONFIG_ARM64_PAN 1210 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1211 { 1212 /* 1213 * We modify PSTATE. This won't work from irq context as the PSTATE 1214 * is discarded once we return from the exception. 1215 */ 1216 WARN_ON_ONCE(in_interrupt()); 1217 1218 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1219 asm(SET_PSTATE_PAN(1)); 1220 } 1221 #endif /* CONFIG_ARM64_PAN */ 1222 1223 #ifdef CONFIG_ARM64_RAS_EXTN 1224 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1225 { 1226 /* Firmware may have left a deferred SError in this register. */ 1227 write_sysreg_s(0, SYS_DISR_EL1); 1228 } 1229 #endif /* CONFIG_ARM64_RAS_EXTN */ 1230 1231 #ifdef CONFIG_ARM64_PTR_AUTH 1232 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap) 1233 { 1234 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | 1235 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB); 1236 } 1237 #endif /* CONFIG_ARM64_PTR_AUTH */ 1238 1239 #ifdef CONFIG_ARM64_PSEUDO_NMI 1240 static bool enable_pseudo_nmi; 1241 1242 static int __init early_enable_pseudo_nmi(char *p) 1243 { 1244 return strtobool(p, &enable_pseudo_nmi); 1245 } 1246 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1247 1248 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1249 int scope) 1250 { 1251 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1252 } 1253 #endif 1254 1255 static const struct arm64_cpu_capabilities arm64_features[] = { 1256 { 1257 .desc = "GIC system register CPU interface", 1258 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1259 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1260 .matches = has_useable_gicv3_cpuif, 1261 .sys_reg = SYS_ID_AA64PFR0_EL1, 1262 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1263 .sign = FTR_UNSIGNED, 1264 .min_field_value = 1, 1265 }, 1266 #ifdef CONFIG_ARM64_PAN 1267 { 1268 .desc = "Privileged Access Never", 1269 .capability = ARM64_HAS_PAN, 1270 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1271 .matches = has_cpuid_feature, 1272 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1273 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1274 .sign = FTR_UNSIGNED, 1275 .min_field_value = 1, 1276 .cpu_enable = cpu_enable_pan, 1277 }, 1278 #endif /* CONFIG_ARM64_PAN */ 1279 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) 1280 { 1281 .desc = "LSE atomic instructions", 1282 .capability = ARM64_HAS_LSE_ATOMICS, 1283 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1284 .matches = has_cpuid_feature, 1285 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1286 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1287 .sign = FTR_UNSIGNED, 1288 .min_field_value = 2, 1289 }, 1290 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ 1291 { 1292 .desc = "Software prefetching using PRFM", 1293 .capability = ARM64_HAS_NO_HW_PREFETCH, 1294 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1295 .matches = has_no_hw_prefetch, 1296 }, 1297 #ifdef CONFIG_ARM64_UAO 1298 { 1299 .desc = "User Access Override", 1300 .capability = ARM64_HAS_UAO, 1301 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1302 .matches = has_cpuid_feature, 1303 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1304 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 1305 .min_field_value = 1, 1306 /* 1307 * We rely on stop_machine() calling uao_thread_switch() to set 1308 * UAO immediately after patching. 1309 */ 1310 }, 1311 #endif /* CONFIG_ARM64_UAO */ 1312 #ifdef CONFIG_ARM64_PAN 1313 { 1314 .capability = ARM64_ALT_PAN_NOT_UAO, 1315 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1316 .matches = cpufeature_pan_not_uao, 1317 }, 1318 #endif /* CONFIG_ARM64_PAN */ 1319 #ifdef CONFIG_ARM64_VHE 1320 { 1321 .desc = "Virtualization Host Extensions", 1322 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1323 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1324 .matches = runs_at_el2, 1325 .cpu_enable = cpu_copy_el2regs, 1326 }, 1327 #endif /* CONFIG_ARM64_VHE */ 1328 { 1329 .desc = "32-bit EL0 Support", 1330 .capability = ARM64_HAS_32BIT_EL0, 1331 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1332 .matches = has_cpuid_feature, 1333 .sys_reg = SYS_ID_AA64PFR0_EL1, 1334 .sign = FTR_UNSIGNED, 1335 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1336 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1337 }, 1338 { 1339 .desc = "Kernel page table isolation (KPTI)", 1340 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1341 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1342 /* 1343 * The ID feature fields below are used to indicate that 1344 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1345 * more details. 1346 */ 1347 .sys_reg = SYS_ID_AA64PFR0_EL1, 1348 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1349 .min_field_value = 1, 1350 .matches = unmap_kernel_at_el0, 1351 .cpu_enable = kpti_install_ng_mappings, 1352 }, 1353 { 1354 /* FP/SIMD is not implemented */ 1355 .capability = ARM64_HAS_NO_FPSIMD, 1356 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1357 .min_field_value = 0, 1358 .matches = has_no_fpsimd, 1359 }, 1360 #ifdef CONFIG_ARM64_PMEM 1361 { 1362 .desc = "Data cache clean to Point of Persistence", 1363 .capability = ARM64_HAS_DCPOP, 1364 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1365 .matches = has_cpuid_feature, 1366 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1367 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1368 .min_field_value = 1, 1369 }, 1370 { 1371 .desc = "Data cache clean to Point of Deep Persistence", 1372 .capability = ARM64_HAS_DCPODP, 1373 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1374 .matches = has_cpuid_feature, 1375 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1376 .sign = FTR_UNSIGNED, 1377 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1378 .min_field_value = 2, 1379 }, 1380 #endif 1381 #ifdef CONFIG_ARM64_SVE 1382 { 1383 .desc = "Scalable Vector Extension", 1384 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1385 .capability = ARM64_SVE, 1386 .sys_reg = SYS_ID_AA64PFR0_EL1, 1387 .sign = FTR_UNSIGNED, 1388 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1389 .min_field_value = ID_AA64PFR0_SVE, 1390 .matches = has_cpuid_feature, 1391 .cpu_enable = sve_kernel_enable, 1392 }, 1393 #endif /* CONFIG_ARM64_SVE */ 1394 #ifdef CONFIG_ARM64_RAS_EXTN 1395 { 1396 .desc = "RAS Extension Support", 1397 .capability = ARM64_HAS_RAS_EXTN, 1398 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1399 .matches = has_cpuid_feature, 1400 .sys_reg = SYS_ID_AA64PFR0_EL1, 1401 .sign = FTR_UNSIGNED, 1402 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1403 .min_field_value = ID_AA64PFR0_RAS_V1, 1404 .cpu_enable = cpu_clear_disr, 1405 }, 1406 #endif /* CONFIG_ARM64_RAS_EXTN */ 1407 { 1408 .desc = "Data cache clean to the PoU not required for I/D coherence", 1409 .capability = ARM64_HAS_CACHE_IDC, 1410 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1411 .matches = has_cache_idc, 1412 .cpu_enable = cpu_emulate_effective_ctr, 1413 }, 1414 { 1415 .desc = "Instruction cache invalidation not required for I/D coherence", 1416 .capability = ARM64_HAS_CACHE_DIC, 1417 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1418 .matches = has_cache_dic, 1419 }, 1420 { 1421 .desc = "Stage-2 Force Write-Back", 1422 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1423 .capability = ARM64_HAS_STAGE2_FWB, 1424 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1425 .sign = FTR_UNSIGNED, 1426 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1427 .min_field_value = 1, 1428 .matches = has_cpuid_feature, 1429 .cpu_enable = cpu_has_fwb, 1430 }, 1431 #ifdef CONFIG_ARM64_HW_AFDBM 1432 { 1433 /* 1434 * Since we turn this on always, we don't want the user to 1435 * think that the feature is available when it may not be. 1436 * So hide the description. 1437 * 1438 * .desc = "Hardware pagetable Dirty Bit Management", 1439 * 1440 */ 1441 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1442 .capability = ARM64_HW_DBM, 1443 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1444 .sign = FTR_UNSIGNED, 1445 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1446 .min_field_value = 2, 1447 .matches = has_hw_dbm, 1448 .cpu_enable = cpu_enable_hw_dbm, 1449 }, 1450 #endif 1451 { 1452 .desc = "CRC32 instructions", 1453 .capability = ARM64_HAS_CRC32, 1454 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1455 .matches = has_cpuid_feature, 1456 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1457 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1458 .min_field_value = 1, 1459 }, 1460 #ifdef CONFIG_ARM64_SSBD 1461 { 1462 .desc = "Speculative Store Bypassing Safe (SSBS)", 1463 .capability = ARM64_SSBS, 1464 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1465 .matches = has_cpuid_feature, 1466 .sys_reg = SYS_ID_AA64PFR1_EL1, 1467 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1468 .sign = FTR_UNSIGNED, 1469 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1470 .cpu_enable = cpu_enable_ssbs, 1471 }, 1472 #endif 1473 #ifdef CONFIG_ARM64_CNP 1474 { 1475 .desc = "Common not Private translations", 1476 .capability = ARM64_HAS_CNP, 1477 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1478 .matches = has_useable_cnp, 1479 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1480 .sign = FTR_UNSIGNED, 1481 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 1482 .min_field_value = 1, 1483 .cpu_enable = cpu_enable_cnp, 1484 }, 1485 #endif 1486 { 1487 .desc = "Speculation barrier (SB)", 1488 .capability = ARM64_HAS_SB, 1489 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1490 .matches = has_cpuid_feature, 1491 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1492 .field_pos = ID_AA64ISAR1_SB_SHIFT, 1493 .sign = FTR_UNSIGNED, 1494 .min_field_value = 1, 1495 }, 1496 #ifdef CONFIG_ARM64_PTR_AUTH 1497 { 1498 .desc = "Address authentication (architected algorithm)", 1499 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 1500 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1501 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1502 .sign = FTR_UNSIGNED, 1503 .field_pos = ID_AA64ISAR1_APA_SHIFT, 1504 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 1505 .matches = has_cpuid_feature, 1506 .cpu_enable = cpu_enable_address_auth, 1507 }, 1508 { 1509 .desc = "Address authentication (IMP DEF algorithm)", 1510 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 1511 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1512 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1513 .sign = FTR_UNSIGNED, 1514 .field_pos = ID_AA64ISAR1_API_SHIFT, 1515 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 1516 .matches = has_cpuid_feature, 1517 .cpu_enable = cpu_enable_address_auth, 1518 }, 1519 { 1520 .desc = "Generic authentication (architected algorithm)", 1521 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 1522 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1523 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1524 .sign = FTR_UNSIGNED, 1525 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 1526 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 1527 .matches = has_cpuid_feature, 1528 }, 1529 { 1530 .desc = "Generic authentication (IMP DEF algorithm)", 1531 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 1532 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1533 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1534 .sign = FTR_UNSIGNED, 1535 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 1536 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 1537 .matches = has_cpuid_feature, 1538 }, 1539 #endif /* CONFIG_ARM64_PTR_AUTH */ 1540 #ifdef CONFIG_ARM64_PSEUDO_NMI 1541 { 1542 /* 1543 * Depends on having GICv3 1544 */ 1545 .desc = "IRQ priority masking", 1546 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 1547 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1548 .matches = can_use_gic_priorities, 1549 .sys_reg = SYS_ID_AA64PFR0_EL1, 1550 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1551 .sign = FTR_UNSIGNED, 1552 .min_field_value = 1, 1553 }, 1554 #endif 1555 {}, 1556 }; 1557 1558 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1559 .matches = has_cpuid_feature, \ 1560 .sys_reg = reg, \ 1561 .field_pos = field, \ 1562 .sign = s, \ 1563 .min_field_value = min_value, 1564 1565 #define __HWCAP_CAP(name, cap_type, cap) \ 1566 .desc = name, \ 1567 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 1568 .hwcap_type = cap_type, \ 1569 .hwcap = cap, \ 1570 1571 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 1572 { \ 1573 __HWCAP_CAP(#cap, cap_type, cap) \ 1574 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1575 } 1576 1577 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 1578 { \ 1579 __HWCAP_CAP(#cap, cap_type, cap) \ 1580 .matches = cpucap_multi_entry_cap_matches, \ 1581 .match_list = list, \ 1582 } 1583 1584 #ifdef CONFIG_ARM64_PTR_AUTH 1585 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 1586 { 1587 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 1588 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 1589 }, 1590 { 1591 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 1592 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 1593 }, 1594 {}, 1595 }; 1596 1597 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 1598 { 1599 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 1600 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 1601 }, 1602 { 1603 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 1604 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 1605 }, 1606 {}, 1607 }; 1608 #endif 1609 1610 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 1611 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 1612 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 1613 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 1614 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 1615 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 1616 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 1617 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 1618 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 1619 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 1620 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 1621 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 1622 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 1623 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 1624 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 1625 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 1626 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 1627 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 1628 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 1629 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 1630 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 1631 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 1632 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 1633 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 1634 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 1635 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 1636 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 1637 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 1638 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 1639 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 1640 #ifdef CONFIG_ARM64_SVE 1641 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 1642 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 1643 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 1644 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 1645 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 1646 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 1647 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 1648 #endif 1649 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 1650 #ifdef CONFIG_ARM64_PTR_AUTH 1651 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 1652 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 1653 #endif 1654 {}, 1655 }; 1656 1657 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 1658 #ifdef CONFIG_COMPAT 1659 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 1660 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 1661 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 1662 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 1663 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 1664 #endif 1665 {}, 1666 }; 1667 1668 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1669 { 1670 switch (cap->hwcap_type) { 1671 case CAP_HWCAP: 1672 cpu_set_feature(cap->hwcap); 1673 break; 1674 #ifdef CONFIG_COMPAT 1675 case CAP_COMPAT_HWCAP: 1676 compat_elf_hwcap |= (u32)cap->hwcap; 1677 break; 1678 case CAP_COMPAT_HWCAP2: 1679 compat_elf_hwcap2 |= (u32)cap->hwcap; 1680 break; 1681 #endif 1682 default: 1683 WARN_ON(1); 1684 break; 1685 } 1686 } 1687 1688 /* Check if we have a particular HWCAP enabled */ 1689 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1690 { 1691 bool rc; 1692 1693 switch (cap->hwcap_type) { 1694 case CAP_HWCAP: 1695 rc = cpu_have_feature(cap->hwcap); 1696 break; 1697 #ifdef CONFIG_COMPAT 1698 case CAP_COMPAT_HWCAP: 1699 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 1700 break; 1701 case CAP_COMPAT_HWCAP2: 1702 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 1703 break; 1704 #endif 1705 default: 1706 WARN_ON(1); 1707 rc = false; 1708 } 1709 1710 return rc; 1711 } 1712 1713 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 1714 { 1715 /* We support emulation of accesses to CPU ID feature registers */ 1716 cpu_set_named_feature(CPUID); 1717 for (; hwcaps->matches; hwcaps++) 1718 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 1719 cap_set_elf_hwcap(hwcaps); 1720 } 1721 1722 static void update_cpu_capabilities(u16 scope_mask) 1723 { 1724 int i; 1725 const struct arm64_cpu_capabilities *caps; 1726 1727 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1728 for (i = 0; i < ARM64_NCAPS; i++) { 1729 caps = cpu_hwcaps_ptrs[i]; 1730 if (!caps || !(caps->type & scope_mask) || 1731 cpus_have_cap(caps->capability) || 1732 !caps->matches(caps, cpucap_default_scope(caps))) 1733 continue; 1734 1735 if (caps->desc) 1736 pr_info("detected: %s\n", caps->desc); 1737 cpus_set_cap(caps->capability); 1738 1739 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 1740 set_bit(caps->capability, boot_capabilities); 1741 } 1742 } 1743 1744 /* 1745 * Enable all the available capabilities on this CPU. The capabilities 1746 * with BOOT_CPU scope are handled separately and hence skipped here. 1747 */ 1748 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 1749 { 1750 int i; 1751 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 1752 1753 for_each_available_cap(i) { 1754 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 1755 1756 if (WARN_ON(!cap)) 1757 continue; 1758 1759 if (!(cap->type & non_boot_scope)) 1760 continue; 1761 1762 if (cap->cpu_enable) 1763 cap->cpu_enable(cap); 1764 } 1765 return 0; 1766 } 1767 1768 /* 1769 * Run through the enabled capabilities and enable() it on all active 1770 * CPUs 1771 */ 1772 static void __init enable_cpu_capabilities(u16 scope_mask) 1773 { 1774 int i; 1775 const struct arm64_cpu_capabilities *caps; 1776 bool boot_scope; 1777 1778 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1779 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 1780 1781 for (i = 0; i < ARM64_NCAPS; i++) { 1782 unsigned int num; 1783 1784 caps = cpu_hwcaps_ptrs[i]; 1785 if (!caps || !(caps->type & scope_mask)) 1786 continue; 1787 num = caps->capability; 1788 if (!cpus_have_cap(num)) 1789 continue; 1790 1791 /* Ensure cpus_have_const_cap(num) works */ 1792 static_branch_enable(&cpu_hwcap_keys[num]); 1793 1794 if (boot_scope && caps->cpu_enable) 1795 /* 1796 * Capabilities with SCOPE_BOOT_CPU scope are finalised 1797 * before any secondary CPU boots. Thus, each secondary 1798 * will enable the capability as appropriate via 1799 * check_local_cpu_capabilities(). The only exception is 1800 * the boot CPU, for which the capability must be 1801 * enabled here. This approach avoids costly 1802 * stop_machine() calls for this case. 1803 */ 1804 caps->cpu_enable(caps); 1805 } 1806 1807 /* 1808 * For all non-boot scope capabilities, use stop_machine() 1809 * as it schedules the work allowing us to modify PSTATE, 1810 * instead of on_each_cpu() which uses an IPI, giving us a 1811 * PSTATE that disappears when we return. 1812 */ 1813 if (!boot_scope) 1814 stop_machine(cpu_enable_non_boot_scope_capabilities, 1815 NULL, cpu_online_mask); 1816 } 1817 1818 /* 1819 * Run through the list of capabilities to check for conflicts. 1820 * If the system has already detected a capability, take necessary 1821 * action on this CPU. 1822 * 1823 * Returns "false" on conflicts. 1824 */ 1825 static bool verify_local_cpu_caps(u16 scope_mask) 1826 { 1827 int i; 1828 bool cpu_has_cap, system_has_cap; 1829 const struct arm64_cpu_capabilities *caps; 1830 1831 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1832 1833 for (i = 0; i < ARM64_NCAPS; i++) { 1834 caps = cpu_hwcaps_ptrs[i]; 1835 if (!caps || !(caps->type & scope_mask)) 1836 continue; 1837 1838 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 1839 system_has_cap = cpus_have_cap(caps->capability); 1840 1841 if (system_has_cap) { 1842 /* 1843 * Check if the new CPU misses an advertised feature, 1844 * which is not safe to miss. 1845 */ 1846 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 1847 break; 1848 /* 1849 * We have to issue cpu_enable() irrespective of 1850 * whether the CPU has it or not, as it is enabeld 1851 * system wide. It is upto the call back to take 1852 * appropriate action on this CPU. 1853 */ 1854 if (caps->cpu_enable) 1855 caps->cpu_enable(caps); 1856 } else { 1857 /* 1858 * Check if the CPU has this capability if it isn't 1859 * safe to have when the system doesn't. 1860 */ 1861 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 1862 break; 1863 } 1864 } 1865 1866 if (i < ARM64_NCAPS) { 1867 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 1868 smp_processor_id(), caps->capability, 1869 caps->desc, system_has_cap, cpu_has_cap); 1870 return false; 1871 } 1872 1873 return true; 1874 } 1875 1876 /* 1877 * Check for CPU features that are used in early boot 1878 * based on the Boot CPU value. 1879 */ 1880 static void check_early_cpu_features(void) 1881 { 1882 verify_cpu_asid_bits(); 1883 /* 1884 * Early features are used by the kernel already. If there 1885 * is a conflict, we cannot proceed further. 1886 */ 1887 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU)) 1888 cpu_panic_kernel(); 1889 } 1890 1891 static void 1892 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 1893 { 1894 1895 for (; caps->matches; caps++) 1896 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 1897 pr_crit("CPU%d: missing HWCAP: %s\n", 1898 smp_processor_id(), caps->desc); 1899 cpu_die_early(); 1900 } 1901 } 1902 1903 static void verify_sve_features(void) 1904 { 1905 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 1906 u64 zcr = read_zcr_features(); 1907 1908 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 1909 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 1910 1911 if (len < safe_len || sve_verify_vq_map()) { 1912 pr_crit("CPU%d: SVE: vector length support mismatch\n", 1913 smp_processor_id()); 1914 cpu_die_early(); 1915 } 1916 1917 /* Add checks on other ZCR bits here if necessary */ 1918 } 1919 1920 1921 /* 1922 * Run through the enabled system capabilities and enable() it on this CPU. 1923 * The capabilities were decided based on the available CPUs at the boot time. 1924 * Any new CPU should match the system wide status of the capability. If the 1925 * new CPU doesn't have a capability which the system now has enabled, we 1926 * cannot do anything to fix it up and could cause unexpected failures. So 1927 * we park the CPU. 1928 */ 1929 static void verify_local_cpu_capabilities(void) 1930 { 1931 /* 1932 * The capabilities with SCOPE_BOOT_CPU are checked from 1933 * check_early_cpu_features(), as they need to be verified 1934 * on all secondary CPUs. 1935 */ 1936 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU)) 1937 cpu_die_early(); 1938 1939 verify_local_elf_hwcaps(arm64_elf_hwcaps); 1940 1941 if (system_supports_32bit_el0()) 1942 verify_local_elf_hwcaps(compat_elf_hwcaps); 1943 1944 if (system_supports_sve()) 1945 verify_sve_features(); 1946 } 1947 1948 void check_local_cpu_capabilities(void) 1949 { 1950 /* 1951 * All secondary CPUs should conform to the early CPU features 1952 * in use by the kernel based on boot CPU. 1953 */ 1954 check_early_cpu_features(); 1955 1956 /* 1957 * If we haven't finalised the system capabilities, this CPU gets 1958 * a chance to update the errata work arounds and local features. 1959 * Otherwise, this CPU should verify that it has all the system 1960 * advertised capabilities. 1961 */ 1962 if (!sys_caps_initialised) 1963 update_cpu_capabilities(SCOPE_LOCAL_CPU); 1964 else 1965 verify_local_cpu_capabilities(); 1966 } 1967 1968 static void __init setup_boot_cpu_capabilities(void) 1969 { 1970 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 1971 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 1972 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 1973 enable_cpu_capabilities(SCOPE_BOOT_CPU); 1974 } 1975 1976 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 1977 EXPORT_SYMBOL(arm64_const_caps_ready); 1978 1979 static void __init mark_const_caps_ready(void) 1980 { 1981 static_branch_enable(&arm64_const_caps_ready); 1982 } 1983 1984 bool this_cpu_has_cap(unsigned int n) 1985 { 1986 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 1987 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 1988 1989 if (cap) 1990 return cap->matches(cap, SCOPE_LOCAL_CPU); 1991 } 1992 1993 return false; 1994 } 1995 1996 void cpu_set_feature(unsigned int num) 1997 { 1998 WARN_ON(num >= MAX_CPU_FEATURES); 1999 elf_hwcap |= BIT(num); 2000 } 2001 EXPORT_SYMBOL_GPL(cpu_set_feature); 2002 2003 bool cpu_have_feature(unsigned int num) 2004 { 2005 WARN_ON(num >= MAX_CPU_FEATURES); 2006 return elf_hwcap & BIT(num); 2007 } 2008 EXPORT_SYMBOL_GPL(cpu_have_feature); 2009 2010 unsigned long cpu_get_elf_hwcap(void) 2011 { 2012 /* 2013 * We currently only populate the first 32 bits of AT_HWCAP. Please 2014 * note that for userspace compatibility we guarantee that bits 62 2015 * and 63 will always be returned as 0. 2016 */ 2017 return lower_32_bits(elf_hwcap); 2018 } 2019 2020 unsigned long cpu_get_elf_hwcap2(void) 2021 { 2022 return upper_32_bits(elf_hwcap); 2023 } 2024 2025 static void __init setup_system_capabilities(void) 2026 { 2027 /* 2028 * We have finalised the system-wide safe feature 2029 * registers, finalise the capabilities that depend 2030 * on it. Also enable all the available capabilities, 2031 * that are not enabled already. 2032 */ 2033 update_cpu_capabilities(SCOPE_SYSTEM); 2034 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2035 } 2036 2037 void __init setup_cpu_features(void) 2038 { 2039 u32 cwg; 2040 2041 setup_system_capabilities(); 2042 mark_const_caps_ready(); 2043 setup_elf_hwcaps(arm64_elf_hwcaps); 2044 2045 if (system_supports_32bit_el0()) 2046 setup_elf_hwcaps(compat_elf_hwcaps); 2047 2048 if (system_uses_ttbr0_pan()) 2049 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2050 2051 sve_setup(); 2052 minsigstksz_setup(); 2053 2054 /* Advertise that we have computed the system capabilities */ 2055 set_sys_caps_initialised(); 2056 2057 /* 2058 * Check for sane CTR_EL0.CWG value. 2059 */ 2060 cwg = cache_type_cwg(); 2061 if (!cwg) 2062 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2063 ARCH_DMA_MINALIGN); 2064 } 2065 2066 static bool __maybe_unused 2067 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 2068 { 2069 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); 2070 } 2071 2072 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2073 { 2074 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2075 } 2076 2077 /* 2078 * We emulate only the following system register space. 2079 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2080 * See Table C5-6 System instruction encodings for System register accesses, 2081 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2082 */ 2083 static inline bool __attribute_const__ is_emulated(u32 id) 2084 { 2085 return (sys_reg_Op0(id) == 0x3 && 2086 sys_reg_CRn(id) == 0x0 && 2087 sys_reg_Op1(id) == 0x0 && 2088 (sys_reg_CRm(id) == 0 || 2089 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2090 } 2091 2092 /* 2093 * With CRm == 0, reg should be one of : 2094 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2095 */ 2096 static inline int emulate_id_reg(u32 id, u64 *valp) 2097 { 2098 switch (id) { 2099 case SYS_MIDR_EL1: 2100 *valp = read_cpuid_id(); 2101 break; 2102 case SYS_MPIDR_EL1: 2103 *valp = SYS_MPIDR_SAFE_VAL; 2104 break; 2105 case SYS_REVIDR_EL1: 2106 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2107 *valp = 0; 2108 break; 2109 default: 2110 return -EINVAL; 2111 } 2112 2113 return 0; 2114 } 2115 2116 static int emulate_sys_reg(u32 id, u64 *valp) 2117 { 2118 struct arm64_ftr_reg *regp; 2119 2120 if (!is_emulated(id)) 2121 return -EINVAL; 2122 2123 if (sys_reg_CRm(id) == 0) 2124 return emulate_id_reg(id, valp); 2125 2126 regp = get_arm64_ftr_reg(id); 2127 if (regp) 2128 *valp = arm64_ftr_reg_user_value(regp); 2129 else 2130 /* 2131 * The untracked registers are either IMPLEMENTATION DEFINED 2132 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2133 */ 2134 *valp = 0; 2135 return 0; 2136 } 2137 2138 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2139 { 2140 int rc; 2141 u64 val; 2142 2143 rc = emulate_sys_reg(sys_reg, &val); 2144 if (!rc) { 2145 pt_regs_write_reg(regs, rt, val); 2146 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2147 } 2148 return rc; 2149 } 2150 2151 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2152 { 2153 u32 sys_reg, rt; 2154 2155 /* 2156 * sys_reg values are defined as used in mrs/msr instruction. 2157 * shift the imm value to get the encoding. 2158 */ 2159 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2160 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2161 return do_emulate_mrs(regs, sys_reg, rt); 2162 } 2163 2164 static struct undef_hook mrs_hook = { 2165 .instr_mask = 0xfff00000, 2166 .instr_val = 0xd5300000, 2167 .pstate_mask = PSR_AA32_MODE_MASK, 2168 .pstate_val = PSR_MODE_EL0t, 2169 .fn = emulate_mrs, 2170 }; 2171 2172 static int __init enable_mrs_emulation(void) 2173 { 2174 register_undef_hook(&mrs_hook); 2175 return 0; 2176 } 2177 2178 core_initcall(enable_mrs_emulation); 2179 2180 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2181 char *buf) 2182 { 2183 if (__meltdown_safe) 2184 return sprintf(buf, "Not affected\n"); 2185 2186 if (arm64_kernel_unmapped_at_el0()) 2187 return sprintf(buf, "Mitigation: PTI\n"); 2188 2189 return sprintf(buf, "Vulnerable\n"); 2190 } 2191